Download 1 CMOS Logic Gates

1. CMOS Logic Gates
1.1 Introduction
Fig.1.1 shows the characteristics of p-type and n-type
enhancement-mode MOS transistors. The polarity of voltages and
currents are shown for both types of transistor. It can be seen that the
voltages are positive in the n-type and negative in the p-type
(including the threshold voltage). It can also be seen that current flow
through the transistors is from drain to source in the n-type device but
from source to drain in the p-type device.
In the circuits that are of interest, which operate from a singlerail supply, the p-type device will appear upside-down in the circuit
configuration with respect to the n-type device. If the convention is
adopted for the p-type device to use the source-to-gate voltage, VSG,
and the source-to-drain voltage, VSD, as shown in Fig. 1.2, then the
same set of equations can be used to characterise both enhancement
mode devices where all voltages, including the threshold voltage VT
are considered positive.
iD
iD
iD
+ ive
D
G
VDS
S
VGS
+ ive
+ ive
+ ive
D
G
G
+ ive
VSG
+ ive
S
VGS
VDS
S
VSD
D
- ive
+ ive
- ive
n-channel
Fig. 1.2
p-channel
p-channel
Sign Conventions for p-type and n-type MOS Transistor
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iD
iD
+ ive
-ive
VGS ≤ VT
VGS  VT
VDS
VDS
p-channel enhancement
n-channel enhancement
n-channel enhancement
p-channel enhancement
D
D
iD
G
iD
G
S
S
VT
VDS
iD
+ ive
- ive
+ ive
- ive
D
S
S
D
VGS
+ ive
- ive
VGS -VT
+ ive
- ive
Fig. 1.1 Characteristics of Both Types of MOS Transistors
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1.2
Current-Voltage Relationships
A conducting channel is formed in the enhancement-mode device
when VGS > VT. If the above sign convention is adhered to, the same
set of equations can be used to describe the current-voltage
relationship for both n-type and p-type transistors.
Non-Saturation Region
n-channel




2
ID  K n 2VGS  VT VDS  VDS
p-channel
2
ID  Kp 2VSG  VT VSD  VSD
Saturation Region
n-channel
ID  Kn VGS  VT 
2
p-channel
ID  K p VSG  VT 
2
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The CMOS Inverter
The CMOS inverter is formed by connecting an n-type transistor
and a p-type transistor in series, with the p-type inverted to operate
from a single-voltage supply, as shown in Fig.1.3. The transfer
characteristic of the inverter is also shown. The critical logic voltages,
defined at the points on the characteristic where the slope is -1, can be
adjusted by changing the relative aspect ratios W/L of the two
transistors. Typically they are set at 20 – 25% and 75 – 80% of the
supply voltage.
If the nominal logic voltages are defined as VL = 0V and VH = VDD then:
If the input voltage is LO with Vi = 0V the gate-source voltage of the
lower n-type transistor, T1, is zero which is below the threshold
voltage, VT, and so this transistor is non-conducting or OFF. On the
other hand, the p-type transistor, T2, which is upside down, has a VGS
= -VDD or VSG = VDD which is well above the threshold voltage and so
this transistor is fully conducting or ON. Transistor T2 can then supply
current to any load required and with full conduction will give an
output voltage VO → VDD or a logic HI level.
When the input voltage is HI with Vi = VDD the gate-source voltage of
the p-type transistor is zero so that T2 is OFF, while the gate-source
voltage of the n-type transistor is equal to VDD and hence transistor,
T1, is fully conducting and is ON. With a sufficiently high
transconductance parameter the output voltage can be made very low
so that VO → 0V or logic LO. This results in an inverting action as
verified by the table below:
INPUT
T1
T2
OUTPUT
Vi = 0V,
LO
OFF
ON
VO
VDD, HI
Vi = VDD ,
HI
ON
OFF
VO
0V, LO
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VDD
Schematic
Diagram
T2
T1
Vi
VO
VO
VOH MIN
Tangents at
slope = -1
Transfer
Characteristic
VOL MAX
ViL MAX ViH MIN
Fig. 1.3
Vi
Schematic Diagram and Transfer Characteristic of a CMOS
Inverter
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1.4 The CMOS NOR Gate
The schematic diagram of a 2-input CMOS NOR gate is shown in
Fig. 1.4. It can be seen that the transistors are driven in p-type cum ntype pairs by each input. Essentially, the n-type driving transistors are
connected in parallel while the p-type load transistors are connected in
series. Within each pair, either the n-type transistor will be ON while
the p-type is OFF, or vice-versa, depending on the logic state of the
associated input. A table of conduction states for all transistors can be
drawn up to establish the logic function performed by the gate, as
shown below. The state of the output can be established by treating
the transistors which are ON as equivalent to closed switches and
those that are OFF as equivalent to open switches. This is shown, for
example, in Fig. 1.5 for the case where Input A is HI and Input B is LO.
IN A
IN B
T1
T2
T3
T4
OUT
LO
LO
OFF
ON
OFF
ON
HI
LO
HI
OFF
ON
ON
OFF
LO
HI
LO
ON
OFF
OFF
ON
LO
HI
HI
ON
OFF
ON
OFF
LO
1.5 The CMOS NAND Gate
The schematic diagram of a 2-input CMOS NAND gate is shown in
Fig. 1.6. It can be seen that the structure is similar to the NOR gate,
but in this case the n-type driving transistors are connected in series
while the p-type load transistors are connected in parallel. Transistors
are again driven in n-type cum p-type pairs with one transistor ON
while the other is OFF. A table of the conducting states of the
transistors for all logic combinations of the inputs is given below. The
switch equivalent is shown for the case where Input A is HI and Input
B is LO in Fig. 1.7
IN A
IN B
T1
T2
T3
T4
OUT
LO
LO
OFF
ON
OFF
ON
HI
LO
HI
OFF
ON
ON
OFF
HI
HI
LO
ON
OFF
OFF
ON
HI
HI
HI
ON
OFF
ON
OFF
LO
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VDD
T2
IN B
T4
OUT
T1
IN A
Fig. 1.4
T3
Schematic Diagram of a 2-input CMOS NOR Gate
VDD
T2
IN B
T4
OUT
IN A
Fig. 1.5
T1
T3
Equivalent Circuit of NOR Gate with IN A = HI and IN B = LO
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VDD
T2
T4
OUT
IN B
T3
IN A
Fig. 1.6
T1
Schematic Diagram of a 2-input CMOS NAND Gate
VDD
T4
T2
OUT
IN B
T3
T1
IN A
Fig. 1.7
Equivalent Circuit of NAND Gate with IN A = HI and IN B = LO
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