Download common emitter transistor amplifier

COMMON EMITTER TRANSISTOR AMPLIFIER
DESIGN AND ANALYSIS
Consider the generalised form of a Common Emitter Transister Amplifier.
Firstly considering the DC conditions (biasing) of the amplifier under quiescent
conditions (no input signal).
The object of the DC biasing is to get the voltage at the collector, Vc to be about mid
supply so that when a signal is applied to the input, Vc has the potential to swing equal
distance in both a positive and negative direction before saturation.
So Rb1 & Rb2 are sized to bias the voltage at the base, Vb to a particular voltage. The
voltage at the emitter, Ve is 0.65V below Vb. Ve across Re causes an emitter current, Ie
to flow. Lets assume that the emitter current, Ie equals the collector current, Ic. There is
then a voltage drop across the collector resistor, Rc equal to Ic*Rc. So if the base is
biased to the correct voltage and both Re and Rc are sized correctly then Vc will sit at
mid-supply under no signal conditions.
Now consider what happens to the collector voltage,Vc if the base is raised slightly by an
applied signal. Vb increases slightly. Ve must follow as it remains 0.65V below Vb. This
results in an increased emitter current, Ie (increased voltage across Re) which results in
an equally increased collector current through Rc resulting in Vc dropping. By a similar
mechanism, if the voltage at the base drops then the voltage at the collector will rise.
The ratio of a drop in Vc to the increase in Vb is equal to the ratio of the collector and
emitter resistors therefore we have a simple gain equation for the amplifier:-
Voltage gain, Av = -Rc / Re
Note that the amplifier is inverting (hence the minus sign), an increase in base voltage
causes a decrease in collector voltage and vice-a-versa.
Note also that the gain is independent of the hFE of the transistor. This is an advantage of
this type of amplifier.
Design of an Amplifier.
At this point we can design an amplifier and allocate actual values to the components.
Step 1
Choose a power supply voltage value (Vcc).
Lets choose 9V.
Step2
Choose a value for the collector current, Ic.
This current should be in the order of a few mAs. Say somewhere between 1mA and
5mA.
Lets choose 3mA.
Step3
Calculate the value of the collector resistor, Rc.
To put the quiescent collector voltage, Vc at mid supply (4.5V)
Rc = (Vcc – Vc)/Ic
Rc = (9 - 4.5)/3mA = 1K5
Note that in this configuration of amplifier Rc equals the output resistance of the
amplifier (Rc = Rout) and it can be seen that a higher chosen value for Ic results in the
advantage of a lower output resistance. The disadvantage of a higher Ic is that more
power is drawn from the supply.
Step 4
Decide on a value of amplifier gain assuming no emitter bypassing. Emitter bypassing is
discussed later on.
A typical value for the gain with no emitter bypassing would be somewhere between 2
and 10.
Lets choose Av to be 5.
Step 5
Calculate a value for the emitter resistor assuming a gain of 5 and using the equation :
Av = Rc / Re
Re = 1K5 / 5 = 300R
Assume Ie = Ic.
This puts the emitter voltage, Ve at Ie * Re
Ve = 3mA * 300R = 0.9V
Somewhere around 1V is a typical value for the emitter voltage in this type of amplifier.
Step 6
Calculate the size of the two base bias resistors.
The base needs to be biased to 0.65V above the emitter voltage, Ve.
Therefore Vb = 0.9V + 0.65V = 1.55V
The usual way of assigning values to the base bias resistors is to make the bias current,
Ibias 10 times the value of the base current. This is done so that the voltage divider at the
base is “stiff” enough to make Vb substantially unaffected by the base current.
Ib = Ic / hFE
Assume hFE is 290. The four BC549Bs I measured all had hFEs of about 290 at an Ic of
3mA and this agrees with the data sheet specified typical hFE value at this collector
current.
Ib = 3mA / 290 = 10.3uA
Ibias = 10 * 10.3uA = 103uA
So
Rb1 + Rb2 = 9V / 103uA = 87K4
Using potential divider law…
Voltage at base = Vcc * Rb1 / (Rb1+Rb2)
But
Rb1 + Rb2 = 87K4
Therefore Rb1 = (1.55V * 87K4) / 9V = 15K
And Rb2 = 72K4
At this point I briefly deviate from the conventional design process.
The base bias resister values that I actually use in my design are 22K & 91K rather than
those values calculated above. The reason for doing this is to increase the input resistance
somewhat. Rb2 was increased by a larger amount proportionally, from the calculated
value, than Rb1 was, in order to compensate for the “de-stiffening” of the potential
divider (loading down of it by the base current due to the higher resister values) and bring
the base bias voltage, Vb back up to 1.55V. These higher resister values give an Ibias of
about 82uA.
Step 7
Calculate a more precise gain.
Av = -Rc/Re is only a rough estimate of the gain. A more accurate estimate of the gain
is:Av = -Rc/(Re+re)
Where re is the transistor’s intrinsic emitter resistance.
re = 26mV/Ie
Where Ie is in mA.
re = 26mV/3mA = 8.7 Ohms
So the more accurate equation for Av is :Av = -1K5/(300+8.7) = -4.86
Not much different to the approximate equation (Av = -Rc/Re) because re is small
compared to Re.
Step 8
Calculate the new gain with a load added.
Another factor that affects the gain of the amplifier is the load that it is driving. I will now
add a 5K load to the amplifier’s output representing the input impedance of a following
amplifier stage.
The added load doesn’t affect the DC biasing.
This load appears in parallel with Rc reducing the effective value of Rc and therefore
also reducing the gain. The new gain equation is now ...
Av = -(Rc//RL)/(Re+re) = -3.74
even lower as expected.
Step 9
Calculate the gain with a partially by-passed emitter.
The trick to increase the gain significantly is to split the emitter resistance and
bypass the lower part with a capacitor, C3. C3 is a short to AC (the signal) but open
to DC (the biasing). Therefore adding C3 doesn't affect the DC bias conditions
(keeping the centre voltage at the collector mid-supply for equal maximum possible
+ve and -ve output swings) but Re has now become just Re1 because Re2 is
effectively shorted out as far as the signal is concerned.
Av now equals -(Rc//RL)/(Re1+re) our final accurate gain equation.
re has now become more significant in the gain calculation as it is fairly large
compared with Re1.
Av = -(1.5K//5K)/(30+8.7) = -29.8
The more bypassed emitter resistance you have, the higher the gain. It's possible to
bypass all the emitter resistance but the drawback of doing this is distortion.
I simulated the circuit in Circuit Wizard and also breadboarded a real version. Both
techniques agreed with the theoretically calculated gain of -30.
Step 10
Calculate the input and output resistance.
It can be useful to know the input and output resistance of an amplifier.
Rout is simply equal to Rc as already stated.
Rout = Rc = 1K5
Input resistance, Rin = Rb1//Rb2//(hFE*(Re1+re))
Rin = 91K//22K//(290*(30+8.7)) = 6K9
Step 11
Calculate the capacitor values required for overall –3dB frequency of about 30Hz.
We nearly have the final design. The only thing left to do is to calculate the values of the
3 capacitors.
There are three high pass filters in the circuit formed by the 3 capacitors acting with
their associated resistances, R.
The cut off frequency of each filter is:fc(-3dB) = 1 / (2*pi*R*C)
So if the –3dB frequency of each filter is to be 20Hz then the capacitor value is :C = 1/(2*pi*R*20)
Where R is each filter’s associated resistance.
For the output coupling capacitor, C2.
R = Rc + RL = 1K5 + 5K =6K5
Therefore C2 = 1 / (2*pi*6K5*20) = 1.2uF
For the input coupling capacitor, C1.
R = Rs + Rin
Rs is the signal source resistance which is the output resistance of the previous
stage.
For this calculation I’ll assume Rs = 0.
Therefore C1 = 1 / (2*pi*6K9*20) = 1.1uF
For the bypass capacitor, C3.
R = Re2//((Re1+re)+((Rb1//Rb2//Rs)/hFE))
If, as before we assume that Rs is zero then the last term in the equation dissapears
and the equation simplifies to :R = Re2//(Re1+re) = 270//(30+8.7) = 34R
Therefore C3 = 1 / (2*pi*34*20) = 234uF
Nearest prefered value is 220uF. (E6 range).
That isn’t the whole story though because these 3 filters are effectively cascaded
giving –9dB drop at 20Hz. The overall –3dB frequency is roughly the sum of the
three filters’ –3dB frequencies or somewhere around 60Hz.
We can achieve a more desirable overall –3dB frequency of about 30Hz by increasing
the size of the input and output coupling capacitors to values of 4.7uF.
Now f(-3dB) due to C1 = 1/(2*pi*6K9*4.7u) = 4.9Hz.
f(-3dB) due to C2 = 1/(2*pi*6K5*4.7u) = 5.2Hz.
f(-3dB) due to C3 = 1/(2*pi*34*220u) = 21.3Hz.
Overall –3dB freq is approx equal to 21.3Hz + 4.9Hz + 5.2Hz = approx 30Hz.
Step 12
Draw finalised design.
To cater for a different supply voltage all we need to do is change the base bias
voltage, Vb in order to keep the collector voltage, Vc at the new mid-supply voltage.
We can easily do this by altering the ratio of Rb1 to Rb2.
Rc, Re1 and Re2 can remain unchanged keeping the amplifier’s gain constant.