Download Test Circuit for Locating Open Leads of QFP ICs

Test Circuit for Locating Open Leads
of QFP ICs
M.Hashizume,
M.Ichimiya,
A.Shimoura,
H.Yotsuyanagi
The Univ. of Tokushima, JAPAN
-1-
Outline
1. Background
2. Our targeted problem:
=open lead location of CMOS QFP ICs
3. Our test method
4. Our test circuit and the design method
5. Feasibility of test circuit design
6. Conclusion
-2-
Background
Many logic circuits are implemented with fine-pitch QFP ICs
and a PCB of fine line layout.
(ex.)circuits that downsizing and high performance are not
requested strongly
solder bridging
Now, 0.4mm
pattern
short
open lead
peeling-off pattern
Open leads of QFP ICs occur more frequently in soldering
process.
[Targeted Defects]
Open lead of QFP ICs occurring in soldering process
-3-
Our Targeted Problem
Our targeted tests: Tests in subcontract soldering factories
 CUTs: circuit s made of QFP ICs in which downsizing and high performance
are not requested strongly
 Difficulty:
o Boundary scan technology may not be introduced in QFP ICs.
o Test vectors are provided from ordering manufactures and can not be generated
in the factories, since detailed information for test generation is not supplied.
Soldering process should be optimized for each kinds of
circuits.
[Requirements]
 powerful and expensive testers
 test vectors and/or test generation for locating open leads
Development of vectorless test method for locating
open leads
-4-
Test Method Proposed in BTW’07
Test based on supply current of our test circuit
Test process:
[1]Attach a test probe to the top of a targeted input lead
[2]Provide AC signal
[3]Measure iDDT(t)
[4]If Eq.(1) is satisfied, an
open occurs at the
targeted input lead.
iDDT(t)≥Ith
(1)
(rms)Open at an output lead
is detected as open at an
input lead.
-5-
Property Used in Our Test
If either Vi=VDD or Vi=0V, IDD=0
If Vi1<Vi<Vi2, large supply current flows into a CMOS INV
ICs.
nMOS:off
pMOS:off
VDD
IDD
Vo
Vo
IDD
IDD
Vi
(a)Measurement Circuit
Vo
Vi1
Vth
Vi2
Vi
(b)DC characteristics
-6-
Principle of Open Lead Detection
When an open occurs at an input lead,
vINV(t) will depend on vs(t).
When Vi1<vINV(t)<Vi2, elevated iDDT(t) will flow.
(a)Test of open lead
(b)iDDT(t) waveforms
-7-
Tests of Defect-free Circuits
vINV(t) depends on output voltage from IC#i-1 and iDDT(t) ≈0.
If either H or L is outputted to a targeted lead,
the lead will be judged as defect-free.
(a)when L is outputted
(b)when H is outputted
-8-
Test Circuits for Detecting Opens in BTW’07
Purpose: detect more than one lead simultaneously
(a)Test circuit for locating open (b)Test circuit for detecting open
-9-
Necessity of RT
If a CUT is defect-free, elevated iDDT(t) may flow and the CUT
may be destroyed when H and L are outputted.
RT’s make
this current small.
[Our new approach]
This circuit is used for
locating open leads.
- 10 -
Drawback of Our Test Circuit in BTW’07
When high-Z is outputted to a targeted lead in a defect-free
circuit, the lead will be judged as defective.
= Test vector generation and application are indispensable.
Elevated
iDDT flows.
high
Z
(a)when high-Z is outputted
(b)when open lead occurs
- 11 -
Our Purposes
a. Revise test circuit proposed in BTW’07 so that expected
test results can be derived even if high-Z is outputted.
b. Develop test circuit design method for locating open leads
Pull-up circuits are added
revised
(a)Test circuit in BTW’07
(b)Revised test circuit
- 12 -
Our New Test Method
 Principle:
Tests with high-Z output leads pulled-up
(ex.)Lead c is pulled-up
by Sel2=H
Pull-up circuits
L
H
L
≈0
ON
 Test process:
1. Test stage #1:
Purpose: Locate leads of high-Z signal
and open leads
2. Test stage #2:
Purpose: Locate open leads
from leads derived
in Test stage#1
- 13 -
Test Stage#1
Purpose: locate open leads and high-Z ones
Test procedure:
[1]All of the targeted leads are pulled-up
(Sel1,Sel2,Sel3)=(H,H,H)
[2]For each of targeted leads,
 Pull-up switch of i-th lead is turned off
by Sel#i=L.
 If iDDT(t)≥Ith, Sel#i=H.
(ex.) Example of tests
Test
iDDT targeted
Sel11 Sel12 Sel13
judgement
Seq.
level
lead
1
H
H
H
low
2
L
H
H
low
a
not opened
3
L
L
H
high
c
opened or High-Z
4
L
H
L
low
f
not opened
Results: (Sel1,Sel2,Sel3)=(L,H,L)
- 14 -
Test Stage#2
Purpose:
Locate open leads by attaching a pull-up
circuit to the input leads of targeted ones
Test Stage#1 Test Stage#2
L
H→L
L
off
Test Procedure:
[1]Pull-up circuit is attached to targeted leads
[2]For each of leads of Sel#i=H,
 pull-up switch of only the i-th lead is turned
off by Sel#i=L.
 if iDDT(t)≥Ith, it is determined that
open lead occurs at the i-th lead and
Sel#i=H.
(ex.) (Sel1,Sel2,Sel3)=(L,H,L)
Even if high-Z signals are outputted,
defect-free circuits will be judged as defect- free
by attaching the pull-up circuit.
ON
off
off
H
Z
L
H
H
L
- 15 -
Example of Open Lead Location
Test Stage#1
L
H
H
Test Stage#2
L →L →L
H→L →H
ON
off
H→H→L
on
ON
off
(a) test stage#1
It can be judged what leads are opened
even if high-Z signals are outputted.
H
Z
L
H
H
??
(b) test stage#2
- 16 -
Test Circuit Design
Goal: specify RT for defect-free circuits to be judged as
defect-free.
L
off
L
pull-up
circuit for
H output
m-parallel
off
n-parallel
pull-down circuit for L output
(b)Equivalent circuit
H
L
(a)Test circuit in test stage#1
# of H output leads =m
# of L output leads = n
(c)Equivalent circuit of (b)
- 17 -
Conditions to be Satisfied
vS(t) [V]
3.0
0
-3.0
vINVH(t),vINVL(t) [V]
Conditions for defect-free
circuits to be judged
as defect-free:
 min(vINVH(t))>Vi2
(2)
 max(vINVL(t))<Vi1
(3)
0
5.0
1.0
2.0
vINVH(t)
Vi2
min(vINVH(t))
Vi1
vINVL(t)
0
-1.0
1.0
0
max(vINVL(t))
(a)Equivalent circuit
time[ms]
time[ms]
2.0
(b)Input voltage of INVs
in defect-free circuit tests
- 18 -
Test Circuit Design
Test circuit design for N(=m+n) leads
m: # of H outputted leads
worst-case
n: # of L outputted leads
design
min( vINVH (t ))  Vi 2
for m=N-1,n=1
max( vINVL (t ))  Vi1
for m=1,n=N-1
where
VINVH 
VINVL 
mRS RnonVDD  RtpRnonVS
mRS Rtn  RtpRtn  nR s Rtp
VDD
IDD
Vi
Vo
(a)Measurement Circuit
nMOS:off
Vo
pMOS:off
Vo
IDD
(mRS Rtn  RT Rtn  nRS RT ) VDD  RtnR ponVS
Rtp  RT  Rpon
Rtn  RT  Rnon
IDD
mRS Rtn  RtpRtn  nR s Rtp
Vi1
Vth
Vi2
(b)DC characteristics
- 19 -
Experimental Evaluation
Purpose: Examine feasibility of
our test circuit design
CUT: # of leads =50
[Specifications]
 VDD=5.0, Vi1=0.8, Vi2=4.2,
Rpon=2.3k, Rnon=3.0k from IC#i-1
 Vs=VDD/2=2.5, Rs=100
Derivation of RT
 RT≥9.3k from min(vINVH)>Vi1,
 RT≥23.5k from max(vINVL)<Vi2
RT=26k
- 20 -
Evaluation Results
Evaluation by Spice simulation with RT=26k
(a)defect-free circuit
VSD: Voltage of open lead
(b)circuit having an open lead
Expected test results are obtained with the test circuit
designed by our design method.
- 21 -
Conclusion
A new test circuit for locating open leads of CMOS QFP ICs
[features]
 Simple test circuit
 Vectorless test method
Open leads can be located in subcontract soldering factories.
Test circuit design method
[Evaluation by SPICE simulation]
 50 leads are tested with the test circuit designed by our design method
successfully.
Future works
Development of test probes
Open lead location in real ICs with our test circuit
- 22 -