Download JFET Amplifier

Lab 4. JFET Amplifier
I. Overview
In the Lab 3 and Lab 4 you are designing a two-stage amplifier as shown in Figure 1.
After the BJT amplifier in the last two weeks, we will design and build JFET (Junction Field
Effect Transistor) amplifier and connect it with the BJT amplifier to create a two-stage amplifier.
Feedback resistor will be introduced to control the total gain of the amplifier.
Figure 1. Two-Stage Amplifier Schematic with Feedback
As we have seen from the BJT amplifier, the gain is around 200 V/V. Distortion in the
output voltage is observed with the minimum input voltage of 100 mVpp available in the
experiments.
In this lab, we can see that JFET amplifier has a gain usually less than 10. Because of the
high input impedance and low noise, JFET is usually used as the first stage in a multi-stage
amplifier to pick up weak input signals.
The total gain of the two-stage amplifier is the product of the gains of the individual JFET
1
and BJT amplifier. It is obvious that the total gain will exceed 200 V/V and more distortion in
the output voltage of the two-stage amplifier will be observed. By introducing negative feedback
units, feedback resistor Rf, the total gain can be easily adjusted by varying the resistance of Rf.
II. JFET Amplifier Design
You will design a Common Source JFET amplifier shown in Figure 2. Based on the
current-voltage characteristic of the JFET (2N5459), each group should select a proper operation
point (Q-point) and determine the values of the biasing resistors, such as R2, R3 and R1.
DC power supply Vcc = 20 volts, all capacitance as 100 uF.
R2
R3
Figure 2. Common Source Junction FET Amplifier
2.1 Task of the first week: Calculation and Simulation
1. Obtain current-voltage characteristic of JFET and determine the load line and Q-point
a. Each group picks up one n-channel JFET (2N5459) and plugs it into the curve tracer. The
settings of curve tracer: type  n-channel; Vds-max  20V; Is-max  5mA; Vg/step 
0.2 V; Offset  -2.5 V; # of steps  10; Rload  0.25 ; power  0.5 watt;
2
b. Select an operation point (Q-point) with Vds = Vcc/2 and Id in the range of 2 mA  5
mA. Display the values of Vgs, Vds and Id at the Q-point on the screen and obtain a
hard copy of the screen.
c. Draw the DC load line on your printout by manually connecting the Q-point and the point
with Vds = 20V and Id = 0mA.
d. Find the Early voltage VA. Get the Vds and Id values of another point on the same output
 I V  I V 
curve as the Q-point you choose. V A   d 1 ds2 d 2 ds1 
Id 2  Id1


e. The AC output resistance ro 
VA
, where Id is the drain current at Q-point.
Id
2. Determine the DC biasing resistors and AC voltage gain
f. Determine source resistance R3, the drain resistance R2 and gate resistance R1
From the circuit shown in Figure 2, we have
VCC  VR2  Vds  VR3  I d  R2  Vds  I d  R3 and Vgs  Vg  Vs  0  I d  R3
Vgs
V  Vds
Then R3  
, and R2  CC
- R3
Id
Id
where Vgs, Vds and Id are the values at Q-point
R1 is chosen on the order of Ms to maintain the benefit of high input impedance of the
JFET transistor. 1 ~ 3 M will be a good choice.
g. Draw the small signal model of the JFET transistor as Figure 5.34 (b) in the textbook.
Give an estimation of g m 
I d
based on the output curves obtained from curve tracer.
V gs
h. Find the voltage gain of JFET amplifier Av, given as
V
ro  R2 // Rin 
Av  FET  out   g m 
  g m  R2 // Rin 
Vin
ro  R2 // Rin   R3
where Rin is the input impedance of the BJT amplifier, Rin  R4 // R5 // r ,
R4 , R5 and r obtained from Lab 3 : BJT Amplifier, r 
3
 VT
IC
3. Simulation of the JFET amplifier
i. Create and simulate the schematic of Figure 2 in OrCAD – Capture. All the capacitors
have the value of 100 uF. The AC input is VSIN with settings: Voffset = 0, Vampl =
50mV and f = 1kHz. The output of the amplifier is loaded with a resistor Rin. Capture
the input and output voltages in Pspice and determine the peak-peak voltages and
voltage gain of the single JFET amplifier, Av-FET.
j. Compare the voltage gain from simulation with that from the theoretical calculation.
4. Simulation of the two-stage amplifier without feedback resistor Rf
k. Connect the JFET amplifier with the BJT amplifier to get a two-stage amplifier as shown
in Figure 1 except the feedback resistor Rf. The load resistor RL is 10 k. Rin is NOT
needed in this step.
l. Simulate the two-stage amplifier under the input signal VSIN with Voffset = 0, Vampl =
50mV and f = 1kHz. Capture the input and output voltages in Pspice.
m. Simulate the two-stage amplifier again under the input signal VSIN with Voffset = 0,
Vampl = 5mV and f = 1kHz. Capture the input and output voltages and determine
the peak-peak voltages and the voltage gain of the two-stage amplifier, Av-total.
n. Compare the voltage gain of the two-stage amplifier from simulation with the theoretical
value, Av  total  Av  BJT  Av  FET .
5. Determination of the feedback resistor Rf
o. The total voltage gain of the two-stage amplifier, Av-total, found above is under the
open-loop (without feedback) condition. This gain is determined by the properties of the
two transistors and the amplifier configurations. To be capable of varying the gain in a
large range and stabilizing the two-stage amplifier, negative feedback is always
introduced, as the feedback resistor Rf in Figure 1.
For a system with an open-loop gain of Avo (Av-total in our lab), adding feedback will
change the gain of the system to Av (Av-FB in our lab), the closed-loop gain. Av and Avo
can be related by Av 
Avo
R3
, where  
1    Avo
R3  R f
To get a desired gain Av of the feedback system, we first need to find the feedback
4
Avo
1
Av
ratio  
, where Avo (Av-total found in step m) is the open-loop gain of the
Avo
two-stage amplifier without feedback, Av (Av-FB in this lab) is the desired closed-loop
gain of the amplifier with feedback resistor Rf. In this lab, Av-FB is given as 50 V/V.
R
p. Finally the feedback resistor Rf can be determined by R f  3  R3

6. Simulation of the two-stage amplifier with feedback resistor Rf
q. Add feedback resistor Rf to the two-stage amplifier as shown in Figure 1. Simulate the
circuit under the input signal VSIN with Voffset = 0, Vampl = 50mV and f = 1kHz.
Capture the input and output voltages and determine the peak-peak voltages and
the closed-loop voltage gain, Av-FB.
r. Compare the closed-loop voltage gain Av-FB obtained from simulation with the desired
value, 50 V/V in this lab.
2.2 Task of the second week: Testing
1. Testing of the JFET amplifier
s. Fabricate and test the hardware circuit as in Figure 2. The input signal from the Function
Generator is 100 mVpp and the frequency is 1 kHz. Measure the input and output
voltages on the scope and capture to Word or Excel file showing the peak-peak
values for both signals.
2. Testing of the two-stage amplifier without feedback resistor Rf
t. Connect the JFET amplifier with the BJT amplifier as shown in Figure 1 except the
feedback resistor Rf. The input signal from the Function Generator is 100 mVpp and the
frequency is 1 kHz. Measure the input and output voltages on the scope and capture
to Word or Excel file showing the peak-peak values for both signals.
3. Testing of the two-stage amplifier with feedback resistor Rf
u. Add the feedback resistor Rf as shown in Figure 1. Measure the input and output
voltages on the scope and capture to Word or Excel file showing the peak-peak
5
values for both signals.
III. Report
One lab report is required for the two-week experiment:

Introduction

Schematic

Capture from curve tracer. Please indicate Q-point, load line and data for Q-point

Calculations of VA, ro, R2, R3, gm, Rin and Av-FET. Please show the procedures not just the
results

Calculations of Av-total, β and Rf

Simulation results of single JFET amplifier. Please show both input and output voltages and
indicate both the peak-peak voltages and the voltage gain

Simulation results of two-stage amplifier without feedback

Simulation results of two-stage amplifier with feedback

Measurements of single JFET amplifier. Capture of both input and output voltages with Vp-p
displayed. Calculated the voltage gain from measurement results

Measurements of two-stage amplifier without feedback

Measurements of two-stage amplifier with feedback

Comparisons
between
theoretical
calculation,
measurements, discussion and conclusion
6
PSpice
simulation
and
hardware