Download Design_Logic_Probe

Survey
yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project

Document related concepts

Power engineering wikipedia , lookup

Ground (electricity) wikipedia , lookup

Flip-flop (electronics) wikipedia , lookup

Control system wikipedia , lookup

Stepper motor wikipedia , lookup

Power inverter wikipedia , lookup

Electrical ballast wikipedia , lookup

Signal-flow graph wikipedia , lookup

Variable-frequency drive wikipedia , lookup

Islanding wikipedia , lookup

Three-phase electric power wikipedia , lookup

Immunity-aware programming wikipedia , lookup

Ohm's law wikipedia , lookup

Electrical substation wikipedia , lookup

Two-port network wikipedia , lookup

P–n diode wikipedia , lookup

History of electric power transmission wikipedia , lookup

Analog-to-digital converter wikipedia , lookup

Current source wikipedia , lookup

Power MOSFET wikipedia , lookup

Integrating ADC wikipedia , lookup

Rectifier wikipedia , lookup

Triode wikipedia , lookup

Power electronics wikipedia , lookup

Resistive opto-isolator wikipedia , lookup

Test probe wikipedia , lookup

Metadyne wikipedia , lookup

Surge protector wikipedia , lookup

Alternating current wikipedia , lookup

Buck converter wikipedia , lookup

Voltage regulator wikipedia , lookup

Stray voltage wikipedia , lookup

Voltage optimisation wikipedia , lookup

Switched-mode power supply wikipedia , lookup

Schmitt trigger wikipedia , lookup

Mains electricity wikipedia , lookup

Opto-isolator wikipedia , lookup

Transcript
Experiment 20
Design a logic probe as shown in the block diagram of Figure 1 with
a signal input lead, a ground lead, and a power input lead.
The logic probe should have three output LEDs. Only one LED at a
time should light when the input is a steady DC level between zero
and +5 V.
– LED 1 should light when the input voltage is below 0.8 V.
– LED 2 should light (a) when the input is open (floating) or (b) when the
input voltage is between 0.8 and 2.2 V.
– LED 3 should light when the input voltage is above 2.2 V.
• All voltage levels have a tolerance of approximately ±12%.
Ideally, your design should use only one LM324 chip.
You may use all four of the LM324's op amps on the
chip. No extra credit will be awarded.
You may use either the +5 or +9V ANDY board supply or a DC
voltage supplied by the Velleman function generator.

In addition to the circuit with the voltage
comparators, you must design and construct a
voltage divider so that you can vary the input
voltage to the logic probe during validation using a
100 kW trim pot.


Explanation of the principles applied in the circuit design.
Schematic diagram of the circuit that you designed using
PSpice (i.e., not drawn by hand).
 Schematic diagram that show the bias voltages (Procedure Part B, step 6).
• Schematics should also include the locations of any PSpice voltage and/or
current markers.

PSpice screen snapshots of:
 A graph of the input voltage to the logic probe versus the output voltages
from the op amps (Procedure Part B, step 7). The graph should cover the
entire range of voltages that illustrate all three logic levels (i.e., a DC
Sweep).
 A graph of logic probe input voltage versus the voltage across the series
combination of an LED and its current limiting resistor using at least one
PSpice differential voltage probe (Procedure Part B, step 8) or an
equivalent trace expression.
 A graph of logic probe input voltage versus the current through each of
the three LEDs (Procedure Part B, step 9).


The material from your pre-lab.
A table of the input voltages that turn on and turn
off each LED and a discussion of the hysteresis of
these voltages.
 If there is significant hysteresis, an explanation on how might
you modify your design to eliminate these effects.

A conclusion that states whether you circuit met the
design specifications and what some of the causes
that contributed to issues with the circuit operation.