Download B++--The Design of A Low-Power Low-Noise Phase Lock

文档下载 免费文档下载
http://www.wendangwang.com/
本文档下载自文档下载网，内容可能不完整，您可以点击以下网址继续阅读或下载：
http://www.wendangwang.com/doc/a25eb73104264e90a50e40e9
B++--The Design of A Low-Power Low-Noise Phase Lock Loop
The Design of A Low-Power Low-Noise Phase Lock Loop
Abishek Mann, Amit Karalkar, Lili He, and Morris Jones
Department of Electrical Engineering San Jose State University, CA, USA
Abstract
A phase lock loop is a closed-loop system that causes one system to track with another.
More precisely, a PLL can be perceived as a circuit synchronizing an output signal
with a reference or input signal in frequency as well as phase. High-performance phase
lock loops are widely used within a digital system for clock generation, timing
recovery, and to efficiently sequence operations and synchronize between function
units and ICs As the digital system grows the role of phase lock loop increases.
Achieving low jitter and phase noise in phase lock loop with less area and power
consumption is challenging. The present research relates to characterization and
redesign of individual blocks of Phase lock loop (PLL) to improve its characteristics.
Morehttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9
specifically
redesigning of individual blocks like: Phase Frequency Detector to reduce area and
static phase error, Voltage to Current converter to linearly increase the current
文档下载 免费文档下载
http://www.wendangwang.com/
input to the current controlled oscillator, Current Controlled Oscillator to reduce
phase noise, amplitude distortion, area and power consumption. We also introduce an
additional feedback loop to increase the gain of the charge pump in a manner that
linearizes the overall loop gain over wide bandwidth. The Results are substantial
improvements in the PLL characteristics such as low jitter, phase noise, area and
power consumption.
reference signal remains constant or is zero However, if in the process due to some
discrepancy a phase error builds up, a control mechanism gets triggered, which acts
on the oscillator to counter-balance the so resulted phase error in such a manner
that it is reduced to minimum until it is matched. As, the control system
http://www.wendangwang.com/doc/a25eb73104264e90a50e40e9actually locks (matches)
the phase of the output signal to the phase of the reference or the input signal.
Hence the name, “Phase-locked loop”. It is important here to note that, the PLL
not only sets a fixed relationship between its output clock phase and the input or
reference clock phase but also tracks the subsequent phase changes that are within
its bandwidth. Due to its characteristics, the PLL is used for communication network
systems and other circuits that require a clock recovery, frequency multiplier, and
data synchronization. It provides the system and circuit engineers with a greater
degree of freedom to generate well-timed on-chip clocks in high-performance digital
systems.
3. PLL Components
A basic block of PLL as shown in figure 1 consists of five fundamental blocks, namely,
Phase detector, Charge pump, Loop filter, voltage controlled oscillator and the
divider
network.
The
individual
building
blochttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9ks are explained to
understand the generic block diagram representation of a
文档下载 免费文档下载
http://www.wendangwang.com/
basic PLL in a much wider sense [7].
Keywords
Phase Lock loop (PLL), Phase Frequency Detector (PFD), Voltage to Current converter
(V2I), Current Controlled Oscillator (ICO)
1. Introduction
A PLL is essentially a negative feedback loop that locks the on-chip clock phase to
that of an input clock or signal [1]. High-performance PLL’s are widely used within
a digital system for clock generation, timing recovery, and to efficiently sequence
operations and synchronize between function units and ICs [2]. Clock frequencies and
data rates have been increasing with each generation of processing technology and
processor architecture. Within these digital systems, well-timed clocks are
generated with phase-locked loops (PLLs) and then distributed on-chip with clock
buffers.
The
rapid
increase
of
the
system’s
clock
frequenchttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9y poses challenges
in generating and distributing the clock with low phase noise and low power [3].
Figure 1 : Basic Compoments of PLL
3.1 Phase Detector
The primary purpose of the phase detector (PD) is to compare the phase of the periodic
input signal against the phase of the voltage controlled oscillator (VCO) and
accordingly generates a subsequent error signal which is proportional to the phase
deviation between them. The difference voltage (error signal) is then filtered by
文档下载 免费文档下载
http://www.wendangwang.com/
the loop filter and applied to the divided down output from VCO [8].
2. PLL Definition
A PLL can be perceived as a circuit synchronizing an 3.2 Charge Pump
output signal (generated by an oscillator) with a reference or input signal in
frequency as well as phase [4]. In the synchronized state, often referred to as “the
locked state”, the phase error between the output signal and the input
or://www.wendangwang.com/doc/a25eb73104264e90a50e40e9r
The charge pump coupled to a phase detector block is a vital building block in the
design topology. It helps provide an effective controlling mechanism for the charging
and discharging of the low pass filter. It is used to manipulate the
978-1-4244-6455-5/10/$26.00 ?2010 IEEE
528 11th Int’l Symposium
on Quality Electronic Design
amount of charge on the loop filter’s capacitors depending on the lead (UP) and lag
(Down) error signals generated from the phase detector [8].
4.1 Implementation/Redesign of High Speed Low Power Phase Frequency Detector
Implementation of low power high speed PFD using TSPC (True Single Phase Clock)
positive edge triggered D
The Loop filter included in design architecture is a passive Flip Flop is shown in
figure 3. The operating range of this device comprising of two capacitors and a
resistor.
The
PFD
is
up
to
1
GHz
with
no
extra
circuitshttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9 added. The PFD
output voltage generated from the loop filter informs the are designed using 0.18u
文档下载 免费文档下载
http://www.wendangwang.com/
technology with 1.8V as the power VCO to adjust its frequency (increase/decrease)
in such a supply.
manner that the voltage output is maintained proportional to
the charge of the
capacitors. The introduction of additional capacitor serves to reduce the incoming
noise from the 3.3 Loop filter
previous components and further helps in the reduction of the lock time.
It is imperative to note that the output translated from the phase detector consists
of a DC component and a superimposed AC component. Thus, the low pass filter is one
of the key design components which serve to effectively filter out the undesired AC
component and provides a steady control voltage for the VCO to operate with.
3.4 Voltage Controlled Oscillator
The
voltage
controlled
oscillators
is
the
most
important
device
componhttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9ent of this prolific
feedback system that helps produce the essential frequency output (Fout) of the PLL.
Depending on the control voltage of the low pass filter, the VCO generates the
frequency that matches the reference signal.
3.5 Loop Divider
An efficient Divider circuit provides a greater degree of
flexibility to the design engineers by allowing them to effectively operate a given
PLL at a higher frequency. Being an integral part of the feedback loop, the divider
configuration also serves as an optimum solution to reduce the frequency from the
VCO into a value that can be comparable to the reference signal. Thus, as the operation
range for the crystals is usually not more than a few 100 MHz, while the VCO’s
generally works in the range of a few tens of GHz, the loop divider block completes
the dynamic design of a basic PLL.
文档下载 免费文档下载
http://www.wendangwang.com/
4. Proposed PLL Architecture and sub blocks
Figure
2:
Proposed
PLL
Archihttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9tecture
The proposed PLL architecture is shown in figure 2.
Mann et al, The Design of A Low Power Low Noise…
Figure 3: Implementation of TSPC D flip flop with low true
Reset
From the architecture of FPD the data pin of D flip flop is always connected to VDD.
The node voltage node X is always 0, also the charges only when my D goes to 0 (not
possible in this case since D is connected to Vdd). The
transistors before node X and also below Node X can be removed. The proposed
architecture is shown in figure 4. The Proposed architecture reduces dead zone (less
than 30ps), steady state error, area and power consumed.
文档下载 免费文档下载
http://www.wendangwang.com/
Figure 4: Proposed architecture of TSPC D flip flop with low
true Reset
4.2 V2I
The Voltage to current converter block is used to convert
voltage
(control
voltage
Vctrl)
to
current.
IIhttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9CO the current generated
from the V2I block is used to control the output frequency of the Current Controlled
Oscillator.
Fout = IICO / (N * Ctotal * Vdd)
Fout is the output frequency of the ring oscillator. N is the number of stages in
the ring oscillator. Ctotal is the total node capacitance between two current starved
inverters. As the current IICO increases the output frequency increases. Now the
question is how to increase the current linearly such that the Fout increases linearly.
The device to which the Vctrl is applied should have a linear relationship between
the current produced and the voltage applied to the device. MOS is a non – linear
device, the resistor on the other hand is a linear device with linear relationship
between the voltage applied 4.3 Feedback
The Feedback block helps in linearizing gain and to remove the non linearity of the
VCO.
The
gain
of
the
charge
文档下载 免费文档下载
http://www.wendangwang.com/
pumhttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9p
is
controlled
by
current controlled oscillator input current in a manner that linearizes the
combination of charge pump and current controlled oscillator [10]. The proposed
architecture for feedback block is shown in figure 7.
across the resistor and the current flowing through it.
Figure 5: Proposed Architecture for V2I.
The proposed architecture for V2I block is shown in figure 5. The value of IICO
is
determined by the control voltage Vctrl generated from loop filter. Vctrl is applied
to node A. The current sources B and C sinks and current source A sources equal amount
of current. IICO is proportional to the current flowing through the resistor. The
linear increase of IICO with applied Vctrl is shown in figure 6.
Figure 6: Linear increase of current in ICO.
Mann et al, The Design of A Low Power Low Noise…
Figure
7:
Prophttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9osed
Architecture for V2I
文档下载 免费文档下载
http://www.wendangwang.com/
.
The values of the current sources are set so that when the gain of VCO starts reducing
the gain of charge pump should start increasing, i.e. the total loop gain remains
constant. The point A in figure 8 represents the point where oscillator gain decreases
and the charge pump current increases.
Figure 8: Linear increase of charge pump current.
4.4 Current Controlled Oscillator
The Current starved Oscillator operates similar to that of the ring oscillator. It
has additional control of the output frequency. The design consists of current starved
inverters and Schmitt trigger inside the loop. The proposed architecture for ICO is
shown in figure 9.
The output of the current starved VCO is buffered through inverter
to connect it to
large load.
Figure 9: Linear increase of charge pump current
.
The
Schmitt
trhttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9igger
is
designed with upper and lower voltage levels set to 1.2V and 600mv. The Schmitt trigger
文档下载 免费文档下载
http://www.wendangwang.com/
acts like inverter with hysteresis .It helps in reducing Phase 9. References
Noise.
Figure 10: Linear increase of charge pump current
.
The phase noise for the ICO without Schmitt trigger is shown in figure 10.
Figure 11: Linear increase of charge pump current.
Phase noise for the ICO Schmitt trigger is shown in figure 9. It’s clear from the
figures that Schmitt trigger helps in reducing the phase noise and also removes the
amplitude distortion form the output of the oscillator.
Figure 12 shows the output of PLL in locked state.
Figure 12: Linear increase of charge pump current.
文档下载 免费文档下载
http://www.wendangwang.com/
Mann et al, The Design of A Low Power Low Noise…
[1]
R.
E.
Best,
Phase-Locked
Loops
Design,
Simulhttp://www.wendangwang.com/doc/a25eb73104264e90a50e40e9ation,
and
Applications, 5th Ed. New York: McGraw Hill Company, 2003.
[2]
R. J. Baker, CMOS: Circuit Design, Layout, and Simulation.
Wiley & Sons Inc., 2005 [3]
New Jersey:
John
Mohzgan Mansuri “Low-Power Low-Jitter On-Chip Clock
Generation” PhD Thesis, Electrical Engineering, UCLA, 2003
[4]
Zafer Ozgur Gursoy, “ Design and Realization of a 2.4Gbps-3.2-Gbps clock and
data recovery circuit” MSEE Thesis, Sabanci University, January 2003
[5]
B. Razavi, Design of Integrated Circuit for Optical Communications. New York,
McGraw Hill Company, 2002. [6] B. Razavi, Design of Analog CMOS Integrated Circuit.
New York, McGraw Hill Company, 2002.
[7] B. Razavi, Phase-Locking in High-Performance Systems From Device to Architecture.
New Jersey:
[8]
John Wiley & Sons Inc., 2003.
B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuit Theory and
Design.
New
York:
IEEE
Inc.,
2005.://www.wendangwang.com/doc/a25eb73104264e90a50e40e9ar
[9]
W. J. Dally and J. W. Poulton, Digital Systems Engineering. United Kingdom:
Cambrigde University Press, 1998.
[10]
Kelly Patrick McClellan, Parameshwaran K Gopalier, Rancho Santa Margarita,
文档下载 免费文档下载
http://www.wendangwang.com/
Phase locked loop with linear combination of charge pump and oscillator,
US Patent
#5687201, Nov 11th
1997.
文档下载网是专业的免费文档搜索与下载网站，提供行业资料，考试资料，教
学课件，学术论文，技术资料，研究报告，工作范文，资格考试，word 文档，
专业文献，应用文书，行业论文等文档搜索与文档下载，是您文档写作和查找
参考资料的必备网站。
文档下载 http://www.wendangwang.com/
亿万文档资料，等你来发现