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VENUS INTERNATIONAL COLLAGE OF TECHNOLOGY Phase-Locked Loop Design EE 3rd semester PREPARED BY:HARSH SHRMA (130810109024) PARTH METHANIYA (130810109042) ARJUN GADHAVI (130810109022) PARTH PANDYA (130810109046) 1 INTRODUCTION • PLL is full form of PHASE LOCKED LOOP. • The phase locked loop principle has been used in applications such as FM stereo decoders, motor speed control , tracking filters ,frequency synthesized transmitters and receiver, and generation of local oscillator frequencies in TV and in FM tuners. 2 Block diagram of PLL What is a PLL? • A PLL is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal. • Analogous to a car’s “cruise control” 4 Phase-Frequency Detector(PFD) • Edge-triggered - Input duty-cycle doesn’t matter • Pulse-widths proportional to phase error Vdd D GoFaster Q DFF Ref CK R DLY Vdd R D D Q DFF FB GoSlower CK 5 PFD Logic States • 3 and “1/2” Output states • States: GoFaster GoSlower Effect: 0 0 No Change 0 1 Slow Down 1 0 Speed Up 1 1 Avoid Dead-Zone 6 Example: PFD Ref FbClk GoFaster GoSlower Vctl 7 Low-Pass Filter • Integrates charge-pump current onto C1 cap to set average VCO frequency (“integral” path). • Resistor provides instantaneous phase correction w/o affecting avg. freq. (“proportional” path). • C2 cap smoothes large IR ripple on Vctl • Typical value: 0.5k < Rlpf < 20kOhm Vctl Res C1 C2 8 Voltage-Controlled Oscillator • VCO usually consists of two parts: control voltage- to-control current (V2I) circuit and current-controlled ring oscillator (ICO) • VCO may be single-ended or differential • Differential design allows for even number of oscillator stages if differential-pair amps used for delay cells • V2V may be used instead to generate bias voltages for diff-pair amps 9 How are PLL’s Used? • Frequency Synthesis (e.g. generating a 1 GHz clock from a 100 MHz reference) • Skew Cancellation (e.g. phase-aligning an internal clock to the IO clock) (May use a DLL instead) • Extracting a clock from a random data stream (e.g. serial-link receiver) • Frequency Synthesis is the focus of this tutorial. 10 Charge-Pump PLL Block Diagram Ref GoFast PFD GoSlow Clk Vctl C P VCO LS C2 C1 FbClk DIV Clk 11 Charge Pump • Converts PFD phase error (digital) to charge (analog) • Charge is proportional to PFD pulse widths Qcp = Iup*tfaster – Idn*tslower • Qcp is filtered/integrated in low-pass filter 12 VDD D Q REF CK R GoFaster Charge Pump Icp Sup Reset VDD R D DFF FB Sdn Q GoSlower Icp CK 13 Charge-Pump Wish List • Equal UP/DOWN currents over entire control voltage range - reduce phase error. • Minimal coupling to control voltage during switching - reduce jitter. • Insensitive to power-supply noise and process variations – loop stability. • Easy-to-design, PVT-insensitive reference current. • Programmable currents to maintain loop dynamics (vs. M, fref)? • Typical: 1 A (mismatch)< Icp < 50 A ( Vctl) 14 PLL Problem • Problem: large static offset. • Cause: designer did not account for gate leakage in LPF caps. • Solutions: – switch to thick-gate oxide caps – switch to metal caps 15 PLL Problem • Problem: VCO stuck at max frequency at poweron. • Cause: PLL tried to lock before VDD was stable. Because VCO couldn’t run fast enough to lock at low VDD, Vctl saturated. When VDD finally stabilized, Vctl = VDD, causing a maxed-out VCO to outrun FBDIV. • Solution: maintain PLL RESET high until VDD is stable to keep Vctl at 0V. 16 • THANK YOU