Download AND8309 - Trends in Integrated Circuits that Affect ESD Protection

AND8309/D
Trends in Integrated
Circuits that Affect ESD
Protection Requirements
Integrated Circuit Trends
www.onsemi.com
The stunning progress in integrated circuit capability over
the last 40 years is most succinctly expressed by Moore’s
Law; “Every 2 years the number of transistors that can be
economically manufactured in an integrated circuit will
double”. The secret to this success has been the shrinking of
integrated circuit feature sizes in all three dimensions. To
maintain circuit reliability with the smaller dimensions the
operating voltage of integrated circuits has been steadily
declining. This trend will continue in the future, as
documented in the International Technology Roadmap for
Semiconductors (International Technology Roadmap for
Semiconductors’, http://www.itrs.net, 2000−2006),
Figure 1. As the working voltage for integrated circuits
decreases the voltage at which circuit damage can occur also
decreases.
APPLICATION NOTE
The move to smaller geometries has also prompted
fundamental changes in IC technologies that have had an
adverse effect on the intrinsic ability of the technologies to
survive ESD stress. A prime example is the evolution of
nMOS transistors in CMOS technologies. Some of the
changes that have degraded the nMOS’s ability to survive
ESD are outlined in Table 1.
Table 1. nMOS INNOVATIONS IN CMOS TECHNOLOGY
Change
Reason for Implementation
Impact on ESD
Shallower Junctions
Allows Shorter Channel Length
Transistors
Higher Current Density During an ESD Event
Lightly Doped Drains
Reduce Hot Carrier Transistor
Degradation
Degraded Performance of Parasitic Bipolar Transistor which Provides
Intrinsic High Current Capability
Silicided Junctions
Reduced Transistor Series
Resistance
Removes Ballast Resistance in nMOS Drains, Degrading High Current
Carrying Capability of Parasitic Bipolar Transistor
Thin Gate Oxides
Improved Transistor
Performance
Reduced Voltage at Which Oxide Damage Occurs
Charged Device Model (CDM) and Machine Model (MM),
point out an important development. In the 1980s and into
the 1990s integrated circuits became more robust, even in
a period of rapidly shrinking IC geometries. This reflected
improved understanding of how to design ESD protection
into ICs. In the late 1990s and into the 21st century the
shrinking of IC geometries has outpaced innovative
technology to provide on chip protection leaving IC’s more
vulnerable to damage from ESD.
The overall effect of technology changes on the ESD
robustness of integrated circuits is discussed in the
“Electrostatic Discharge (ESD) Technology Roadmap”
produced by the Electrostatic Discharge Association
(ESDA) (see Electrostatic Discharge (ESD) Technology
Roadmap, ESD Association, 7900 Turin Rd. Bldg. 3, Rome
NY 13440, 2005). This document shows the history and
future trends in robustness of integrated circuits to ESD.
An example for Human Body Model (HBM) robustness is
shown in Figure 2. The HBM trend, and similar trends for
© Semiconductor Components Industries, LLC, 2008
January, 2017 − Rev. 3
1
Publication Order Number:
AND8309/D
AND8309/D
2.0
1.8
1.6
VOLTAGE (V)
1.4
1.2
Vmax Perf.
1.0
0.8
Vlow Power
0.6
0.4
0.2
0
1995
2000
2005
2010
2015
2020
2025
YEAR
Figure 1. Operating Voltage for Advanced ICs from the International Technology Roadmap for Semiconductors.
Values from 1999 to 2006 Were Taken from that Year’s Roadmap.
Values for 2007 through 2020 Were Taken from the 2006 Update
10000
CMOS HBM Max Levels
VOLTAGE (V)
8000
6000
CMOS HBM Min Levels
4000
2000
1980
1985
1990
1995
2000
2005
2010
YEAR
Figure 2. Human Body Model Sensitivity Limits Based on ANSI/ESD STM5.1
Effect of IC Trend on System Level ESD
Protection elements located at sensitive nodes are and
effective solution to divert harmful ESD events away from
IC’s. Protection elements must be matched to the circuits
they are protecting. All IC pins have an intended voltage
range for operation, as illustrated in Figure 3. Beyond the
intended voltage range is a safe guard band. Voltage beyond
the guard band will initiate circuit damage. As more
advanced technologies are used, and the operating voltage
is decreased, the width of the guard band region also
decreases. ESD protection components need to work within
the guard band as shown in Figure 3. A narrower guard band
requires protection elements with lower resistance in their
“on” state resulting in lower ESD clamping voltages to
prevent voltage excursions from getting into the device
damage region. ON Semiconductor recognizes this
requirement and designs their ESD protection solutions to
have industry leading low clamping voltage.
Lower working voltages and reduced device level ESD
robustness has an effect on the requirements for external
ESD protection components. ESD testing of ICs to the
HBM, CDM and MM standards indicate an IC’s ability to
survive circuit board and system assembly in ESD
controlled environments. System level ESD tests, such as
IEC 61000−4−2, are much more severe than the device level
tests. Electronic systems, such as laptops and mobile
phones, must therefore be capable of providing off-chip
ESD protection for ICs within the system.
System level ESD protection is provided in a number of
ways. The system case provides physical protection and
shielding and good board design can direct many ESD
threats to system ground rather than to sensitive circuit
elements. These design elements can not fully prevent ESD
threats from getting coupled into sensitive IC’s, though.
www.onsemi.com
2
AND8309/D
Guard Band Region
Normal
Voltage
Range
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
Current
Device
Damage
Voltage
Crowbar
V Clamping
Figure 3. Operation of ESD Protection Components
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage
may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer
is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of
any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and
do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices
intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and
hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was
negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright
laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
◊
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
3
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AND8309/D