Download 2 CMOS VLSI Design

Introduction to
CMOS VLSI
Design
SRAM/DRAM
Textbook: Chapter 11
Outline
 Memory Arrays
 SRAM Architecture
– SRAM Cell
– Decoders
– Column Circuitry
– Multiple Ports
 DRAM
 Serial Access Memories
CMOS VLSI Design
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Memory Arrays
Memory Arrays
Random Access Memory
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
CMOS VLSI Design
Content Addressable Memory
(CAM)
Serial Access Memory
Read Only Memory
(ROM)
(Nonvolatile)
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Queues
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
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Array Architecture
 2n words of 2m bits each
 If n >> m, fold by 2k into fewer rows of more columns
wordlines
bitline conditioning
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
column
circuitry
k
n
8-word by 4-bit
memory folded into a
4-row by 8-column
array with n=3, m=2,
k=1
column
decoder
2m bits
 Good regularity – easy to design
 Very high density if good cells are used
CMOS VLSI Design
simplest design: one
row per word and
one column per bit
in each word very
tall skinny memory
hard to fit in the chip
floorplan
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12T SRAM Cell
 Basic building block: SRAM Cell
– Holds one bit of information, like a latch
– Must be read and written
 12-transistor (12T) SRAM cell
– Use a simple latch connected to bitline
– 46 x 75 l unit cell
bit
write
write_b
read
read_b
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6T SRAM Cell
 Cell size accounts for most of array size
– Reduce cell size at expense of complexity
 6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
 Read:
bit
– Precharge bit, bit_b
word
– Raise wordline
 Write:
– Drive data onto bit, bit_b
– Raise wordline
CMOS VLSI Design
bit_b
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SRAM Read
bit_b
bit
 Precharge both bitlines highword
 Then turn on wordline
N2
 One of the two bitlines will
– be pulled down by the cell
 Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
 Read stability
– A must not flip
P1 P2
A
N4
A_b
N1 N3
A_b
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
400
500
600
time (ps)
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SRAM Read
bit_b
bit
 Precharge both bitlines high
word
 Then turn on wordline
N2
 One of the two bitlines will
– be pulled down by the cell
 Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
 Read stability
– A must not flip
– N1 >> N2
P1 P2
N4
A
A_b
N1 N3
A_b
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
400
500
600
time (ps)
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bit_b
bit
word
P1 P2
N2
A
N4
A_b
N1 N3
SRAM Read, 0 is stored in the cell
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SRAM Write
bit
 Drive one bitline high,
word
– the other low
P1
N2
 Then turn on wordline
A
 Bitlines overpower cell
N1
– with new value
 Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 A_b
– Force A_b low,
bit_b
• then A rises high
 Writability
word
– Must overpower
• feedback inverter
1.5
bit_b
P2
N4
A_b
N3
A
1.0
0.5
0.0
0
100
200
300
400
500
600
700
time (ps)
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SRAM Write
bit_b
bit
 Drive one bitline high,
word
– the other low
N2
 Then turn on wordline
 Bitlines overpower cell
– with new value
 Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
1.5
 Writability
– Must overpower feedback inverter 1.0
– P2 << N4 to force A_b low,
0.5
– N1 turns off, P1 turns on,
0.0
– raise A high as desired
0
P1 P2
N4
A
A_b
N1 N3
A_b
A
bit_b
word
100
200
300
400
500
600
time (ps)
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700
SRAM Sizing
 High bitlines must not overpower inverters during
reads
 But low bitlines must write new value into cell
bit_b
bit
word
weak
med
med
A
A_b
strong
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SRAM Column Example
read
write
Bitline Conditioning
2
More
Cells
word_q1
bit_b_v1f
bit_v1f
SRAM Cell
write_q1
data_s1
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Decoders
 n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory
– Build AND from NAND or NOR gate
choose minimum size to reduce
load on the address lines
A1
A0
A1
1
1
8
A1
1
4
A0
1
A0
1/2
4
16
A1
1
1
2
8
word0
word0
word1
word1
word2
word3
CMOS VLSI Design
word
A0
static
word
Pseudo-nMOS
word2
word3
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Decoder Layout
 Decoders must be pitch-matched to SRAM cell
– Requires very skinny gates
A3
A3
A2
A2
A1
A1
A0
A0
VDD
word
GND
NAND gate
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buffer inverter
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Decoder Layout
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Large Decoders
 For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
A3
A2
A1
A0
word0
word1
word2
word3
word15
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Predecoding
 Many of these gates are redundant
– Factor out common
gates into predecoder
– Saves area
– Same path effort
A3
A2
A1
A0
predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
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Column Circuitry
 Some circuitry is required for each column
– Bitline conditioning
– Sense amplifiers
– Column multiplexing
 Each column must have write drivers and read
sensing circuits
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Bitline Conditioning
 Precharge bitlines high before reads

bit
bit_b
 Equalize bitlines to minimize voltage difference
when using sense amplifiers

bit
CMOS VLSI Design
bit_b
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Sense Amplifiers
 Bitlines have many cells attached
– Ex: 32-kbit SRAM has 256 rows x 128 cols
– 128 cells on each bitline
 tpd  (C/I) DV
– Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)
– Discharged slowly through small transistors
(small I)
 Sense amplifiers are triggered on small voltage
swing (reduce DV)
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Differential Pair Amp
 Differential pair requires no clock
 But always dissipates static power
sense_b
bit
P1
N1
P2
N2
sense
bit_b
N3
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Clocked Sense Amp
 Clocked sense amp saves power
 Requires sense_clk after enough bitline swing
 Isolation transistors cut off large bitline capacitance
bit
bit_b
isolation
transistors
sense_clk
regenerative
feedback
sense
CMOS VLSI Design
sense_b
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Twisted Bitlines
 Sense amplifiers also amplify noise
– Coupling noise is severe in modern processes
– Try to couple equally onto bit and bit_b
– Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
equalize voltage to
reduce noise.
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Column Multiplexing
 Recall that array may be folded for good aspect ratio
 Ex: 2k word x 16 folded into 256 rows x 128 columns
– Must select 16 output bits from the 128 columns
– Requires 16 8:1 column multiplexers
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Tree Decoder Mux
 Column mux can use pass transistors
– Use nMOS only, precharge outputs
 One design is to use k series transistors for 2k:1 mux
– No external decoder logic needed
B0 B1
B2 B3
B4 B5
B6 B7
B0 B1
B2 B3
B4 B5
B6 B7
bitlines
propagate
through 3
transistors
A0
A0
A1
A1
A2
A2
Y
CMOS VLSI Design
to sense amps and write circuits
Y
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Single Pass-Gate Mux
 Or eliminate series transistors with separate decoder
A1
A0
B0 B1
B2 B3
bitlines propagate
through 1 transistor
Y
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Ex: 2-way Muxed SRAM
2
More
Cells
More
Cells
word_q1
2-to-1 mux
A0
A0
write0_q1
2
write1_q1
data_v1
CMOS VLSI Design
two bits from
two cells and
selected by A0
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Multiple Ports
 We have considered single-ported SRAM
– One read or one write on each cycle
 Multiported SRAM are needed for register files
 Examples:
– Multicycle MIPS must read two sources or write a
result on some cycles
– Pipelined MIPS must read two sources and write
a third result each cycle
– Superscalar MIPS must read and write many
sources and results each cycle
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Dual-Ported SRAM
 Simple dual-ported SRAM
– Two independent single-ended reads
bit
– Or one differential write
bit_b
wordA
wordB
wordA reads bit_b (complementary)
wordB reads bit (true)
 Do two reads and one write by time multiplexing
– Read during ph1, write during ph2
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Multi-Ported SRAM
 Adding more access transistors hurts read stability
 Multiported SRAM isolates reads from state node
 Single-ended design minimizes number of bitlines
bA bB bC
bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
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bA bB bC
bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
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Logical effort of RAMs
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DRAM: Dynamic RAM
 Store their contents as charge on a capacitor rather
than in a feedback loop.
 1T dynamic RAM cell has a transistor and a
capacitor
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DRAM Read
1. bitline precharged to VDD/2
2. wordline rises, cap. shares it
charge with bitline, causing a
voltage DV
3. read disturbs the cell content
at x, so the cell must be
rewritten after each read
Ccell
VDD
DV 
2 Ccell  Cbit
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DRAM write
On a write, the bitline is driven
high or low and the voltage is
forced to the capacitor
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DRAM Array
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DRAM
 With large size, the bitline cap is an order of
magnitude higher than in the cell, causing very small
voltage swing.
 A sense amplifier is used.
 Three different bitline architectures, open, folded,
and twisted, offer different compromises between
noises and area.
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Serial Access Memories
 Serial access memories do not use an address
– Shift Registers
– Tapped Delay Lines
– Serial In Parallel Out (SIPO)
– Parallel In Serial Out (PISO)
– Queues (FIFO, LIFO)
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Shift Register
 Shift registers store and delay data
 Simple design: cascade of registers
– Watch your hold times!
clk
Din
Dout
8
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Denser Shift Registers
 Flip-flops aren’t very area-efficient
 For large shift registers, keep data in SRAM instead
 Move read/write pointers to RAM rather than data
– Initialize read address to first entry, write to last
– Increment address on each cycle
Din
clk
11...11
reset
CMOS VLSI Design
counter
counter
00...00
readaddr
writeaddr
dual-ported
SRAM
Dout
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Tapped Delay Line
 A tapped delay line is a shift register with a
programmable number of stages
 Set number of stages with delay controls to mux
– Ex: 0 – 63 stages of delay
clk
delay2
SR1
delay3
SR2
CMOS VLSI Design
delay4
SR4
delay5
SR8
SR16
SR32
Din
delay1
Dout
delay0
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Serial In Parallel Out
 1-bit shift register reads in serial data
– After N steps, presents N-bit parallel output
clk
Sin
P0
CMOS VLSI Design
P1
P2
P3
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Parallel In Serial Out
 Load all N bits in parallel when shift = 0
– Then shift one bit out per cycle
P0
P1
P2
P3
shift/load
clk
Sout
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Queues
 Queues allow data to be read and written at different
rates.
 Read and write each use their own clock, data
 Queue indicates whether it is full or empty
 Build with SRAM and read/write counters (pointers)
WriteClk
WriteData
FULL
CMOS VLSI Design
ReadClk
Queue
ReadData
EMPTY
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FIFO, LIFO Queues
 First In First Out (FIFO) organized as a circular
buffer
– Initialize read and write pointers to first element
– Queue is EMPTY
– On write, increment write pointer
– If write almost catches read, Queue is FULL
– On read, increment read pointer
 Last In First Out (LIFO)
– Also called a stack
– Use a single stack pointer for read and write
CMOS VLSI Design
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