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CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
JULY15
ASSESSMENT_CODE BCA2050_JULY15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10919
QUESTION_TEXT
List and explain the characteristics of Memory Systems?
SCHEME OF
EVALUATION
1Location:
Location of the memory:
*CPU: own local memory in the form of registers.
*Internal (main): it is often equated with the main memory.
*External (secondary): peripheral storage devices.
2 marks)
2Capacity:
*Word size:natural unit of organization of memory.
*Number of words: addressable unit, interms of bytes.
*Unit of transfer: a)word
b)Block(02 marks)
3Access Method:
*Sequential: data are generally stored in units called “records”.
*Direct: individual blocks or records have a unique address based on
physical location.
*Random: each addressable location in memory has a unique,physically
wired-in addressing mechanisms.
*Associative: cache uses this method.(02 marks)
4Performance:
*Access time: time to perform read or write operation.
*Cycle time: access time+ additional time required before second
access can commence.
*Transfer rate: rate at which data can be transferred into or out of a
memory unit.(02 marks)
5Physical Type:
*Semiconductor: main memory,cache,RAM,ROM.
*Magnetic: magnetic disks,tape units.
*Optical: CD-ROM,CD-RW.
*Magneto-optical:optical laser used.(01 marks)
6Physical characteristics:
*Volatile/non-volatile.sable
*Erasable/non-erasable
*Memory Hierarchy(01 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10920
QUESTION_TEXT
Explain the features of microprogramming & discuss the various
applications of microprogramming.
SCHEME OF
EVALUATION
Features (page 295)
Each point 1 mark(1*5)=5 marks
Applications (page297)
Microprogramming …..predecessors [1 mark]
This technique…..microprocessors[1 mark]
Microprogramming is used …..etc[1 mark]
In order……chip-[2 marks]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72894
QUESTION_TEXT
Explain any five 8086 addressing modes
Implied mode
Immediate mode
Direct addressing mode
Indirect addressing mode
SCHEME OF EVALUATION Register addressing mode
Register indirect mode
Relative addressing mode
Indexed addressing mode
(Each mode carries 2 marks, any 5 Total – 10)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125688
QUESTION_TEXT
Explain the 8086 address set and its different modes.
8086 register set includes:
SCHEME OF
EVALUATION
•
General purpose registers
•
Segment Registers
•
Pointers and index registers
•
Flag Registers
1.
General Purpose Registers: are those registers which may seem
like operands of the logical, arithmetic and associated instructions. There
are 16 general purpose registers which can be split into two 8-bit
registers. The general purpose registers have been named as AX, BX, CS
and DX. Theses registers can be either lower order or higher order. (2
marks)
2.
Segment Register: The 8086 processor utilises the segment
registers to retrieve blocks of memory known as segments. Since there
are four memory segments in an 8086 model i.e. code, data, stack and
extra segments therefore there are 4 segment registers to hold the upper
16 bit addresses of the four memory segments. (1 mark)
3.
Pointers and index registers: are useful in addressing functions.
Since the segment registers are 16 bits but address bus requires 20 bits,
hence pointer registers IP, BP and SP are used to hold the offset within
the code, data and stack segments respectively. The index registers SI
and DI are used for offset storage in certain types of addressing modes.
They can be used as general purpose registers as well. (1 mark)
4.
The flags register: is a 32 bit register called EFLAGS. The flags
operate particular operations and depict the status of the 80386. (1
mark)
5.
The last class of 8086 registers is special/ miscellaneous registers
such as control registers, debug registers, test registers, descriptor
registers, a task register and model specific registers. (1 mark)
Two modes are:
•
Maximum mode
•
Minimum mode
1.
Maximum mode: is planned for multiprocessor systems where an
extra bus controller is needed to produce the control signals. The
processors monitor the bus-controller utilising status codes. Maximum
mode operation is new and specially designed for the operation of the
8086 arithmetic coprocessor. It is selected by grounding MN/MX. It is
different from minimum as few of the control signals should be
externally produced. (2 marks)
2.
Minimum mode: Is utilised for single processor system. Where
8086/8088 directly produces all the essential control signals. It is
acquired by linking the mode selection pin MN/MX to +5.0V. In such a
mode, all the control signals are distributed by the microprocessor chip
itself. The rest of the components in the system are clock generator,
latches, transrecievers, memory and I/O devices. (2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125689
QUESTION_TEXT
Explain salient features of SCSI Bus
1.
SCSI addresses: SCSI utilizes a 3-bit addressing scheme, in which
every device is designated an address varying from 0 to 7. Device 7 has
the topmost priority, thus the host computer is normally designated to be
device 7.
2.
Initiator/Target: Communication happens as soon as the initiator
(client), who is particularly the host computer, initiates a request, and the
target (server) works on the request. The SCSI allows all devices to
communicate with one another; however few devices are executed in
such a manner that they are not able to start communications.
SCHEME OF
EVALUATION
3
Protocols: SCSI devices can utilize either synchronous or
asynchronous communication protocols. In the initial SCSI arrangement,
synchronous communication permitted speeds till 5Mb/sec.
4.
SCSI Variants: SCSI comes in four variants, SCSI-1, SCSI-2,
SCSI-3 and LVD SCSI.
5.
SCSI Bus termination: Reflected signals intrude with the “real”
data on the bus and cause data corruption and signal loss. Several
techniques are used for SCSI bus termination. These are forced perfect
termination (FPT), Low Voltage Differential (LVD) terminations,
passive termination, High Voltage Differential (HVD), and active
termination.
(2 marks each)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125690
QUESTION_TEXT
Explain instruction execution procedure.
SCHEME OF
EVALUATION
1.
Contents of PC are loaded into MAR and read request is sent to the
main memory. While waiting for the MFC signal PC is incremented by
setting one of the current values in the PC. Mean while carry–in to ALU
is set to 1 and an add operation is specified.
2.
The updated value from the register Z is sent back to PC. This step
can be started immediately after issuing the read request without having
to wait for the MFC signal.
3.
Wait for the MFC signal. Here word fetched from the memory is
loaded into the IR. This completes fetch phase of the operation.
4.
The instruction decoding circuit interprets the contents of IR at the
beginning which enables the control circuitry to choose the appropriate
signals for the remainder of the control sequence. Here address field of
IR, which contains the address NUM, is gated to the MAR and memory
read operation is initiated.
5.
Transfer the content of R0 to register Y and wait for the MFC
signal.
6.
Now the memory operand is available on register MDR. The
addition operation is performed.
7.
The result is transferred to R0. This completes the execution phase
of the operation. The end signal indicates that this is the last step of
current instruction and causes a new fetch cycle to be started going back
to step1.
(Total 10 marks)