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CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
APR2016
ASSESSMENT_CODE BCA2050_APR2016
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10924
QUESTION_TEXT
What is conduction? Explain the various technique for reducing
contention.
SCHEME OF
EVALUATION
Contention
In a shared memory …..arbiter-[1 mark]
Techniques for reducing contention:
a) Memory Allocation:[2 mark]
b) Cache memory: [1 mark]
c) cache memory: [1 mark]
d) local & Global memories: [3 mark]
e) Better interconnection/w[ 2 mark]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72892
QUESTION_TEXT
Write a note on instructions format.
SCHEME OF
EVALUATION
Instruction Formats
Instruction Format is defined as the layout of bits in an instruction in
terms of its constituent parts. An Instruction Format must include
opcode implicitly or explicitly and one or more operand(s). For, most
instruction sets have usually more than one instruction format.
Instruction Length
Most important design issue is the length of an instruction. It is affected
by and affects Memory size, Memory organization, Bus structure, CPU
complexity, CPU speed. There is a trade off between powerful
instruction repertoire and saving space.
Number of addressing modes: Some times addressing mode is implicit
in the instruction or may be certain opcodes call for indexing.
Number of operands: Typically today’s machines provide two
operands. Each operand may require its own mode indicator or the use
of indicator is limited to one of the address fields.
Register versus memory: A machine must have registers so that the
data can be brought into the CPU for processing.
Number of register sets: Almost all machines have a set of general
purpose registers, with typically 8 or 16 registers in it.
Address range: For addresses that refer to the memory locations, the
range of addresses is related to the number of address bits.
Address granularity: It is concerned with addresses that refer to the
memory other than registers.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72894
QUESTION_TEXT
Explain any five 8086 addressing modes
Implied mode
Immediate mode
Direct addressing mode
Indirect addressing mode
SCHEME OF EVALUATION Register addressing mode
Register indirect mode
Relative addressing mode
Indexed addressing mode
(Each mode carries 2 marks, any 5 Total – 10)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125686
QUESTION_TEXT
What is instruction cycle? Explain the various registers utilised in the
CPU cycle and the steps involved in the instruction cycle.
An instruction cycle means the time duration in which a single
instruction is obtained from memory and implemented as soon as a
computer is provided with an instruction in machine language. It is also
called fetch-and-execute cycle. (1 mark)
The various registers utilised in the CPU cycle are:
SCHEME OF
EVALUATION
•
Program counter: This is a special purpose register which is
utilised by the processor to contain the address of the subsequent
instruction to be implemented. As each instruction is implemented, the
PC is automatically incremented. (1 mark)
•
Memory Address Register: The MAR saves the physical memory
address on which the subsequent instruction is placed or the subsequent
piece of data will be written. IT contains the address of a memory block
to be written to or read from. (1 mark)
•
Memory Data Register: MDR is a two way register which
contains data accessed from memory or data awaiting storage in
memory. Hence MDR can stack its data from:
One of the CPU registers
The data bus (1 mark)
•
Instruction Register: IT stores the instruction presently being
executed. (0.5 mark)
•
Control Unit: After choosing machine resources like a specific
arithmetic operation and a data source register, The CU is utilised to
decode the program instruction in the IR. It synchronises the initiation of
those resources. (1 mark)
•
Arithmetic Logic Unit: Works on the logical operations (0.5
mark)
Steps involved in Instruction Cycle are:
•
Fetch the instruction: Fetching the instruction is in the first phase
of an instruction cycle. The subsequent instruction is extracted from the
memory address which is at present stored in the Program Counter as
well as in the Instruction Register. (1 mark)
•
Decode the Instruction: The decoder interprets the instruction
when the instruction has been obtained. In this phase, the instruction
present in the instruction register gets decoded. (1 mark)
•
Read Effective address: When the instruction contains an indirect
address, the actual address is read from the main memory and any
needed data is obtained from main memory and there after positioned in
data registers. (1 mark)
•
Execute the instruction: The control unit of CPU forwards the
decoded information in the form of a sequence of control signals to the
applicable functional units of the CPU to perform the actions needed by
the instruction like reading values from registers, forwarding them to the
ALU to conduct logical or mathematical functions on them as well as
writing the outcome back to a register. (1 mark)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125689
QUESTION_TEXT
Explain salient features of SCSI Bus
1.
SCSI addresses: SCSI utilizes a 3-bit addressing scheme, in which
every device is designated an address varying from 0 to 7. Device 7 has
the topmost priority, thus the host computer is normally designated to be
device 7.
2.
Initiator/Target: Communication happens as soon as the initiator
(client), who is particularly the host computer, initiates a request, and the
target (server) works on the request. The SCSI allows all devices to
communicate with one another; however few devices are executed in
such a manner that they are not able to start communications.
SCHEME OF
EVALUATION
3
Protocols: SCSI devices can utilize either synchronous or
asynchronous communication protocols. In the initial SCSI arrangement,
synchronous communication permitted speeds till 5Mb/sec.
4.
SCSI Variants: SCSI comes in four variants, SCSI-1, SCSI-2,
SCSI-3 and LVD SCSI.
5.
SCSI Bus termination: Reflected signals intrude with the “real”
data on the bus and cause data corruption and signal loss. Several
techniques are used for SCSI bus termination. These are forced perfect
termination (FPT), Low Voltage Differential (LVD) terminations,
passive termination, High Voltage Differential (HVD), and active
termination.
(2 marks each)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125690
QUESTION_TEXT
Explain instruction execution procedure.
1.
Contents of PC are loaded into MAR and read request is sent to the
main memory. While waiting for the MFC signal PC is incremented by
setting one of the current values in the PC. Mean while carry–in to ALU
is set to 1 and an add operation is specified.
SCHEME OF
EVALUATION
2.
The updated value from the register Z is sent back to PC. This step
can be started immediately after issuing the read request without having
to wait for the MFC signal.
3.
Wait for the MFC signal. Here word fetched from the memory is
loaded into the IR. This completes fetch phase of the operation.
4.
The instruction decoding circuit interprets the contents of IR at the
beginning which enables the control circuitry to choose the appropriate
signals for the remainder of the control sequence. Here address field of
IR, which contains the address NUM, is gated to the MAR and memory
read operation is initiated.
5.
Transfer the content of R0 to register Y and wait for the MFC
signal.
6.
Now the memory operand is available on register MDR. The
addition operation is performed.
7.
The result is transferred to R0. This completes the execution phase
of the operation. The end signal indicates that this is the last step of
current instruction and causes a new fetch cycle to be started going back
to step1.
(Total 10 marks)