Download Microprocessors and rPeANUt

Microprocessors and rPeANUt
Eric McCreath
Microprocessors
There are many well known microprocessors:
Intel x86 series, Pentium, Celeron, Xeon, etc.
AMD Opteron,
Intel Itanium,
Motorola 680xx series, PowerPC,
SPARC/ UltraSPARC,
MIPS,
Compaq Alpha,
AVR, PIC,
ARM, Atom, Tegra, IBM Cell....
We shall investigate the design and operation of the ANU
illustrative microprocessor, the rPeANUt.
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Memory
The rPeANUt is a 32 bit microprocessor with:
32 bit registers, and
16 bit addresses,
memory that is addressable in words of 32 bits.
So the total maximum amount of addressable memory is
words or 262144 bytes (256KiB). Only the
addresses 0x0000 to 0x7FFF are connected to actual memory.
Addresses between 0x8000 and 0xFFFFare used for memory
mapped IO (although only 3 of these addresses are actually
used).
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Memory
When the microprocessor is reset the instruction pointer (IP)
is set to 0x0100, so normally a program will be load at this
point for execution.
Addresses 0x0000 to 0x00FF are reserved for the interrupt
vector and other OS code. Also the last 960 words of actual
memory is used for the frame buffer.
0x0000-0x00FF
Interrupts and OS
0x0100-0x7B3F
General Memory
0x7C40-0x7FFF
Frame Buffer
0x8000-0xFFFF
Not connect to
real memory.
Used for memory
mapped IO.
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Memory Access
Memory contains both data and programs.
Memory is accessed via: the MAR (Memory Address Register),
the MDR (Memory Data Register), and bus control signals.
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Memory Access
To read from main memory:
The CPU places the address it wishes to read from into the
MAR.
The MAR is placed on the address bus and a read signal is
given to the bus.
Memory reads this address and writes to the data bus.
The contents of the data bus is copied into the MDR.
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Memory Access
To write to main memory:
The CPU places the address it wishes to write to into the
MAR, also the data the CPU is writing is placed into the MDR.
The MAR and MDR is placed on the bus and a write signal is
given to the bus.
Memory writes the data to the address.
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CPU (Central Processing Unit)
The CPU contains:
A control unit,
The following 32 bit registers:
8 generally purpose registers these may be used for storing
either data or addresses. These are denoted R0, R1, ... R7.
3 constant registers. These are denoted ONE, ZERO, MONE.
An instruction register (IR) - which holds the current
instruction that is being executed.
A status register (SR) - contains status information about the
CPU. Bit 0 is used for integer overflow (OF), bit 1 is used for
interrupt mask (IM), bit 2 to enable the timer interrupt (TI).
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CPU (Central Processing Unit)
The following 16 bit registers:
A stack pointer (SP) - this points to the top of the stack and is
used for method calls, method returns, and interrupts.
A program counter (PC) - which contains the address of the
next instruction to execute.
An ALU (Arithmetic Logic Unit) which does 2-complement
integer arithmetic and bitwise logic computations.
The MAR, MDR, and a number in internal buses for moving
information around the CPU. Note that the registers: MAR,
MDR, IR and PC are not directly accessible via the instruction
set. Although clearly the execution of instructions will effect
these registers.
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Fetch-decode-execute cycle
The control unit sequences the movement of data around the
CPU.
The microprocessor goes through the follow execution cycle:
do {
IR = mem[PC];
PC = PC + 1;
execute_instruction in IR;
check for interrupts;
} while(!halt);
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Instruction Set
Instructions are all 1 word long (32 bits).
Registers have the labels R0,R1,...R7, SP, SR, ONE, ZERO,
MONE and take a nibble (4 bits) in the machine code. The
encoding of this nibble is: R0 is 0x0, R1 is 0x1, ... , R7 is 0x7, SP
is 0x8, SR is 0x9, ONE is 0xB, ZERO is 0xC, and MONE is 0xD.
Addresses and values take 16 bits of the 32 bit machine code
instruction.
Values are sign extended from 16 bits to 32 bits.
The format of the instructions is given in the specification
document.
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Assembling Code By Hand
Assembly code provides a human readable way of describing
the machine code of that is executed on a CPU.
The mapping from assembler to machine code is a simple and
direct process. This is normally done by the assembler.
However, it is useful to be able to do this by hand. It basically
involves looking up the table of instructions and putting
together the bytes of the instruction based on the format of that
instruction.
Say we have the assembly instruction:
add R5 R2 R3
Looking up the addition instruction in the table we have:
add <RS1> <RS2> <RD> => 0x1<RS1><RS2><RD>0000
+ Hence "add R5 R2 R3" would assemble to:
0x15230000
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Load and Store Instruction
The "load" instruction let you load data into a register.
data could be a literal within the text or may be another
location within memory.
The
Whereas the "store" lets you transfer data from a register to a
memory location.
store
CPU
Main memory
load
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Load Addressing Modes
All load operations load from main memory into a designated
register. There are 4 possible addressing modes:
Immediate load - this takes a value from the operand in the
instruction, sign extends it, and stores it into a register.
Absolute load - this takes the address in the operand and
loads the word at this address in main memory into a register.
Indirect load - this takes the address in a given register and
loads the word at this register's address in main memory into a
register.
base+displacement load - this adds a value from the operand
to a register to give an address, which is used as the address to
load from.
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Store Addressing Modes
All store operations store from a designated register into main
memory. There are 3 possible addressing modes:
Absolute store - this takes the address in the operand and
stores the register value at this address in main memory.
Indirect store - this takes the address in a given register and
stores the source value (also in a register) at the given
register's address in main memory.
base+displacement store - this adds a value from the operand
to a register to give the address. This address is used to store
the sources register value.
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Hello World Example
Address 0xFFF0 is the dataIO address for the simple terminal
device. When words are written to this address, there is no
memory to store this information, rather the word is directed to
a simple terminal device. In the simulator this appears with a
text area.
To implement hello world in rPeANUt one can simply load the
character literals into a register and store them to the dataIO
address.
0x0100 : load #'H' R1
store R1 0xFFF0
load #'e' R1
store R1 0xFFF0
load #'l' R1
store R1 0xFFF0
load #'l' R1
store R1 0xFFF0
load #'o' R1
store R1 0xFFF0
halt
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Exercises
Read over the spec for rPeANUt.
Convert the following instructions to machine code.
load #10 R2
halt
add R3 R4 R5
move R4 R5
Write a program that prints your name.
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