Proceedings of the 7th IEEE International Conference on Nanotechnology August 2 - 5, 2007, Hong Kong Spin-MTJ based Non-Volatile Flip-Flop Weisheng Zhao, Student Member, IEEE, Eric Belhaire, Member, IEEE and Claude Chappert the MTJ with currents compatible with standard logic gate close the minimum size in advanced CMOS technologies. Abstract— Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using STMicroelectronics 90nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface. Fig.1 Magnetic Tunnel Junction is composed of three principle layers: an oxidation barrier, such as MgO and AlxOy; a Pinned layer and a storage layer, which are ferromagnetic Materiaux (e.g.CoFe). The spin direction in pinned layer is fixed, but can be changed in the storage layer, there are so that two states of MTJ: parallel and antiparallel when the spin direction in pinned layer and free layer are in the same direction or the opposite direction. Index Terms—Magnetic, MRAM, Non-volatile, High speed, Low power, SOC, FPGA, Flip-Flop, Spin-MTJ, SMNFF I. INTRODUCTION SRAM based Flip-Flop is widely used as internal memory to store and synchronize the data processed in the Field Programmable Gate Array (FPGA) and System On Circuit (SOC) circuits, but as the SRAM is volatile, all the data stored in these Flip-Flops is lost when the power goes down, FlipFlop based on non-volatile memory is thus required to protect these data from system crashes and power failures to improve the data security and performance of FPGA and SOC circuits. Contrary to memory plane cells, Flip-Flops work at very high frequency  and the Flash and Phase Change Memory (PCRAM) technologies can thus hardly be used here, while Magnetic memory (MRAM) seems the best candidate thanks to its high writing/reading speed and infinite endurance. MRAM is based on Magnetic Tunnel Junction (MTJ) technology, as represented in Fig.1 . A MTJ device has two permanent states with different resistance values which can easily be read by a CMOS Sensing Amplifier circuit (S.A). Recent rapid progresses in the MTJ writing techniques, especially the Spin Transfer Torque (STT) technology (SpinMTJ) , and the use of MgO barrier  now allows to write This work was supported in part by the European Community under the sixth Framework, Contract Number 510993: MAGLOG. The views expressed are solely those of the authors, and the other Contractors and/or the European Community cannot be hold liable for any use that may be made of the information contained herein. 1 IEF, Univ Paris-Sud, UMR 8622, Orsay, F-91405 2 CNRS, Orsay, F-91405 *Contacting Author: Weisheng Zhao is with Univ Paris-Sud, Bat220, Orsay, France, 91405 (Email:email@example.com, Phone: +33-0169155251, Fax: +33-0169154000) 1-4244-0608-0/07/$20.00 © 2007 IEEE. In this paper, we introduce Spin-MTJ based Non-Volatile Flip-Flop (SMNFF). In the second section, the Spin-MTJ device property, the working mode of Spin Transfer Torque writing approach and its integration with CMOS technology are presented. SMNFF circuit design and the evaluation of its characteristics in the aspect of stability, speed and surface are presented in the third section. The fourth section presents some electrical simulation results of SMNFF based on 90nm CMOS technology and a complete MTJ simulation model . This model is based on Spin Transfer Torque writing approach and MgO barrier. II. SPIN-MTJ AND HYBRID MTL/CMOS DESIGN Spin Transfer Torque (STT) writing phenomena  has been observed in MTJ whose length or width is inferior to 100nm. A current, passing through the MTJ, superior to the density threshold Ic, can switch the MTJ from one state to the other, while a current superior to Ic but in the opposite direction can switch it back (see Fig.2). Because Spin-MTJ cell surface is very small (e.g. 75nm×113nm), the threshold current can be as low as 221uA . STT writing approach resolves some major disadvantages of conventional Field Induced Magnetic Switching (FIMS) writing mode, such as high power dissipation, easy selection disturbance and large transistors in of the CMOS writing circuit etc. 399 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:49 from IEEE Xplore. Restrictions apply. III. SPIN-MTJ BASED NON-VOLATILE FLIP-FLOP (SMNFF) When used in Flip-Flop circuit, the MTJs are spread on the entire chip surface. So, SRAM based sense amplifier, represented in Fig.4, is used to sense the state of MTJs. This sensing structure is much simpler and less precise than a standard MRAM sense amplifier and so two complementary MTJs are used per bit for more robustness. The cell sense the magnetic information by briefly turning on the NMOS transistor MN2 switch and then promptly turning it off (“SEN” is the reading control signal). This structure has been demonstrated to read the states of MTJs in very high speed about 200 ps , which allows the FPGA circuits to realize a real “instant-on”. The use of MgO barrier in MTJs makes this sense amplifier robust to CMOS process variation and mismatch. As represented in Fig.5, Monte-Carlo statistic simulations with pessimistic mismatch parameters has shown an error percentage inferior to 0.1% if the TMR of Spin-MTJ is about 230% and all the transistors in the sense amplifier are in the minimum dimension. Fig.2 The Spin-MTJ state changes from Parallel (P) to Anti-parallel (AP) if the positive direction current density I>Ic, on the contrast, its state will return if the negative direction current density I > Ic. As mentioned in the first section, Spin-MTJ shows different resistance between its two states (low resistance in parallel P state and high resistance in anti-parallel AP state). The ratio between these two resistance values, named Tunnel MagnetoResistance (TMR)  is an important factor for design of the reading circuit. TMR as high as 230% has been obtained at the room temperature with MgO barriers  while it was limited to around 70% with AlxOy barriers . The high TMR enables the sensing of the different states in lower disturbance of process variation and mismatch. Combining the STT effect and MgO barrier, the Spin-MTJ has the excellent writing and reading performance and makes hybrid MTJ/CMOS logic circuit design much more compact. In the writing circuit, a bi-direction current source with the signal “EN” is required to generate the currents to switch the states of MTJs; in the reading circuit, a sense amplifier is used to identify the state registered in the MTJs and export the logic information '1' or '0'. Fig.4 SRAM based sense amplifier used in the SMNFF Error percentage of Mismatch % 250 Fig.3 Spin-MTJ memory cells are implemented above the CMOS circuits 200 150 100 50 0 Another advantage of this hybrid Spin-MTJ/CMOS design is that the storage element MTJ does not take much die area, because it is processed over the chip surface (see Fig.3). Unlike the conventional FIMS-MTJ, which requires very high current (>20mA)  and thus impose the use of thick metal layers to avoid the electromigration effect, a thin metal layer can be used to connect the electrode of Spin-MTJ. This makes that the Spin-MTJ/CMOS technology is less costly. 0 50 1 00 1 50 20 0 25 0 TM R % Fig.5 The error percentage of mismatch decreases down to 0.1% if MgO is used as barrier in MTJs, which can produce the TMR up to 230% maximum at room temperature. The Spin Transfer Torque (STT) writing approach needs a bi-directional current to write the information in the MTJs, so 400 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:49 from IEEE Xplore. Restrictions apply. that a bi-directional current generator is used in this SMNFF, as represented in Fig. 6. Four transistors NMOS MN3-6 generate the current and every time two of them are active, for example, MN3, MN6 are active and MN4, MN5 are inactive, the current passing through the two MTJs will be from the right to the left, contrarily the current will pass from the left to the right; two logic gates NOR control how to activate the four transistors. The signal “EN” is required to enable this current source and reduce the power dissipation as the circuit is in static mode. “Input” determines the current direction and writes the couple of MTJs. The low writing current required in STT writing approach allows to use small size transistors in this current source. The SRAM based sense amplifier use the minimum transistors in width, here 0.12um; because of the low threshold current also the current source occupy also a small surface and the total surface of the SMNFF cell is as small as 5.65um×10.15um. Its layout is shown in Fig.8. Metal 1-3 layers are used to connect the transistors and Metal 4 layers are connected with the electrode of MTJs. Contrary to the FIMS writing approach, here a low inter disturbance is found between two MTJs and their distance can be small barely affecting the final layout. Fig.8 Full layout (5.65um×10.15um) of Spin-MTJ based Flip-Flop, MTJs are placed above the two points ML and MR, see also Fig.2 IV. THE SIMULATION OF SMNFF Fig.6 Bi-directional current source used in the SMNFF By using STMicroelectronics 90nm CMOS low power technology and a behavior Spin-MTJ simulation model , under the Cadence Spectre 5.0.32 simulator environment and 1.2v power supply, the simulations of SMNFF have been done [see Fig.9 and Fig.10]. The width of four NMOS transistors MN3-6 in the writing circuit is 1um and all the others transistors are with the minimum dimension: 0.12um. The TMR of MTJ0-1 is 170%, the height of barrier between two ferromagnetic layers is 1.2nm and the surface is 75nm*113nm in the Spin-MTJ model. The simulation results demonstrate that this Flip-Flop stores and synchronizes well the input data as classical Master-Slave Flip-Flop, moreover, the propagation delay of SMNFF is as low as about 300ps, which includes the input set-up time, sense amplifier reading time, logic delay and the Spin-MTJ writing time. This last time is very rapid and writing times around 100ps has been observed with a significant switching current , therefore SMNFF can work in high speed up to 3.3GHz maximum. The non-volatility of SMNFF enables to decrease largely the start-up latency of FPGA and SOC circuits from some micro seconds down to some hundred pico seconds . By allowing frequent power down of the circuits, it would allow to reduce significantly the standby power dissipation which takes more and more proportion in the total power dissipation as the minimizing development of CMOS technology . Fig.7 Full schematic of Spin-MTJ based Non-Volatile Flip-Flop Combining the SRAM based sense amplifier with the bidirectional current source, the full schematic of the SMNFF is represented in Fig.7.An additional NMOS transistor MN7 is introduced to switch between the writing and reading mode and a slave classical SRAM based register is connected at the output of sense amplifier. The writing and reading process of SMNFF is controlled by the signal “Clk”, when it is active as ‘1’, the input data is stored in the couple of MTJs (e.g. MTJ1: P state and MTJ0: AP state), meanwhile the slave register keeps the precedent data; when it is ‘0’, the sense amplifier reads the data stored and the slave register becomes transparent and updates its output data from Qm. 401 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:49 from IEEE Xplore. Restrictions apply. aviation and space where the security of information is one of the most important considerations. VI. ACKNOWLEDGMENT The authors would like to thank Dr. P. Mazoyer and F. Jacquet of STMicroelectronics for the CMOS 90nm technology design kit, their support and some valuable suggestions. REFERENCES Fig.9 Simulation of Spin-MTJ based Flip-Flop; Qm is the output of sense amplifier. (Clk: 1GHz and Input data: 500MHz) Fig.10 Simulation of Spin-MTJ based Flip-Flop; the points A (10.091ns) and B (10.396ns) show that the propagation delay is abut 300 ps. V. CONCLUSIONS AND PERSPECTIVES Spin-MTJ based Non-Volatile Flip-Flop is presented in this paper. This technology is very promising and would allow logic circuit to work in low power dissipation and high speed with the same surface than SRAM based Flip-Flop. Nevertheless, all the results obtained here are still from the simulations, the first SMNFF demonstrator with CMOS 90nm low power process is under design in our laboratory in cooperation with STMicroelectronics and the University of Bielefeld. As the MTJ is intrinsically radiation-hard and nonvolatile, the application of SMNFF in FPGA and SOC (System-on-chip) then makes these chips non-volatile and secure, therefore it could be advantageously used in the field of  V.Stojanovic and G. Oklobdzija. “Comparative analysis of master-slave Latches and Flip-Flops for high-performance and low-power systems” IEEE Journal of solid-state circuits, Vol. 34, NO.4, April, 1999, pp.536-548  S. Wolf, D. Awschqlom, R. Buhrman, J. Daughton, S. Von Molnar, M. Roukes, A. Chtchelkanova and M. Treger, “Spintronics: A spin-based electronics vision for the future: Magnetism and materials” Science, 2001, Vol.294, pp.14881495  J.Hayakawa, S. Ikeda, Y. Lee, R. Sasaki, T. Meguro, F. Matsukura, H. Takahashi and H.Ohno “Current-driven magnetization switching in CoFeB/MgO/CoFeB magnetic tunnel Junction” Japanese Journal of Applied physics Vol44, pp.12671270, 2005  S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki and K. Ando “Giant room-temperature Magnetoresistance in sigle-crystal Fe/MgO/Fe magnetic tunnel junctions” Nature materials October 2004, pp:868-871  W. Zhao, E. Belhaire, V. Javerliac, Q. Mistral, E. Nicolle, B. Dieny and C. Chappert, “Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid MagneticCMOS design” IEEE International Behavioral Modeling and Simulation Conference, 2006, USA, pp.40-43  J.Z.Sun “Spin angular momentum transfer in currentperpendicular nanomagnetic junctions” IBM Journal of Research and Development, Vol50 January, 2006 pp.81-100  K.D.Belashchenko, J.Velev and E.Y.Tsymbal “Effect of interfaces states on spin-dependent tunneling in Fe/MgO/Fe tunnel junctions” Physical Review B, 2005, pp: 72-76  W.J.Gallagher and S.S.P.Parkin “Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip” IBM Journal of Research and Development Vol50, 2006, pp.5-23,  Design Rules Manuel, CMOS 90nm, Low Power (LP) process, STMicroelectronics  W.Zhao, E. Belhaire, V. Javerliac, C. Chappert and B. Dieny. “Evaluation of a Non-volatile FPGA based on MRAM technology”, IEEE International Conference on integrated circuit design and technology, Padova, Italy, 2006. pp. 17-21  T. Devolder, A. Tulapurkar, K. Yagami, P. Crozat, C. Chappert, A.Fukushima and Y.Suzuki “Ultra-fast magnetization reversal in magnetic nano-pillars by spin polarized current” Journal of magnetism and magnetic materials, vol.286,pp:77-83 2005  D.Curd, “Power consumption in 65nm FPGA” White paper : Virtex-5 FPGAs pp:4-5 Oct. 2006 402 Authorized licensed use limited to: CEA Saclay. Downloaded on November 7, 2008 at 07:49 from IEEE Xplore. Restrictions apply.