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Embrace the BRAIN Century: EDA Challenges in Neuromorphic Computing Hai Li and Yiran Chen Evolutionary Intelligence Lab (EI-Lab) Electrical and Computer Engineering University of Pittsburgh 1 What is Neuromorphic Computing? • An interdisciplinary technology that was inspired from biology, physics, mathematics, computer science, and electronic engineering to design artificial neural systems. (Wikipedia) • It is supposed to fulfill the weakness of von Neumann architecture in processing cognitive applications. • The relevant research has been well funded by all major funding agencies: • And supported in many countries: 2 Question I – Understanding? • Unfortunately we still do not know much about human brains. • The artificial neural network models also evolves over years. – Representation of neuron: 1943, McCulloch (Pitt) – The 1st learning rule: 1949, Hebb – Neuron nets: 1955, Dartmouth Summer Research Project on AI – STDP (Spike-timing-dependent plasticity): 1973, Taylor – CNN (Convolutional neural networks): 1989, LeCun • Do we really need to understand brains before designing a useful N.C. system? – No. Many useful systems have been prototyped, e.g., IBM TrueNorth. – The debates on “Emulative vs. Simulative”. 3 Question II – Platform? AD AD ASIC SC PE PR PO FPGA SC PE PR PO Application Specific IC Programmable Hardware Misra et al, Neurocomputing, 2010 Graf et al, NIPS, 2009 Misra et al, Neurocomputing, 2010 CPU AD Adaptivity (AD) Performance (PE) Power Efficiency (PO) Programmability (PR) Scalability (SC) AD NCA GPGPU SC PE PR PO General Purpose Platform P. J. Fox, Tech. Report, 2013 Graf et al, NIPS, 2009 SC PE PR PO Memristor Based Reconfigurable Design H. Li, HPEC, 2010 4, DAC, 2015 4 Question III – Technologies? • Are conventional CMOS and EDA technologies capable to support long-term research and development of N.C. systems? – Debates • Analog or Digital? Qualcomm, Zeroth Custom hybrid Spike neurons on chip Synapse off chip • Spiking-based or level-based? • Synchronous or asynchronous? • CMOS or Post-Silicon? – Other Challenges • Programmability J. Hsu, IEEE Spectrum, 2014 J. Gehlhaar, ASPLOS, 2014 HP, memristor X-bar Analog computing Dense connection • Security Stanford, Brain in Silicon Mixed-signal VLSI 1M neurons/16 chips 1B synapse/16 chips B. Benjamin, Neurogrid, 2014 D.B. Strukov, Nature, 2014 • Reliability • Scalability IBM, TrueNorth SRAM synapse Digital spike 1M neurons/chip 256M synapse/chip HBP Analog VLSI 64 neurons/chip 1024 synapses/chip S. Miller, ESANN, 2012 Micron, Automata Massively parallel Memory driven Non-von Neumann XML-based language F. Samarrai, UVAToday, 2014 5 Acknowledgement • Dr. Daniel Hammerstrom, Program manager, DARPA • Dr. Robinson Pino, Program manager, DOE • Dr. Dharmendra S. Modha, IBM Fellow and IBM Chief Scientist for Brain-inspired Computers • Dr. Mark Barnell, Senior computer scientist and program manager, US AFRL • Dr. H.-S. Philip Wong, Willard R. and Inez Kerr Bell Professor, Stanford University Q & A? 6