Download Analog and Mixed Signal Circuits On Digital CMOS Processes

Analog and Mixed Signal Circuits On Digital CMOS Processes
Jerry Twomey, Member IEEE
Abstract - CMOS processes that have been developed
primarily for logic are now increasingly used for analog and mixed signal applications. Process restrictions,
wide parametric variance, and noisy application environments lead to special efforts in circuit design/architecture, layout techniques, and optimizing the use of a
limited process. This paper addresses a combination of
techniques that provide a system development approach for mixed signal circuitry on digital CMOS
processes.
Index Terms - Mixed analog-digital design, MOS integrated circuits, CMOS analog integrated circuits, analog integrated circuits.
I. INTRODUCTION:
The motivations for using mixed signal designs on
CMOS are multiple. A dominant portion of IC’s now
produced are CMOS. Emphasis on high levels of system
integration creates wide demand for IC’s that can process
both analog signals and digital logic. High production
volumes of CMOS motivate a preference for process
compatible designs.
Cost of CMOS wafer processing is a major
consideration. These wafers typically have 7 to 9 masks in
their lithography/process, whereas a more versatile design
environment such as BiCMOS can have 17 or more. This
is reflected in wafer cost.
•
Methodology in layout and mask design
•
Empirical evaluation of silicon
Each of these areas is addressed, and cross
references on topics are provided.
II. PROCESS EVALUATION AND USE:
Restrictions of a Digital CMOS Process:
A digital CMOS process (DCP) optimizes
parameters for logic functionality: switching speed, low
voltage power supplies, submicron geometry, and high
component density. Considerations that address analog
and mixed signal circuits are not emphasized in the
definition of process parameters. Process elements
commonly used in analog signal processing are often left
out to keep process costs low.
A DCP restricts the process to those elements
necessary for logic design. A full set of bipolar elements
are not available; resistor structures are limited to process
layers used in CMOS transistors. Capacitors are often
implemented with the gate capacitance of CMOS
transistors. [1,2,3]
Process Characterization and Models:
Silicon needs analysis for items not usually
addressed in DCP models. These include:
Mixed signal designs on CMOS requires the use of
multiple techniques to achieve success. Items needing
special attention include:
Capacitors may have significant parasitic elements
that provides substrate coupling. These need to be
accounted for and included in simulation analysis.
•
Designing with a restrictive process
•
Noise isolation
•
Compensation for wide process variance
•
Decisions regarding digital/analog architecture
Resistors made from isolation wells can be bias
sensitive and have substrate leakage current. Resistance
can vary as a function of the DC bias to the substrate.
These resistors also have parasitic capacitance coupling to
the substrate that needs to be part of the element model.
Figure 1 briefly illustrates these items.
The procedure for development can be divided into
several areas:
•
Optimal use and evaluation of process
•
Techniques in circuit architecture
Page: 1
Capacitor
Physical Layout
Poly Gate
N-Well
Substrate
N-Well Resistor
A
N-Well
Substrate
Equivalent Circuit
Poly
Gate
N-Well
Substrate
B
A
B
Consequently, voltage headroom, in linear circuits,
can limit how the circuit is implemented.
CMOS Mixed Signal Elements:
Substrate
Figure 1. Parasitic elements.
Tolerable variance in process parameters is more
stringent for analog applications. Variation of elements
across multiple wafers and fabrication cycles requires
monitoring. Changes in threshold voltages, matching of
elements on a common wafer need to be carefully
analyzed, so the designer knows the variance that must be
compensated for.
Minimum geometry elements are used for logic
designs. These are often not acceptable for analog signal
processing. Parametric variance is generally higher for
smaller devices. This includes both active and passive
elements. Lithography variations on minimum geometry
resistors will cause higher variances than larger bodies.
These effects need to be analyzed so informed selections
can be made about element geometry.
Transistor models and simulation tools can have
problems not seen in digital simulations. Simulator
accuracy of charge conservation and linearity of transistor
models are frequently sources of error.
Examination of changes in transistor performance
due to short channel effects, threshold variance, and body
effect, should be done. [4,5,6]
Power Supply, Threshold Voltages, and Biasing
Circuits:
As DCP’s go to smaller geometry transistors, power
supply voltage must also decrease. Submicron CMOS is
now using 3.3 V or lower for system power.
Logic circuits are biased in the triode region or
turned off. Analog circuits require bias in the saturation
region, which has a higher drain to source voltage. Analog
circuits frequently require three to five transistors,
connected drain to source, between power and ground.
Page: 2
Threshold voltages restrict the number of transistors
that can be properly biased. Sometimes a higher supply
voltage is appropriate. However, processes can have low
breakdown voltages, which restricts the power supply.
Circuit elements that are not normally used on
DCP’s can be developed. This includes:
Substrate tied PNP transistors can be done on many
CMOS processes. [7] These devices have been
successfully used in Gilbert cell multipliers and matched
pairs in differential amplifiers.[8]
Isolation wells for CMOS devices can be forward
biased and used as diodes. Although tied to the substrate,
they are suitable for the development of thermally
compensated bandgap references.
Capacitor structures are available from the gates of
CMOS transistors or adjacent metal layer capacitors.
Ground tied capacitors can be developed using diffusion
and isolation wells to the substrate.
Designs on Transistor Arrays:
Some DCP’s use transistor arrays that are standard
to multiple IC’s. These transistors are minimum
geometry, suitable to logic designs. These “gate arrays”
use a unique set of metal layers to define circuitry.
Analog designs on gate array processes can be
deficient, because the designer cannot optimize the
layout. However success can be achieved in certain
applications.
The primary restriction of the gate array is its fixed
geometry. Variable channel widths and length can be
done using transistor arrays. (see Figure 2) DC bias results
are similar, but distributed capacitance in the layout can
degenerate performance. Parallel transistors to increase
channel width are frequently done; series arrays to
increase effective channel length are not commonly used.
Process parameters for such elements need
characterization to show viability. [2]
Drain
Drain
Gate
Bulk
Bulk
Bulk
Gate
Bulk
Source
Source
Channel width extension
Channel length extension
Figure 2. Use of fixed geometry transistors.
Designs with transistor arrays have greater success
at lower frequencies. However, selective layouts,
shielding, and noise isolation efforts cannot be done on
these devices.
Transistor arrays do not allow optimal designs.
Designs that can generate custom layouts are preferential.
Analog signal processing is more susceptible to
noise and process variances. Complexity of digital
implementations is sometimes increased, but die area of
digital implementation is often smaller.
Use of a digital equivalent on a DCP is
recommended whenever possible.
Analog Cells of Primary Importance:
Due to architecture and portability considerations, a
set of robust designs for converters between digital and
analog are of primary importance. Converter accuracy
needs to be maintained on a process that can have a large
amount of variance. [9,10,11,12,13]
Other analog cells necessary include:
•
Variable gain control cells: Provides amplitude range
for the converter inputs. Gilbert cell multipliers or
stepped gain amplifiers under digital control are both
feasible. [7,14]
•
Continuous time filters for: ADC inputs, to prevent
aliasing due to Nyquist rate limitations. DAC outputs, to minimize quantization noise on converter
outputs. [15,16,17,18,19,20]
III. CONSIDERATIONS IN CIRCUIT
ARCHITECTURE:
Design Portability:
Portability of a design to a new set of process
parameters becomes important due to the rapid evolution
of DCP’s. These processes are undergoing reduction of
transistors size, lowering gate threshold voltages, and
smaller power supply voltages.
At the gate level, synchronous logic designs are
largely immune to these changes; analog circuitry is not.
Digital designs allow easier portability between processes
and has become largely automated, based upon functional
definition in some form of hardware description language.
Analog designs require more analysis and validation.
Analog or Digital Architecture:
Decisions on circuit architecture depend largely on
the ability to quantize the signal. If acceptable signal
conversions between analog and digital can be performed,
digital signal processing can usually provide a suitable
transfer function.
Accuracy and sampling rates of converters become
the limiting factors of this strategy.
Ground Noise and Distribution of Control Bias:
Ground reference across the IC will have dynamic
variance due to substrate currents and inductance of the
metal layer ground connections. This results in noise from
switching transients between grounds across the IC.
Differential probing of ground on opposite sides of a logic
IC illustrates the problem.
Presence of ground noise dictates many of the
design mechanisms used on these IC’s.
Distribution of bias controls is commonly done by
two methods:
•
Distribution of reference current.
•
Distribution of reference voltage.
Small induced voltages can lead to a large amount of
current modulation in a current mirror. The equivalent
circuit model is shown in Figure 3.
Page: 3
Reference
Current
Distribution of
a reference
voltage
VSS
Transistors
separated by
distance on
the IC
VSS
Accuracy and Modulation of Current Mirror is dependent
upon potentials developed across the substrate.
VDD
Distribution
of a
reference
current
VSS
External
filter
capacitors
with
inductive
component
Noise between
separated grounds.
Reference
Current
Transistors
separated by
distance on
the IC
Power bondwire and
package inductance
External VDD
Mirror
Current
Internal
VDD
Package
Capacitors
Internal
Filter
Capacitors
Ground bondwire and
package inductance
External VSS
Internal
VSS
Figure 4. Equivalent Network for a power pin on an IC.
Mirror
Current
Noise
between
separated
grounds.
VSS
External filter capacitors need to be examined for
the frequency where they become ineffective. Due to
physical structure, all capacitors have reactive
components that cause variance from an ideal response.
Inductive resonance of ceramic surface mount capacitors
is shown in Figure 5. Above resonance, impedance of the
capacitor is dominated by its inductance, and is not an
effective filter.
Figure 3. Distribution of control bias across the IC.
Power Isolation:
Logic causes high frequency noise on the power
supply. Isolated power supplies for analog circuits should
be considered mandatory.
Power supplies will not always be quiet due to
internal noise coupling. Some noise will be present on all
nodes, and a multitude of techniques can be used to reduce
the net effect of this. This includes circuit architecture
internal to the IC, circuitry external to the IC, and internal
die layout. [21,23]
Capacitor self resonance for ceramic surface mount capacitors
Self-resonant frequency characteristics
10
Self-resonant frequency (MHz)
Distribution of a current across the IC avoids current
source modulation. The bias current is channeled through
a diode connected device at the local reference ground.
This provides a local voltage reference for control of the
current source.
1000
C1608
10
C2012
C3216
10
1
1
10
100
1000
10000
Capacitance (pF)
100000
Distributed Filtering:
Noise coupling is a distributed process. Isolation and
filtering, to be most effective, need to also be distributed
throughout the system. This involves filtering both power
and signal/control nodes.
Low frequency power filtering can be external to the
IC. However, the IC package and bond wire has
inductance that degenerates performance of external
filters at high frequencies. Figure 4 shows the equivalent
network for an IC package pin.
Page: 4
Figure 5. Equivalent network for a ceramic surface mount capacitor.
Distributed values of filter capacitors allow overlap
of resonance points, minimizing self resonance effects.
External filters need close proximity to the IC, to
minimize inductance of the connection.
Logic with rise/fall transients under 1ns lead to
spectral noise that defies external filters. Capacitors on
the die become necessary for high frequency filtering.
Classic
Nested
VDD
VDD
Power filtering for devices that use constant or low
currents may benefit from RC sections placed between the
power supply and the circuit. This will give a quieter
power source. Loss of voltage headroom due to the filter,
or voltage variations due to current surges needs review
for viability.
Long
Channel
Device
Noise Filtering of Control Signals:
In addition to power filtering, use of filters on
control signals will reduce noise. Figure 6 shows a
common implementation. This gives both differential and
common mode filtering relative to the local ground. The
response of the filter is ineffective to the spectral content
of the control signal. However, the filter provide
attenuation for the clocking frequencies of the logic.
Reference
Current
Mirror
Current
Reference
Currents
Mirror
Current
Note: Classic Cascode requires 2*Vth to bias properly. Nested
Cascode gives performance improvement of cascode, and
can use less bias headroom.
Figure 7. Comparison of Classic Cascode and Nested Cascode.
Differential Circuits:
VSS
CONTROL_A
+
CONTROL_B
VSS
Note:
1. Spectral content of “CONTROL A/B” is below the filter’s
frequency at which it starts to attenuate.
2. Switching noise, normally high frequency, is prevented
from entering the amplifier.
Figure 6. Use of distributed filtering on control signals.
Active filters are often not effective here. High
frequency noise can couple through the parasitic
capacitances of an active filter. RC filters are simple to
implement, but effective in limiting logic switching noise.
Systems operating in a noisy environment will
greatly benefit by using differential signals to minimize
noise coupling. Differential signals between stages, with
the lines routed together, will have common mode noise,
which can be removed by the receiver.
A differential transmitter and receiver can be used,
or, a ground referenced transmitter and a differential
receiver. The differential receiver processes both the
control signal and the transmitter’s ground reference.
(Figure 8) Both methods allow the common mode noise
reduction of a differential signal path, and remove ground
noise effects.
Fully differential system:
-
Cascode Isolation:
Current sources from the power supply will have a
greater isolation from noise with the use of a cascode
configuration. Cascode structures exhibit higher
impedance, and more closely approaches the ideal current
source that is desired. Headroom restrictions can inhibit
cascode use due to the voltage required for biasing.
Classic cascode structures use twice the threshold
voltage for biasing. Nested cascode structures (Figure 7)
can reduce bias headroom losses.
+
+ +
-
Amplifiers
separated by
distance on the IC
-
Differential receiver, processes
control signal and remote ground:
+
-
+
Amplifiers
separated by
distance on the IC
-
Figure 8. Passing of Differential Signals.
Page: 5
Differential receivers should be designed for a large
amount of common mode signal rejection.
9(a)
Bonding Pads
Signals off Chip, and Isolation for Control/Observation:
Circuits going outside the IC will usually have
increased noise coupling. Designs should review the need
to exit the IC and minimize the use of external signals.
Any noise sensitive signal should have a minimal
amount of routing attached. Common examples are: VCO
inputs in phase locked loops, comparator inputs, and the
inputs to op-amps. These can have a large amount of gain
and be very noise sensitive.
Frequently the need is for signal observation and not
signal control. In these cases, other methods to avoid offchip noise coupling can be pursued. Figure 9(a) shows the
problems associated with passing the signal off chip.
External noise coupled to the pin cause signal noise.
Figure 9(b) passes the signal internal to the IC and uses a
buffer amplifier to allow external observation. Figure 9(c)
allows signal observation, and the capability to connect to
the internal node. However, digital control allows the
node to be isolated from external noise if the observation
pin is not in use.
These methods improve noise performance while
allowing signal control/observation.
High Gain and High Impedance Circuit Nodes:
Connections outside the IC should require a large
amount of voltage swing to achieve the desired control.
Input circuits with a large amount of gain will be very
noise sensitive.
Noise present at the bond pads
will couple into the receiver.
9(b)
Bonding Pads
Signal is passed internally.
Buffer amplifier allows external
observation without adding noise
to the signal.
9(c)
Bonding Pads
Switch
Signal is passed internally, can
control node through external
bond pad if needed.
Can turn off outside connection
when not needed.
Figure 9. Passing signals external to the IC.
VSIGNAL
Z-source
VRECEIVE
Z-parasitic
Common examples of this are inputs of op-amps and
comparators. Op-amp inputs should remain internal to the
IC where possible.
Comparators should be bandwidth limited or include
hysterisis in the design for noise immunity.
High impedance nodes will be susceptible to noise
coupling. Most MOS circuits use gates of transistors as
amplifier inputs. Gate inputs are high impedance and
prone to noise coupling. In these cases, the impedance of
the circuit that drives the gate should be reviewed. The
high frequency impedance of the node needs to remain
low for noise immunity. Figure 10 illustrates the concept.
Page: 6
VNOISE
As: Z-source << Z-parasitic
Vnoise minimizes at Vreceive node.
Figure 10. Effect of source impedance on noise received.
Signals Between Analog/Digital Parts of the IC:
Digital controls need to be passed in/out of the
analog part of the IC. Some linear systems must remain
functional while controls change. These systems need to
exclude switching noise in the analog section. Figure 11
shows a three stage isolation method that works
reasonably well.
Calibration and Alignment:
Digital
Environment
Signal A
Analog
Environment
Q
Q
Signal B
Differential
Low Pass
Filter
Signal C
Analog
Circuit with
Nonswitch
Response
Signals:
Signal A
Signal B
Signal C
Figure 11. Passing of Digital control into Analog environment with
minimal noise effects.
Limit the slew rate of the digital control signal and
provide a differential output.
Pass the differential signals through filters with low
bandwidth, and referenced to the local analog ground.
Make sure that the receiver takes the “soft switched”
control and responds in a linear fashion. Input to a
comparator would immediately generate more switching
noise.
A multitude of techniques for offset, gain, and
operating point adjustment are available to the designer.
A partial listing includes:
•
Dynamic calibration.
•
Static calibration under digital control.
•
Static calibration while testing.
A simple example of each is included for
illustration:
Dynamic Calibration - Figure 12 shows a clocked
comparator, AC coupled, with the comparator offset
being cancelled by the voltage on the coupling capacitors.
Figure 12(a) shows the comparator in “precharge” mode.
Inputs are connected to a common voltage, and outputs
are fed back to drive the coupling capacitors. This forces
the inputs to the comparators crossover point. The
capacitors charge up to the offset voltage. Figure 12(b)
shows the comparator in “compare” mode. The input is
connected to the comparator through a capacitor voltage
that stores the input offset voltage.
12(a)
This provides the passing of digital control into the
analog environment with a minimal amount of noise.
Outputs of the differential control are routed as a pair, so
transients are complementary, and provide a minimal
noise source.
IN_PLUS
Precharge
Mode
OUT_PLUS
+ +
VDD/2
Offset
- -
OUT_MINUS
IN_MINUS
Element Matching and Offsets:
Junction mismatch effects manifest themselves as
offsets in amplifiers, and imprecise current mirror
matching. Circuit mismatches are more prevalent in DCP
devices because threshold voltage variances are larger
than those of bipolar junctions. Process control in DCP’s
can tolerate wide variances while producing acceptable
logic circuits.
Larger geometry elements and use of centroid
differential amplifiers reduce some variations, but size
increase does not always suffice. Larger geometry causes
bandwidth reduction due to junction capacitance, or
higher currents must be used to retain bandwidth.
To avoid these problems, process variances can
frequently be compensated for with calibration and
alignment circuits.
12(b)
IN_PLUS
Compare
Mode
OUT_PLUS
+ +
VDD/2
Offset
-
-
OUT_MINUS
IN_MINUS
Figure 12. Dynamic calibration/alignment - Offset cancellation in a
differential comparator.
Static Calibration Under Digital Control - Circuits
go through a digitally controlled alignment process for
compensation. An example of op-amp gain adjustment is
shown in Figure 13. Gain control is a function of resistor
ratios. One resistor has a switched R-2R ladder to allow
fractional gain adjustments. A digital counter is
incremented until the comparator state changes. This
Page: 7
value is maintained while the linear circuit is used. A
controlled, definable gain can be created.
V_SIGNAL
To: Alignment
Comparator
V_REFERENCE
Metal masks which includes small geometry fuses
can be forcibly opened by a voltage forced by the IC
tester. (Figure 15) The resulting high current opens a fuse
link. This process of “link blowing” allows permanent
adjustments while on the test system.
Ground
Bus
+
R
R
-
R
Normal
Signal Path
2R
2R
2R
To Switch Control
2R
Power
Bus
Metal
Probe
Pad
VSS
Fuse
Link
Resistor
Bottom
Top
Resistor
Figure 13. Static Calibration - Op Amp Gain Adjustment Circuit.
This type of system can be applied to compensate for
offsets, gain variance, current source matching, etc.
Static Calibration While Testing - The two prior
methods can compensate for many process variations.
These techniques are comparative, and suitable for many
applications. However, definition of a high accuracy
voltage requires a metering system as a reference
standard. Bandgap references can provide thermal
compensation, but will have errors due to offsets in the
differential amplifier. Figure 14 outlines a bandgap
reference that has static calibration under digital control.
BOND_PAD
VDD
VDD
RTOP
RTOP BOND_PAD
FUSE_LINK
FUSE_LINK
RBOTTOM
VSS
RBOTTOM
VSS
+
BANDGAP_OUT
Figure 15. Bottom resistor is present to allow forcing of logic high to
switch control. Elevation to higher voltage will open link and leave just
the top resistor as a pullup.
This technique can have reliability problems with
the fuse link remaining permanently open. A voltage step
will usually open a properly designed link reliably. Slow
elevation of voltage until the link opens is much less
reliable.
Laser trimming is not generally deemed as cost
effective in high volume production and techniques such
as “zener zapping” are not usually available on DCP’s.
Multiple other alignment/calibration methods exist.
[24,25,26] Of primary importance is the need to recognize
that the wide variance of a DCP requires these elements to
produce accurate and consistent functionality.
Amplifier Bandwidth:
-
VSS
Figure 14. Static Calibration while Testing - Bandgap with Fusable
Link Trimming.
Digital control from the IC tester determines the
proper digital pattern for a calibrated bandgap. This
pattern then requires permanent storage in the IC.
Page: 8
Linear circuits with proximity to digital signals
require designs that do not respond to switching noise.
Active gain stages should be designed with a spectral
response suitable only to the signals of interest.
Many designs include circuits with bandwidth above
the desired signal. Although noise can be eliminated by
bandwidth limiting/filtering of just the output circuits, it
does cause propagation of noise among internal circuits,
and onto power and ground lines.
Bandwidth limiting of amplifiers offers the added
bonus of power reduction, due to the correlation between
lower currents and lower bandwidth.
Electrostatic Discharge (ESD) Protection:
Diode protection is usually available for ESD
potentials below ground. Design of input elements should
consider larger geometry devices, allowing current
distribution over a wider junction area. Resistors in series
with input pins will help to provide ESD current limiting.
Latching ESD protection devices used for overvoltage
protection on digital input lines are applicable. [27]
IV. LAYOUT AND MASK DESIGN:
Shielding:
Additional noise reduction can be achieved in metal
mask design through judicious use of shielding. Use of
metal layer shields around analog signals is effective.
Figure 16 shows a shield on all sides which is electrically
connected by vias and grounded. Passing a signal as a
shielded differential pair will lower effects due to
common mode noise and variations between local
grounds.
Substrate Isolation and Guard Rings:
Substrate coupling is common to all elements on the
IC die. Noise transients generated in digital areas will be
present across the chip.
Guard rings consist of metal layer connections
which are connected to substrate taps. Depending on
process characteristics, low resistance diffusions are often
used under guard rings to improve isolation. The guard
ring creates a barrier to noise coupling. To be most
effective, guard rings need to be placed around the noise
source, and around circuits which need noise shielding.
The effect desired is to reduce the noise from the source,
and also reduce the noise at the receiver.
A single guard ring will help noise and ground
stability somewhat, but multiple rings, with the
distributed resistance of the substrate between rings will
work better. The reasons for this are illustrated in Figure 17.
The single guard ring allows potentials at the perimeter to
be connected directly to the other side of the ring. The
double ring structure allows noise shielding, but noise
couples to the second ring only through the resistance of
the substrate.
Split Guard
Ring
Top View
Wide Guard
Ring
Two layers of metal: shield is
placed towards substrate.
Signal -
Signal -
Signal +
Cross Sectional View
Signal +
One dimensional model of substrate resistance and guard
ring isolation.
Three layers of metal:
fully enclosed signal path.
Figure 16. Differential channel shield.
Noise isolation needs to be optimized at the receiver.
For this reason the shield should be connected to a ground
reference at the receiver only. Shielding of a nondifferential
signal will still be susceptible to ground noise.
Substrate Resistance
Substrate Resistance
Figure 17. Split guard rings vs. wide guard rings.
Although models for substrate noise have been
attempted, accurate models are questionable due to the
large number of parasitic elements present. Empirical
methods to directly measure noise magnitude on the
substrate are available. [22]
Placement of Pins and Bonding Pads:
Grouping of analog signals away from digital pins is
suggested. Digital input/output cells generate large noise
transients due to the currents necessary to drive external
loads. Ground pins between digital and analog pins are
desirable.
Page: 9
Grouping of logic signals will also help. Any logic
signals that are near the analog pins should be static
digital controls. Clocks and high frequency data paths
should be kept away.
Mixed signal cells, should be placed such that the
analog side of the cell is beside the bonding pads that will
have analog signals. This minimizes routing of analog
signals, and gives less opportunity for noise coupling.
Distribution of Filter Capacitance:
V. EVALUATION OF SILICON:
Filter capacitors can take up die space, but, are
needed for noise performance. However, filter capacitors
can often be added without affecting die size. As layout
designs near completion, the designs should be reviewed
for empty areas that are not actively used. These can be
filled with filter capacitors.
Although a circuit may function properly in
simulation, proper functionality can only be validated
through silicon testing. Transistor models developed for
logic may have sufficient accuracy, but analog designs
often require more precise models. Simulation needs to be
used as a tool for sensible design.
A large amount of die space is used for metal layer
routing. Most capacitors are in base layers, underneath the
metal. This allows designers to put distributed filter
capacitance underneath any area that is only used for
metal routing.
Evaluation testing needs to be performed over
extremes of temperature and power. Performance over
process variance can be evaluated using IC’s from
different wafers and multiple wafer lots.
Power buses for distribution of power and ground
are frequently routed beside each other. These can be
placed on top of each other. This provides a power filter
capacitor between metal layers, and reduces die area.
Also, a filter capacitor can be placed under the power bus
areas.
Design validation should be in a similar
environment to that of the final application. This includes
a noisy digital environment outside the cell. Figure 18
suggests a test environment. The analog test cell is
surrounded by a group of logic cells that are chained
together under a common clock. The logic cells are
underneath the control of an external clock, which can be
swept in frequency.
Sizeable power filter capacitors can be included
using these methods.
Exclusion of Noisy Signal Sources:
Routing of digital signal over analog cells will
increase noise coupling. Two methods to avoid this are
suggested:
Some layout tools have blocking layers, to prevent
routing.
A guard ring at the cell perimeter using all metal
layers in its design will make crossover routing
impossible.
As part of a cell library, the cell and IC designers are
often different. For this reason, design of the mixed signal
cell should anticipate, and try to circumvent noisy signal
routing.
Layout and Placement of Mixed Signal Cells:
Routing of logic controls out one side of the cell, and
analog signals out the opposite side is advised.
Page: 10
Analog Cell
+
-
Bond pads at edge of chip
Figure 18. Test environment: Analog cell with noisy digital
environment around it.
This allows functional testing, with noise injection
and an empirical evaluation of noise immunity.
VI. CONCLUSION:
A number of items key to analog design on a DCP
have been touched upon. Including:
Process Characterization and CAD Models:
[4] Y. Tsividis et. al., “MOSFET Modeling for Analog Circuit
CAD: Problems and Prospects.”
IEEE J. Solid-State Circuits, vol. 29, No. 3, pp. 210-216,
March 1994.
•
Optimal use of a restrictive process
•
Process evaluation
•
Threshold and bias limitations
•
Designs on gate arrays
•
System architecture considerations
•
Cells of primary importance for a library
•
Distributing control bias
Bipolar Transistors on CMOS:
•
Power Isolation and distributed filtering
•
Circuits for noise isolation
[7] T. Pan et. al., “A 50-dB Variable Gain Amplifier Using
Parasitic Bipolar Transistors in CMOS,” IEEE J. Solid-State
Circuits, vol. 24, No. 4, pp. 951-961, August, 1989.
•
Control signals that do not disturb functionality
•
Offsets and mismatching concerns
•
Calibration and alignment
•
Layout methods to optimize performance
•
Silicon evaluation
A single document cannot provide in depth coverage
of these topics. However, all of these items require
consideration for successful designs.
VII. ACKNOWLEDGMENTS:
My thanks to the members of several groups at LSI
Logic: Mixed Signal Design, Mask Design/Layout,
Technical Publications, and Modeling/Process
Development. Also, my thanks to Christine Ingalls for her
help and support.
REFERENCES
CMOS System Design Considerations:
[1] Y. Tsividis, “Analog MOS Integrated Circuits - Certain
New Ideas, Trends, and Obstacles,” IEEE J. Solid-State
Circuits, vol SC-2, No. 3, pp. 317-321, June 1987.
[2] P. Duchene, et. al., “Analog Circuit Implementation on
CMOS Semi-Custom Arrays,” IEEE J. Solid-State Circuits,
vol. 28, pp. 872-874, July 1993.
[3] P. Gray et. al., “Design Considerations for a High
Performance 3-um CMOS Analog Standard-Cell Library,”
IEEE J. Solid-State Circuits, vol. SC-22, No. 2, pp. 181-189,
April 1987.
[5] H. Haddara, “Characterization Methods for Submicron
Mosfets”, 1995, Kluwer Academic Press.
[6] K. Lakshimikumar et. al., “Characterization and Modeling
of Mismatch in MOS Transistors for Precision Analog Design,”
IEEE J. Solid-State Circuits, vol. SC-2, No. 6, pp. 1057-1066,
December, 1986.
[8] E. Vittoz, “MOS Transistors Operated in the Lateral
Bipolar Mode and Their Applications in CMOS Technology,”
IEEE J. Solid-State Circuits, vol. SC-18, No. 3, pp. 273-279,
June, 1983.
Data Converter Technology:
[9] A. Karanicolas, et. al., “A 15-b 1-Msample/s Digitally SelfCalibrated Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28,
No. 12, pp. 1207-1215, December, 1993.
[10] B. Razavi, et. al., “A 12-b 5-Msample/s Two-Step CMOS
A/D Converter,” IEEE J. Solid-State Circuits, vol. 27, No. 12,
pp. 1667-1677, December, 1992.
[11] M. Flynn, et. al., “CMOS Folding A/D Converters with
Current-Mode Interpolation,” IEEE J. Solid-State Circuits,
vol. 31, No. 9, pp. 1248-1257, September, 1996.
[12] A. Venes, et. al., “An 80-MHz, 80-mW, 8-b CMOS
Folding A/D Converter with Distributed Track-and-Hold
Preprocessing,” IEEE J. Solid-State Circuits, vol. 31, No. 12,
pp. 1846-1853, December, 1996.
[13] P. Yu, et. al., “A 2.5-V, 12-b, 5-Msample/s Pipelined
CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, No. 12,
pp. 1854-1861, December, 1996.
Variable Gain Amplifier Design:
[14] J. Rijns, “CMOS Low-Distortion High-Frequency
Variable-Gain Amplifier,” IEEE J. Solid-State Circuits, vol. 31,
No. 7, pp. 1029-1034, July, 1996.
Continuous Time Filter Design:
[15] B. Stefaneli et. al., “A 2-um CMOS Fifth-Order Low-Pass
Continuous-Time Filter for Video-Frequency Applications,”
IEEE J. Solid-State Circuits, vol. 28, No. 7, pp. 713-718,
July 1993.
Page: 11
[16] Y. Tsividis, “Integrated Continuous-Time Filter Design An Overview,” IEEE J. Solid-State Circuits, vol. 29, No. 3,
pp. 166-176, March 1994.
[17] C. Wu et. al., “The Design of CMOS Continuous-Time
VHF Current and Voltage-Mode Lowpass Filters with
Q-Enhancement Circuits,” IEEE J. Solid-State Circuits, vol. 31,
No. 5, pp. 614-624, May, 1996.
[18] A. Durham et. al., “High Linearity Continuous-Time Filter
in 5V VLSI CMOS,” IEEE J. Solid-State Circuits, vol. 27,
No. 9, pp. 1270-1276, September, 1992.
[19] T. Kwan et. al., “An Adaptive Analog Continuous-Time
CMOS Biquadratic Filter,” IEEE J. Solid-State Circuits, vol. 26,
No. 6, pp. 859 - 867, June, 1991.
[20] Z. Chang, et. al., “A Highly Linear CMOS Gm-C
Bandpass Filter with On-Chip Frequency Tuning,” IEEE J.
Solid-State Circuits, vol. 32, No. 3, pp. 388-397, March, 1997.
[26] C. Mensink, et. al., “A CMOS ‘Soft-Switched’
Transconductor and Its Application in Gain Control and
Filters,” IEEE J. Solid-State Circuits, vol. 32, No. 7,
pp. 989-997, July, 1997.
ESD Protection:
[27] M.-D. Ker, “ESD Protection for CMOS Output Buffer by
Using Modified LVTSCR Devices with High Trigger Current,”
IEEE J. Solid-State Circuits, vol. 32, No. 8, pp. 1293-1296,
August, 1997.
General Purpose CMOS Design References:
[28] P. Allen and D. Holberg, “CMOS Analog Circuit Design”,
1987, Publisher: Holt Rinehart and Winston,
ISBN: 0-03-006587-9.
Noise Characterization and Control:
[29] R. Gregorian and G. Temes, “Analog MOS Integrated
Circuits for Signal Processing”, 1986, Publisher: John Wiley
and Sons, ISBN: 0-471-0979-7.
[21] M. Ingels et. al., “Design Strategies and Decoupling
Techniques for Reducing the Effects of Electrical Interference
in Mixed-Mode IC’s,” IEEE J. Solid-State Circuits, vol. 32,
pp. 1136-1141, July 1997.
[30] R. Unbehauen and A. Cichocki, “MOS Switched
Capacitor and Continuous-Time Integrated Circuits and
Systems”, 1989, Publisher: Springer-Verlag,
ISBN: 3-540-50599-7.
[22] K. Makie-Fukuda, et. al., “Measurement of Digital Noise
in Mixed-Signal Integrated Circuits,” IEEE J. Solid-State
Circuits, vol. 30, No. 2, pp. 87 - 92, February 1995.
[31] A. Grebene, “Bipolar and MOS Analog Integrated Circuit
Design”, 1984, Publisher: John Wiley and Sons,
ISBN: 0-471-08529-4.
[23] J. Olmstead, et. al., “Noise Problems in Mixed AnalogDigital Integrated Circuits”, IEEE 1987 Custom Integrated
Circuits Conference, pp. 659-662.
AUTHOR BIOGRAPHY:
Alignment and Calibration Circuits:
[24] J. Atherton et. al., “An Offset Reduction Technique for
Use with CMOS Integrated Comparators and Amplifiers,”
IEEE J. Solid-State Circuits, vol. 27, No. 8, pp. 1168 -1175,
August 1992.
[25] T. Gabera, et. al., “Digitally Adjustable Resistors in
CMOS for High Performance Applications,” IEEE J. SolidState Circuits, vol. 27, No. 8, pp. 1176-1185, August 1992.
Page: 12
Jerry Twomey received a BS and MS in electrical
engineering from Worcester Polytechnic Institute in 1979
and 1982.
He has done mixed signal IC design for mass storage
and data communication systems. He is presently at LSI
Logic, Milpitas California, as part of their Mixed Signal
Design group.