Download An Improved Current Mode Logic Latch

Chinese Journal of Electronics
Vol.22, No.1, Jan. 2013
An Improved Current Mode Logic Latch∗
ZHANG Wei1 , ZHANG Liang1 , ZHANG Xu1 , MA Xuepo1 and LIU Yanyan2
(1.School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China)
(2.College of Information Technical Science, Nankai University, Tianjin 300071, China)
Abstract — In order to reduce power consumption
and additional chip area, an improved Current mode logic
(CML) latch, which can work at a lower power supply without the level shifter, is presented. To compensate the speed
loss caused by large voltage swing, a cross coupled pair is
added to the load of the latch. A simplified model which
divides operating situation into different phases is built
to illustrate the operating principle of the structure and
optimize the speed of the circuit. Further analysis also
indicates that the latch can work at a much lower voltage supply. The proposed divider has been used in a frequency synthesizer. Measurements were made to support
above features. It has been proved that the structure in
this work has more advantages than the conventional ones.
Key words — Current mode logic (CML), Low power
supply, High speed divider.
voltage is VDD − Ibias · R, where R is the load resistance.
The conventional CML latch is difficult to be used in low
power application, because of the existence of constant current
bias, which needs a certain voltage level, and will constrain the
adjusting ranges of other parts[11−13] . That is to say the conventional CML latches use a relatively large voltage supply to
generate the required small output, which means power waste.
In this paper, a novel CML latch is proposed to achieve a high
speed with low power supply. This circuit can work with a
small voltage source and generate a relatively large output
swing utilized directly by CMOS logic circuits without the
level shifter.
II. Design of CML Latch
Fig.2 shows the proposed CML latch. Compared to the
I. Introduction
Millimeter wave and radio frequency circuits are developing rapidly nowadays, such as frequency synthesizers and timing recovery circuits[1,2] . The high speed frequency divider
plays a critical part in these circuits[3] . More importantly,
because of the high frequency operation nature of the block,
its power consumption accounts for a great portion of that of
the system[4,5] . Commonly, there are three types of frequency
dividers: static, dynamic and injection locked[6] . Because of
its narrow locking range and sensitivity to process variation,
injection locked frequency dividers are not adopted in commercial products, even though such configuration can work at
a very high frequency with low power dissipation[7,8] .
Due to the characteristics of low voltage swing, high operating frequency and immunity to the common mode noise, the
Current mode logic (CML) dividers are now widely used[9] .
Static CML dividers which can operate at tens of GHz have
been reported[10] . Fig.1 shows the conventional topology of
a CML latch which consists of a latch part and a track part.
When the input CLK is high (CLKB is low), the latch operates at the track mode, allowing the input to propagate to
the output. When the input CLK is low (CLKB is high), the
circuit operates at the latch mode, i.e. the signal is latched,
and there is no signal that could pass through the circuit. The
highest voltage at output node equals VDD , and the lowest
Fig. 1. Conventional topology of the CML latch
Fig. 2. Topology of proposed CML latch
∗ Manuscript Received Aug. 2011; Accepted May 2012. This work is supported by the National Science and Technology Major Project
of the Ministry of Science and Technology of China (No.2012ZX03004008) and the Fundamental Research Funds for the Central Universities.
An Improved Current Mode Logic Latch
conventional topology, there is no tail current source, and the
load resistors are replaced by P-type MOSFETs (M1 and M2)
with their gates connected to ground. This configuration is
some similar to one proposed by Ref.[14]. However, in this
paper, the lower supply feature is discussed in details. In addition, a cross coupled pair (M5 and M6) is added to compensate
the speed loss caused by larger output swing.
Such structure comes with a large output voltage. When
the output voltage transits from “low” to “high” (or reverse),
the load transistors (M1 and M2) may experience different operating regions. The conditions for different operating regions
are listed below.
VDS ≥ VGS − VT H
(1)
VDS ≤ VGS − VT H
(2)
When expression (1) is satisfied, the MOSFET operates at
the saturation region, and if not, the MOSFET operates at
the triode or the cut off region. VGS of the load transistors
(M1 and M2) is VDD . With simple derivations, we arrive at
the following expressions:
VOU T , VOU T B ≥ VT H
(Triode region)
(3)
VOU T , VOU T B ≤ VT H
(Saturation region)
(4)
There are two operating modes of the circuit: the track
mode and the latch mode. Assuming that the CLK is high,
the circuit works in the track mode. Then, the latch transistors
(M9 and M10) could be omitted, and in this case, M7 degrades
to a resistor. Since the cross coupled transistors (M5 and M6)
are adopted to speed charging or discharging the output capacitance, in the following analysis, they are also omitted.
215
the voltage across it is below the threshold voltage, M3 enters
triode region and serves as a resistor, and so does M7. Based
on the above analysis, the operation of the circuit could be
divided into two phases according to the voltage at the output node. The simplified model of our proposed CML latch is
shown in Fig.3.
1. The speed of the circuit
As a general opinion, the maximum operating frequency of
the latch is limited by signal propagation delay time through
the circuit,
1
(5)
fMAX ≤
2τpd
where fMAX is the maximum
operating frequency and τpd
is the propagation delay in
the sampling period, which
equals to Req Ctot .
When M4 is turned off,
the capacitance connecting
to OUT will be charged
through M2 with equivalent
output resistance Req2 . As
it could be seen in Fig.4,
Ctot is charged by VDD
Fig. 4. The charging process of
node OUT
through Req2 , where Ctot is
the total equivalent capacitance at output node OUT.
Ctot = Cpar + Cload
where Cpar is the parasitic capacitance, such as the drain-bulk
junction capacitance, and Cload is the load capacitance, which
is mainly determined by the gate capacitance of the next stage.
As a matter of fact, the value of Cload is proportional to
the area of the gate. To increase speed, the minimum length of
the gate is set. However the width of transistors at the input
stage cannot be reduced arbitrarily. The transconductance of
the transistor, gm , decreases as the shrinking of the width,
and further, the input stage’s voltage gain Av that equals to
gm · Req would be decreased, which would result in the failure
of the circuit.
When it comes to Req , which equals to:
Req = (RM 3/4 + RM 7/8 )||RM 1/2
Fig. 3. Simplified model of our proposed CML latch on two
different phases
When the input D is low, the transistor M3 is turned off.
No current would flow through the left branch, and the load
transistor M1 works at the triode region. At this time, M1
only displays a very small resistance, Req1 . When the input D
transits from 0 to 1, the current would be gradually drawn to
the left branch from the right one. Then, the voltage at the
node OUTB goes down. As the voltage of the node OUTB
drops below the threshold voltage, and VT H , M1 no longer
operates at the triode region; instead, it enters the saturation
region and acts as a current source. Meanwhile, M2 transits
from the saturation region to the triode region, and thus can
be treated as a resistor. Since the gate level of M3 is high and
(6)
(7)
where RM 1/2 is the corresponding resistance of M1 or M2,
RM 3/4 is the resistance of M3 or M4 and RM 7/8 is the resistance of M7 or M8. Since RM 3/4 and RM 7/8 have obvious
nonlinear features, to get an instructive result with enough accuracy, different working regions should be considered. Here
the method of describing function[15] is used to get the result
of Req . That is,
Vout
2Ibias
Vin
=
2Ibias
RM 3/4 =
(8)
RM 7/8
(9)
Adopting the highest current as 2Ibias and assuming that
at this time every transistor is in the triode region, we have
2Ibias =
μn Cox w
(Vin − Vth )Vo−low
l
(10)
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Chinese Journal of Electronics
2013
where Vo−low is the lowest output voltage, and it equals
(RM
3/4 + RM 7/8 )
. RM
VDD ×
3/4 and RM 7/8 are re
(RM 1/2 + RM
3/4 + RM 7/8 )
sistances of the corresponding transistors in the triode region.
μn , Cox and l are M7’s parameters and w is M7’s width. Then
To accelerate the charging speed, a cross coupled pair (M5
and M6) is added, which can help reinforce the charging process as it constitutes a positive feedback. Fig.5 also provides
the comparison between the working situations with and without a cross coupled pair, and the former one is represented by
the solid line. Under the same circumstances, with the help of
(Vin + Vout )l
||RM 1/2
Req =
a cross coupled pair, a latch can raise itself to a higher level,
μn Cox w(Vin − Vth )Vo−low
and it can reduce charging time by about 55ps at a working
(Vin + VDD − Vo−low )l
=
||RM 1/2
frequency of 1GHz.
μn Cox w(Vin − Vth )Vo−low
Table 1 shows some main characteristics of the divider, of
RM 1/2
which
the charging time of the output determines the speed of
V
l
Vin l +
DD
RM 1/2 + RM
+ RM
3/4
7/8
the
circuit.
And according to the charging time listed below, it
=
||RM 1/2
RM
changes a little in relatively low frequency because of the same
3/4 + RM 7/8
μn Cox w(Vin − Vth )
VDD
RM 1/2 + RM
working conditions of MOSFETs under all range of frequency.
3/4 + RM 7/8
It means that the output almost maintains the same when the
(11)
frequency changes during this region.
Thus, an equivalent circuit which gives sufficient accuracy
Table 1. Characteristics of the improved CML divider
for adjusting MOSFETs is obtained. According to Eq.(11), to
Working
Charging
Output
Current
acquire the smallest Req : firstly, Vin must be small, however
frequency
(GHz)
time
(ps)
swing
(V)
consumed
(mA)
there is a limit that Vin must be high enough to make M7/8 ef1
155
0.250∼3.301
1.248
fective switches; secondly, widening the width of M7, but this
2
144
0.298∼3.254
1.440
way always goes along with enlarging the capacitance, which
3
171
0.400∼3.205
1.540
is much worse; finally, reducing RM 1/2 which means widening
4
183
0.491∼3.117
1.568
the width of PMOS transistors, and because they contribute
little capacitance to the capacitance Ctot , this method tends
2. The swing consideration
to be very effective.
For the sake of brevity, the illustration of phases in Fig.3
By virtue of instructions of analysis above and simulations,
is used to calculate the output swing. Then the minimum
results indicate that to achieve higher speed, the W/Ls of M1
voltage of the output would be
and M2 need increasing, and the W/Ls of M3 and M4 should
(12)
Vlow = Iload (Req3 + Req7 )
be decreased. It can also be noted that the cross coupled pair
M9 and M10 with the same size as M3 or M4 can guarantee
where Req3 and Req7 is the equivalent output resistance of M3
the proper function of the circuit.
and M7, respectively, and Iload is the saturated current of the
As mentioned above, such CML latch can provide big sigload transistor M1 (or M2). Then, the swing of the output is
nal outputs. On one hand, it is beneficial to reduce extra level
(13)
Vswing = VDD − Iload (Req3 + Req7 )
shifters by connecting with CMOS logic directly. But on the
other hand, it requires more time and driving capability to
As mentioned above, if the length of the transistor is set to
swing. This would increase the charging time and impact the
the minimum value, then
wave shape of the output. The output shape of the latch with(14)
Req ∝ L/W
out a cross coupled pair is shown as the dashed line in Fig.5.
When the low level is settled, the high level of the differenand
L
L
tial counterpart has not been settled, which indicates that the
(15)
Vlow ∝ Iload
+
W 3
W 7
rising time is longer than the falling time. So the charging
From Eqs.(13) and (14), we know that if Req3 , Req7 and
time which determines the high level settling, would be the
Iload are all kept small, a near full swing output can be
dominant factor in the limitation to the speed of CML.
achieved. Fig.6 shows the simulation results of the W/Ls of
M7, M3 and M4 vs. Vlow . It was carried out based on Chartered 0.35um RF CMOS technology and the power supply is
3.3V. The curves in the figures could be approximately described by the following equation,
L
+b
(16)
Vlow = a
W M 7,M 3&M 4
Fig. 5. Comparison of charging time between latches with and
without the cross coupled pair
where a and b are two constants.
However, the optimization on swing may slow down the
circuit, because larger gate width means larger gate parasitic
capacitance which would prolong the time of charging or discharging at the output node. Carefully designing and compromising among these parameters would lead to a closed full
swing circuit with desired operating speed.
An Improved Current Mode Logic Latch
217
operating frequency with the same small output swing as the
conventional one. As the power and source voltage decrease,
the conventional divider cannot even work resulting from the
failure of loop gain requirement. However the improved divider
is able to work with less energy and lower voltage supply.
Fig. 6. Simulation results of Vlow vs. W/Ls of M7, M3 and
M4
3. Low power supply operation
The proposed circuit has better performance in low power
supply applications than the conventional ones.
Assume that CLK in Fig.1 is VDD and CLKB is VDD −
Vswing . To ensure that M3 is off, VA would be no less than
VDD − Vswing − VT H3 . On the other hand, VA is at least
VBIAS − VT H1 to keep M1 in saturation operating region. So
the power supply of the conventional CML latch has a dynamic
region of (VDD − Vswing − VT H3 ) − (VBIAS − VT H1 ), which
equals to VDD − Vswing − VBIAS . The lowest value of power
supply voltage must be larger than Vswing + VBIAS . However,
when VDD continues decreasing, M1 is forced to get into triode region, which means smaller and unstable tail current and
output swing.
On the contrary, the improved CML latch could work at
a relative lower power supply. Assume that CLK in Fig.2 is
VDD , CLKB is VOU T , and voltages at node D (VD ) and DQ
(VDQ ) are VDD and low, respectively. The left branch is on
and its output is low. Since VOU T is small, the difference between VB and VOU T can be ignored. M3 and M7 both work
at the triode region. The current of two transistors is:
IM 3/7 =
μn COX Wn
(VDD − VT Hn )VOU T
Ln
Fig. 7. (a) A divide-by-2 divider based on CML latches; (b)
Comparison between dividers with conventional and
improved CML latches
(17)
M1 works at the saturation region, and the current across it
is:
μp COX Wp
(VDD − |VT Hp |)2
(18)
IM 1 =
2Lp
Reasonably assuming that IM 1 = IM 3/7 , VDD − VT Hn ≈
VDD − |VT Hp |, since k = (μn COX Wn Lp )/(μp COX Wp Ln ), the
lowest VDD could be calculated as kVOU T /2 + |VT Hp |. The
improved CML latch could work nearly at the power supply
of VT Hp theoretically, which is much lower than that of the
conventional structure.
III. Simulations and Measurements
A typical divide-by-2 divider based on CML latches is
shown in Fig.7(a). With the same power dissipation, comparisons of working conditions between dividers consisting of
conventional and improved structures are shown in Fig.7(b).
As the curves indicate, the average ratio of output swing
to VDD is 70% for the improved structures, and 8% for the
conventional ones. Under such circumstances the frequencies
of the improved divider are only a little lower than those of
the conventional type. It is also noted that the power dissipation in the improved dividers was reduced regardless of level
shifters which will cost an extra large amount of energy. In
addition, the improved divider actually achieves a much higher
Fig. 8. Output waveform of the implemented divider under
1V power supply at 8MHz
A frequency synthesizer had been designed and fabricated
under Chartered 0.18μm RF CMOS technology. It has the
high frequency dividing circuit inside based on the proposed
CML latch with master-slave configuration, which is driven
by a VCO. The VCO’s frequency is around 2 GHz. The high
frequency divider directly drives the following CMOS divider,
and they have a total ratio of 70. The output frequency of
the whole circuit combined by CML and CMOS dividers is
28.53MHz, and the CML divider can work properly.
An independent divider by 16 was also implemented under
Chartered 0.35μm RF CMOS technology to verify the lowest
power supply working condition. In the testament, VDD is set
as 1V and the input frequency is 8MHz. The result shown in
Fig.8 indicates that the divider can work correctly at the low
power supply as analyzed in Section II.3.
Compared to the conventional CML divider, the improved
Chinese Journal of Electronics
218
one contains no resistors, which means the possibility of
smaller layout area and less dependent on process variation.
IV. Conclusion
An improved CML divider is presented. It can work at a
high frequency with lower voltage supply. Based on the analysis of speed and output situations, the W/Ls of all MOSFETs
in the circuit are set carefully. Simulation and measurement
results show that the circuit has good characteristics. Compared to the conventional type, not only could the power supply be reduced to a lower level, but also the improved circuit
could connect to CMOS logic directly.
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ZHANG Wei
received the B.S.,
M.S. and Ph.D. degrees in 1997, 2000 and
2002, respectively all from Tianjin University, Tianjin, China. Since then, he has
been with School of Electronic Information Engineering, where he is currently a
professor. His research interests include
CMOS radio-frequency integrated circuits
for wireless communications and VLSI implementation for signal processing systems.
(Email: [email protected])
ZHANG Liang
received the B.S.
degrees from School of Electronic Information Engineering of Tianjin University,
Tianjin, China, in 2010. He is currently
working toward the M.S. degree in School
of Electronic Information Engineering of
Tianjin University, Tianjin, China. His research interests are in the field of CMOS
radio-frequency integrated circuits such as
VCO and frequency synthesizer for wireless
communications. (Email: [email protected])
ZHANG Xu received the B.S. and
M.S. degrees from School of Electronic Information Engineering of Tianjin University, Tianjin, China, in 2009 and 2012 respectively. He is going to pursue Ph.D.
degree at Iowa State University. His research interests focus on radio-frequency
integrated circuits such as prescaler, LNA,
mixer and PA for communication circuits.
(Email: zhangxu [email protected])
MA Xuepo received the B.S. and M.S. degrees from School
of Electronic Information Engineering of Tianjin University, Tianjin, China, in 2007 and 2009 respectively. He is currently pursuing
Ph.D. degree at University of Texas at San Antonio. His research interests focus on signal processing for bioinformatics and biomedical
applications. (Email: [email protected])
LIU Yanyan received B.S and M.S. degrees in 1999 and 2002
from Tianjin University, respectively and received Ph.D. degree in
2010 from Nankai University, Tianjin, China. She is currently a
lectuer in School of Information Technology and Science of Nankai
University. Her research interests include integrated circuits design
and microdisplay technology. (Email: [email protected])