Download 2.555new7 - WordPress.com

Application of Special I.C’s.
The 555 Timer, 555 as Monostable, Astable Multivibrator and
Applications, Phase Locked Loops, Operating Principles.
Inside the 555 timer there are
• Over 20 transistors, 15 resistors,
2 diodes, depending of the manufacturer.
• Supply voltage between 4.5 and 18 volt, supply current 3 to 6 mA,
• Sinking or sourcing 200 mA of load current.
•
Rise/Fall time of 100 nSec.
• The Threshold current determine the maximum
• value of Ra + Rb. For 15 volt operation the
• maximum total resistance for R, i.e. (Ra +Rb) is 20 Mega-ohm.
• The temperature variation is only 50ppm/°C (0.005%/°C).
Inside the 555
• Note the voltage divider inside the 555 made up of 3 equal 5k resistors
Salient Functional Features of 555.
1. Trigger (Pin2) <1/3 Vcc, sets Vo (Pin3) to “1”.
Once triggered even pin2 is made 1 or 0 there
is no change in the output.
2. Threshold (Pin6) > 2/3 Vcc sets Vo (Pin3) to “0”
3. Reset “0” (Pin4) sets Vo to “0” any time.
Usually it is at “1”
4. Initially (Pin7) is set to ground as the power
supply is on.
Note that the trigger pulse must actually be of
shorter duration than the time interval determined
by the external R and C. When pin 2 is held low
longer than that, the resultant output will remain
high until the trigger input is driven high once again.
In the mean while even pin2 is made 1 or 0 there is
no change in the output.
Monostable Operation or Timer.
Initial Condition:
R(0), S(1)
1. Threshold Comparator.
Ref: Inv(-) at 2/3 Vcc
2. Trigger Comparator.
Ref: non Inv(+) at 1/3 Vcc .
Q2 is a PNP transistor used to
reset and make a short the
NPN transistor when Pin.4
(Base) is grounded. Usually
Pin.4
is connected to + of
power
R-S Flip Flop
S
0
0
1
1
S
Q
R
Q
R
0
1
0
1
OUTPUT Q
No Change
0
1
Not allowed
REMARK
FF Resets
FF Sets
Supply so that transistor is open. Pin.5 is at 2/3 Vcc. The comparator output
is –ve, Q is 1 making short of pin.7 to ground.
Monostable Operation or Timer.
DERIVATION
• The time t1 taken by the circuit to charge from 0 to (2/3) Vcc is
• t1 = 1.098RC
• The time t2 taken by the circuit to charge from 0 to (1/3) Vcc is
• t2 = 0.405 RC
• The time to charge from (1/3) Vcc to (2/3) Vcc is
• tHigh = t2-t1 = 1.098RC - 0.405 RC = 0.693 RC
Connecting a Load.
Current Sinking and Sourcing.
Charging a Capacitor
10V
TCLOSE = 0
1
U1
R1
2
8V
V
1k
V
1
V
6V
U2
V1
TOPEN = 0
Voltage
C1
4V
2
10V
Capacitor
1uF
2V
0V
0
0s
1ms
V(U2:1)
V(R1:2)
2ms
3ms
4ms
5ms
6ms
7ms
8ms
9ms
10ms
V(V1:+)
Time
• Capacitor C1 is charged up by current flowing
through R1
V 1  VCAPACITOR 10  VCAPACITOR
I

R1
1k
• As the capacitor charges up, its voltage
increases and the current charging it decreases,
resulting in the charging rate shown
Charging a Capacitor
10mA
10V
8mA
8V
6mA
Capacitor
and
Resistor
6V
Current
Capacitor
4mA
4V
2mA
2V
0A
Voltage
0V
0s
1ms
I(R1)
2ms
3ms
4ms
5ms
6ms
7ms
8ms
9ms
10ms
I(C1)
0s
1ms
V(U2:1)
V(R1:2)
2ms
3ms
4ms
5ms
6ms
7ms
8ms
9ms
V(V1:+)
Time
Time
 t
• Capacitor Current
I  Ioe
• Capacitor Voltage
V  Vo 1  e
• Where the time constant
  RC  R1 C1  1ms
 t


10ms
Charging a Capacitor
10V
8V
6V
Capacitor
Voltage
4V
2V
0V
0s
1ms
V(U2:1)
V(R1:2)
2ms
3ms
4ms
5ms
V(V1:+)
Time
6ms
7ms
8ms
9ms
10ms
Charging a Capacitor
The time that it takes for the capacitor to charge to 63.7% of the applied
voltage is known as the time constant (t). It takes approximately 5 complete
time constants for the capacitor to charge to almost the applied voltage.
Astable Multivibrator
Initially when the output is high capacitor C starts charging
towards Vcc through RA and RB. However as soon as the voltage
across the capacitor equals 2/3 Vcc , comparator1 triggers the flipflop and the output switches to low state.
Now capacitor C discharges through RB and the transistor Q1.
When voltage across C equals 1/3 Vcc, comparator 2’s output
triggers the flip- flop and the output goes high. Then the cycle
repeats.
Working Principle
1. Threshold(6) and trigger comparator(2) inputs are joined together.
2. A capacitor is connected to ground from 2&6.
3. If the power is on, Pin2 will be < 1/3 Vcc. Pin3 is “1”. Discharging
transistor is off and the capacitor starts charging. When it is > 2/3
Vcc,
the FF is set, Pin3 is “0” Now the transistor is short and capacitor
starts discharging through RB. When it is < 1/3Vcc. Output is again
“1” and cycle repeats. Hence the charging and discharging is
between 2/3Vcc and 1/3Vcc .
Astable Multivibrator
Tc = 0.693(RA+RB)
Td + 0.693RBC
T + tc + td = 0.693(RA + 2RB)C
Minimum component Astable (50% Duty Cucle)
This is a cheap and cheerful astable using just one resistor and one
capacitor as the timing components: Minimum. However, if you build
this circuit, it is probable that the HIGH time will be longer than the
LOW time. (This happens because the maximum voltage reached by
the output pulses is less than the power supply voltage.) Things will
get worse if the output current increases. The charging and
discharging path is through Pin-3 of 555.
BISTABLE CIRCUIT.
• At the beginning of the cycle, C1 is charged through resistors
R1 and R2. The charging time constant is
• The voltage reaches (2/3)Vcc in a time  = (R1+R2)C1
•  = 0.69(R1+R2)C1
• The capacitor voltage cycles back and forth between (2/3)Vcc
and (1/3)Vcc at times, and
1 = 0.69(R1+R2)C1
2 = 0.69(R2)C1
• The frequency is then given by
1
144
.
f 

0.693( R1  2  R2)C1 ( R1  2  R2)C1
APPLICATIONS OF 555
1. Extended duty cycle astable
Duty Cycle = ton/(t1+t2).
2. Pulse width Modulation.
• One shot triggered by
trigger pulses at Pin-2.
• Modulating Sine wave is
given at Pin-5.
PWM output is at Pin-3. Used for DC motor speed control.
PWM Waveforms
Optical Transmitter Circuit
Astable is used to produce carrier pulses at a
frequency we cannot hear (well above 20kHz)
3. Pulse Position Modulation (PPM)
+ve Pulses
Suppresse
d
Differentiator
In pulse position modulation, the amplitude and width of the pulses
are kept constant, while the position of each pulse with reference to
the position of a reference pulse, is changed according to the
instantaneous sampled value of the modulating signal.
Pulse position modulated waveform
A 555 IC timer can be used to build a Pulse position modulator. This
pulse position modulator (PPM) is different from pulse width modulation
(PWM) which keep constant frequency.The PPM does not keep
constant frequency.
4. FSK Generator
Digital Modulation Only.
5. Linear Ramp Generator
When a capacitor is charged with a constant current source then
linear ramp is obtained. This concept is used in linear ramp
generator.
The circuit is used to obtain constant current Ic is a current mirror
circuit, using transistor Q and diode D. The current Ic, charges
capacitor C at a constant rate towards + Vco But when voltage at pin
6 i.e. capacitor voltage Vc becomes (2/3Vcc), the comparator makes
internal transistor Qi ON within no time. But while discharging when
Vc becomes (1/3 Vcc)/ the second comparator makes Qi OFF and C
starts its charging again. As discharging time of capacitor C is very
small, the time period of ramp is assumed practically same as that of
charging time of capacitor.
Fan/Motor Speed Control
By adding a comparator to the ramp generator we can create a very nice
variable duty-cycle pulse generator, much like we did in the previous
section. We will use this for a speed controller for our little DC brushless fan.
VARIABLE DUTY CYCLE
555 Timer as a Schmitt Trigger
When a Sine wave is
applied Tripping points
are 1/3Vcc &2/3Vcc.
R1=R2
The upper comparator will trip at 2/3
Vcc while lower comparator at 1/3 Vcc.
The frequency of square wave remains same as
that of input. The Schmitt trigger can operate
with the input frequencies up to 50 kHz.
555 Timer Applications
• 555 timer is used to produce an oscillating signal
whose voltage output is increased by the
transformer to a dangerous level, producing
sparks. DO NOT DO THIS WITHOUT
SUPERVISION
ADC & DAC
Most of the physical quantities such as
temperature, pressure, displacement, vibration etc exist
in analog form. But it is difficult to process, store or
transmit the analog signal because errors get
introduced easily. Hence to enable these signals to be
processed digitally, these are to be represented in
equivalent digital form. Hence the need for ADC.
Again, after processing is over, the digital
signals are to be converted into equivalent analog
signals for human observations or activation of further
circuits. For this, we need DAC.
D TO A CONVERTERS
Vo = output voltage
VFS = full scale output voltage
K - scaling factor usually adjusted to unity
d1d2... Dn = n-bit binary fractional word with the decimal point
located at the left
d1- most significant bit (MSB) with a weight of VFS/2
dn - least significant bit (LSB) with a weight of VFS/2n
Current to Voltage Converter
Binary Weighed Resistors
Figure 9-18 (a) D/A converter with binary-weighted
resistors, (b) Decimal equivalent of binary inputs
Gayakwad.
The current through RF depends on switch position
IF is 0.5,1, 1.5, 2, 2.5 mA etc. Vo=IFxRF. Since RF is
1K, the VO = 0.5,1,1.5V…etc.
The important points to note down are
When all the input bits are’0’,
What is the minimum output Vo.?
Resolution = ± ½ LSB.
When all the input bits are ‘1’
What is the output Vo.? Maximum VO.
What is the speed of conversion?
Specifications of DAC
• Resolution
For an n bit INPUT, the total number of steps is 2n-1,
Then % resolution
x100
is defined as the ratio of a change in output voltage
resulting from a change of 1 LSB at the digital
inputs.
VoFS = Full-scale output Voltage.
Example: For an 8bit DAC, if full scale output voltage
is 10.2V, what is the resolution?
R=
= 40mV/LSB. 1 LSB change results in 40mV output.
Accuracy
Accuracy = ½ LSB. In the above example it is
20mV.
Problem: If n=4; VoFS = 15V; R = 15/(24-1) =
1V/LSB. What is Vout for an input of
0110?
Vo = Resolution x D. D=Decimal Equivalent
D= (0110)2 = 6
Vo = (1V/LSB) x 6 = 6V.
DAC SPECIFICATIONS
• Resolution: (2n -1) Total No. of Steps.
% Resolution =
x 100
• Linearity. Relation between input & output.
• Accuracy: Expressed as fraction of LSB
• Settling time. Time required for the O/P of
DAC to settle to with in ½ LSB of the final
value for a given digital input.
• Speed of conversion. Conversion Time.
• Supply Rejection:
• The ability of DAC to maintain accuracy and
linearity when the supply voltage changes.
Types of DAC
1.Binary weighted DAC
2.R-2R ladder type DAC
BINARY WEIGHTED DAC
Single VR is used.
n binary weighed
currents, i1,i2,i3
etc.
-VR
Multiple values of resistors
2R, 4R, 8R etc are used
Binary weighed currents, I1,
I2, I3 are used.
IT = I1+I2+I3+
+In
The output voltage is the voltage across Rf and
it is given as
When RF = R, Vo is given as
LIMITATIONS OF
BINARY WEIGHTED RESISTORS
(1) As the resolution increases, the resistor
value increases.
(2) Difficult to fabricate on chip. For an 8 bit
DAC the largest resistor is 128 times the
smallest one.
(3) The accuracy is low, since depends on
resistor values.
If VR ia – ve, we get +ve stepped voltage as shown.
Ladder Type Voltage-Switched R-2R DAC
voltage scaling is used
-VR
Only TWO values of resistors
R
MSB
LSB
0
0
0
1
Fig.11.8 Four Bit R/2R Ladder D/A Converter Let b1b2b3b4 1000
Only TWO values of resistors are required. Identical resistors and
voltage scaling is used unlike binary weighed DAC binary weighed
currents are used.
R-2R LADDER TYPE D/A CONVERTER
0
0
2
║el
0
1
(R+R) ║ 2R
+
= VR/2
V0 = -VR/2
Equv. Of 3rd stage.
V0 = -VR/2
For b1,b2,b3,b4 = 1000, output Vo = VR/2
0100, VR/4, 0010, VR/8, 0001, VR/16
For n bit DAC
In the previous example when the binary no. is 1000,
V0 = -VR/2, if RF=R, & n=4
V0 = VR/2
Ladder Type Voltage-Switched R-2R DAC
voltage scaling is used
-VR
Only TWO values of resistors
-VR/2
R
MSB
LSB
0
0
0
1
Fig.11.8 Four Bit R/2R Ladder D/A Converter Let b1b2b3b4 1000
Vo = (-Rf/R) (-VR/2) If Rf = R, Vo = (VR/2)
VR/20
VR/21
VR/22
VR/2n
Inverted or Current Mode R-2R Ladder D/A Converter.
MSB & LSB are interchanged.
Since both the positions of switches are
at ground potential, the current flowing
through resistances is constant and it is
independent of switch position. These
currents can be given as
When Rf = R, Vo is given as
R-2R LADDER TYPE DAC
• Uses only two values of resistors
• Overcomes the limitations of Binary
weighted DAC
• OPAMP is connected in inverting mode
• Each digital input is applied through R-2R
network and Vref
Sources of Errors in DAC
• Linearity Error
• The error is defined as the amount by which the actual
output differs from the ideal straight-line output.
• Fig. 8.19 shows the linearity error in the transfer
characteristics of DAC. It is mainly due to the errors
in the current source resistor values.
Fig. 8.19 Linearity error in transfer
characteristics of DAC
Offset Error
Fig. 8.20 Offset error in transfer
characteristics of DAC
• The offset error is defined as the
nonzero level of the output voltage
when all inputs are zero.
• It adds a constant value to all output
values, as shown in Fig. 8.20.
• It is due to the presence of
offset voltage in op-amp and leakage
currents in the current switches.
Gain Error
It is defined as the difference between
the calculated gain of the current to
voltage converter and the actual gain
achieved. It is due to the errors in the
feedback resistor on the current to
voltage converter op-amp.
Fig. 8.21 Gain error in transfer characteristics of DAC.
Quantization Error
This is Caused in ADC.For a given binary
output, the exact analog input is uncertain.
This is because the binary output increases
linearly in steps.
IC 1408 D/A Converter
(DAC0800, DAC0808 are exact pin to pin equivalents.)
The 1408 is an 8 bit R/2R ladder type D/A converter
compatible with TTL and CMOS logic. It is designed to
use where the output current is linear product of an
eight bit digital word.
The IC 1408 consists of a reference current amplifier, an
R/2R ladder and eight high speed current switches. It
has eight input data lines A1 (MSB) through A8 (LSB).
It requires 2 mA reference current for full scale input
and two power supplies Vcc = + 5 V and VEE = - 15 V (VEE
can range from 5 V to - 15 V). The voltage Vref and
resistor R14 determines the total reference current
source and R15 is generally equal to R14 to match the
input impedance of the reference current amplifier.
Important Electrical Characteristics for IC 1408
Reference current : 2 mA
Supply voltage : + 5 Vcc and - 15 V VEE
Setting time : 300 ns
Full scale output current : 1.992 mA
Accuracy : 0.19 %
When input = 11111111, Io is given by
V0= 1.992mA x 5KΩ=9.961V
Unipolar
Note : The arrow on the pin 4 shows the
output current direction. It is inward.
This means that IC 1408 sinks current.
At (0000 0000) 2 binary input it sinks
zero current and at (11111111)2 binary
input it sinks 1.992 mA.
This circuit can be modified to give
bipolar output.
INPUT
OUTPUT
(0000 0000) 2
0
FFH (11111111)2,
= 1.992mA x
5KΩ=9.961V
Bipolar
Condition 1 : For binary input (00H)
When binary input is 00H, the output current Io at pin 4 is zero. Due to this
current flowing through RB (1 mA) flows through Rf giving Vo = - 5 V.
Condition 2 : For binary input 80H (10000000)
When binary input is 80H, the output current Io at pin 4 is 1 mA. By
applying KCL at node A we get,
-IB+I0 +If = 0. Substituting values of IB and Io we get,
-(1 mA) + (1 mA) + If = 0: If = 0 and therefore Vo = 0V.
Condition 3 : For binary input FFH (11111111)
When binary input is FFH, the output current I0 at pin 4 is 2 mA.
By applying KCL at node A we get,
-IB+Io+If = 0
substituting values of IB and Io we get,
- (1 mA) + (2 mA) + If = 0
If = - 1 mA
Therefore, Vo = + 5 V.
In this way, circuit shown in the Fig. 9.26 gives output in the bipolar
range.
Example: For above bopolar circuit, calculate
the output voltage, V0 for digital input word of
1. 00000000
2. 01111111
3. 10000000
4. 11111111
Current for 1 LSB is 8µA. IFS = 8µAx255=2.04mA.
For 00000000 input, I0 = 8µA x 0 = 0
I0’ =2.040mA-0=2.04mA.
V0= (0-2.04mA)(5KΩ) = -10.20V
ADC’s
• Converts analog signal into digital data
• Used in Data acquisition systems &
Digital instruments etc
TYPES OF ADC
1.
2.
3.
4.
Successive approximation ADC
Parallel converter or Flash type ADC
Ramp Converter.
Dual Slope Converter.
Fig. 8.26 Analog input Vs Digital output
Resolution
Fig. 8.26 shows eight (23) discrete output states from 000 to 111, each step
being 1/8 V
apart. Therefore, we can say that expression of ADC resolution is
resolution = 1/2n
(1) In the above case n=3
Resolution is also defined as the ratio of a change in value of input voltage,
X, needed to change the digital output by 1 LSB. If the full scale input voltage
required to cause a digital output of all l's is VIFS, then
Resolution = ViFS/2n
(2)
If viFs is the maximum input voltage, which will
cause all 1’s at the output.
ViFs = VFs -1LSB
Example:
For an input voltage of 0-10V, what is the
resolution?
1LSB = 10V/28= 39.1mV
What is the input voltage that generates all 1’s at
output?
10V-39.1mV = 9.961V.
What is the digital output for an input voltage of
4.8V?
D= 4.8/39.1 = 122.76 say 123.
The binary value is 01111011
Quantization Error
Fig. 8.26 shows that the binary output is 001 for all
values of Vi between 1/4 and ½ V. There is an
unavoidable uncertainty about the exact value of Vi
when the output is 001.
This uncertainty is specified as quantization error. Its
value is  ½ LSB. It is given as,
QE =
(3)
Increasing the number of bits results in a finer
resolution and a smaller quantization error.
Conversion Time
It is an important parameter for ADC. It is defined as
the total time required to convert an analog signal
into its digital output. It depends on the conversion
technique used and the propagation delay of circuit
components.
SUCCESSIVE APPROXIMATION ADC
• Widely used
• Similar to counter type ADC except that, a
SAR is used
• SAR acts as programmable Up/Down
counter
• Completion of conversion, triggered by a
change in the state of the comparator
• Much faster than the counter type
SUCCESSIVE APPROXIMATION ADC
Implements Binary search algorithm
• Initially, DAC input set to midscale (MSB
=1)
• VIN > VDAC , MSB remains 1. Next bit is set to
1
• VIN < VDAC , MSB set to 0. Next bit is set to 1
•MSB’s remain same after each conversion
and next 3 bits are processed. Then next 2
bits, first 2 remaining same etc.
• Algorithm is repeated until LSB.
DAC [input] = ADC [output]
N cycles required for N-bit Conversion.
4
3
Upper arrow 1
2
Lower arrow 0
Vin> 11
1
First Bit
Next bit is
always changed
to ‘1’
2nd Bit
3rd Bit
4th Bit
0
Vin<01
0
1.
2.
3.
4.
5.
6.
Start conversion pulse will set all zeros in SAR.
MSB is set to 1 and others remaining 0’s (1/2 the input voltage). DAC output is compared with unknown voltage. (1000)
If unknown voltage is higher, the bit under comparison is retained 1 and the next bit is made 1.
If unknown voltage is less, the bit under comparison is made 0 and the next bit is made 1.
MSB’s remain same after each conversion and next 3 bits are processed. Then next 2 bits, first 2 remaining same etc.
Then comparison moves to next bit and process continues till last bit.