Download A Low-Power Wideband Polar Transmitter for 3G

A Low-Power Wideband Polar Transmitter
for 3G
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ISSCC 2011 / SESSION 21 / CELLULAR / 21.8
21.8 A Low-Power Wideband Polar Transmitter for 3G Applications
A current-mode second-order passive lowpass filter suppresses spikes arising from the periodic
charge dispensing, and an offset current centers the closedloop VCO characteristic on zero.
Figure 21.8.2 shows the F/V converter circuit. There is no need in the differential circuit to
stabilize the quiescent point of the filter’s input against PVT variations, and the size of the
filter’s capacitance is also halved. The sampling capacitance is chosen as a compromise between
settling time and thermal noise. The output differential-to-single-ended stage boosts impedance
relative to the (programmable) load resistor. When embedded within the complete PLL, this FLL
group delay sets the differential delay between PM and AM paths until they unite at the PA
driver. By calibrating the F/V filter’s poles with a master-slave scheme, the FLL bandwidth is
held at 10MHz with better than 10% accuracy. The AM signal is time-retarded in digital
baseband by this delay. Quantities that cannot be simply calibrated leave a small residual delay
difference, but this is within the WCDMA 2ns delay margin. A polar modulator using this delay
compensation is built around the linearized VCO, as shown in Fig. 21.8.3. The PLL is a
fractional-N, type II loop. The digital AM and PM signals are generated in an FPGA and applied
to the transmitter using two sets of external DACs and reconstruction filters, which can be easily
fabricated on-chip with superior matching. The reference clock of the PLL is supplied from an
external generator, but in a complete transceiver implementation, it can be easily generated in the
receiver PLL. Among the many candidates for a PA driver, we find the commutating differential
driver amplifier to be convenient, simple and acceptably efficient. Its drain supply needs not be
regulated. Gain is controlled with switchable unit cells in the PA driver and a two-step
attenuation in the output transformer. The gain control range is 60dB and can be increased by
adding more unit cells or using other techniques such as cascode current steering. The
measurement results of the FLL are shown in Fig. 21.8.4. The FLL suppresses deviations in the
VCO characteristic from a straight line by 13× (measured as percentage deviation from a best-fit)
across a sweep of ± 200mV in tuning voltage around mid-rail, and kVCO—FB remains within
1% of the designed value of 80MHz/V across temperature and supply voltage. These numbers
are limited by spectrum analyzer accuracy. Spurs arising from sampling appear at 500MHz offset
at a level of –85 dBc, well below the 3GPP specification of spurs less than –69dBc. The
transmitter’s WCDMA constellation and spectrum are shown in Fig. 21.8.5, and compared in
Fig. 21.8.6 with recently published linear transmitters. In WCDMA mode, the ACLR at
5/10MHz offsets is –42/–58dBc, noise at 45MHz offset is –159dBc/Hz, and EVM at 0dBm
output power is 2.9%. The transmitter, including the VCO, LO chain, PLL, FLL, and PA driver,
draws 40mA from the battery, of which the FLL takes only 1.5mA. The DG09 current is 25mA.
The low power consumption stands out as the key advantage of the polar architecture: it arises
from a simple, single-phase LO chain, a PA driver that always operates close to saturation, and
far-away phase noise filtering by the loop rolloff. At 1dBm output power, the transmitter’s
EDGE modulation spectrum is down by –61dBc at 400kHz and the EVM is 2.4% at 32mA of
battery current. Where direct upconversion transmitters would require extensive calibration, the
measured asis LO leakage of this device is –55dBc and scales favorably with gain control. Figure
21.8.7 shows the die micrograph of the transmitter, which occupies 0.7mm2 in 65nm CMOS.
The low power consumption and chip area present a strong case in favor of the well-designed
polar transmitter.
Michael Youssef1,2, Alireza Zolfaghari1, Hooman Darabi1, Asad Abidi2
1
Broadcom, Irvine, CA, 2University of California, Los Angeles, CA
So far all mainstream transmitters for WCDMA are of the direct upconversion type. This
architecture is versatile but requires calibration of the imbalance in its quadrature branches and
DC offset at its inputs, and it is vulnerable to mixer noise. We believe it consumes more power
and chip area than is warranted, and propose the polar transmitter as an alternative. Although it
has been widely discussed as the ideal transmitter for EDGE, the polar architecture has yet to
make significant inroads there, let alone into wideband CDMA. We will describe new circuits
that enable a compact, largely self-calibrated polar transmitter, whose lower power and chip area
put it ahead of state-of-the-art direct upconversion transmitters [1-3]. Polar’s challenges lie in
finding a reliable method of wideband phase modulation (PM), and in suppressing unequal delay
in the two separate paths that the PM and AM waveforms will take before they unite in the prePA driver. Whereas EDGE requires a PM bandwidth of about 800kHz and can tolerate AM/PM
delay mismatch on the order of tens of nanoseconds, WCDMA needs at least an 8MHz
bandwidth with path delay mismatch less than 2ns. The solution we describe takes care of
bandwidth and unequal delay with minimum intervention. PM is transferred via a fractional-N
phase-locked loop (PLL) on to a voltage-controlled oscillator (VCO). The PLL bandwidth is
usually a small fraction of the reference frequency, otherwise spurs and fractional noise will leak
into the output: in our circuit it is between 200 and 300kHz. Then to impose an 8MHz-wide
modulation into this 300kHz-wide loop, one must resort to either pre-emphasis or two-point
injection. Pre-emphasis is sensitive to variations in loop gain, and at large modulation
bandwidths can push PLL components to the limits of their dynamic range. On the other hand
two-point injection is very sensitive to the VCO gain (kVCO), which changes across process,
supply voltage, temperature, and operating frequency. Since in either method the oscillator is
being modulated at rates well beyond the PLL bandwidth, feedback is unable to correct for VCO
nonlinearity, and distortion will appear at high modulation frequencies. But if a linear VCO with
known and reproducible kVCO were made available, twopoint injection becomes feasible. Then
by adding to it a fairly simple AM path and a power-efficient PA driver, a wideband polar
modulator may be realized. What differential delay remains between the two paths must also be
predictable, and more importantly, should be self-calibrated. All-digital PLL-based transmitters
for GSM/EDGE are based on this method [4], but they are sensitive to the oscillator gain and
their output is usually cluttered by spurious tones. Also, extensive calibration and signal
processing make them power-hungry; it is not clear whether they can reach WCDMA
bandwidths. We show that our approach which strikes a balance between analog and digital
calibration is simpler, more robust, and consumes less power. First we consider VCO
linearization. A model-based pre-distortion [5] does not assure the well-controlled, stable, and
linear VCO characteristic that we have shown at low frequencies with frequency-to-voltage
(F/V) feedback [6]. With modern CMOS it becomes possible to extend this method to RF. Thus,
as shown in Fig. 21.8.1, the VCO is surrounded by a local feedback loop, which we refer to as a
frequency-locked loop (FLL). This measures the oscillation frequency continuously via a
switched capacitor (CS) that dispenses packets of charge from a bandgap voltage reference
(VREF) into a reference resistor RL, and compares the resulting voltage with an applied voltage
representing the desired PM. With frequency feedback the VCO gain (kVCO—FB) is
kVCO—FB =
M ( GVREF Cs RL )
When the time constant Cs RL is stabilized against changes in process, voltage, temperature and
frequency, kVCO—FB is also predictably constant. A number of methods have been developed
for use for active filters that stabilize RC time constants against a crystal reference. They
typically obtain accuracies better than 1%, limited by the discreteness of unit C and R. We
employ this form of masterslave tuning.
References: [1] M. Cassia, A. Hadjichristos, et al., “A Low-Power CMOS SAW-Less Quad
Band WCDMA/HSPA/HSPA+/1X/EGPRS Transmitter,” IEEE J. Solid-State Circuits, July
2009. [2] T. Sowlati, B. Agarwal, et al., “Single-Chip Multi-band
WCDMA/HSDPA/HSUPA/EGPRS Transceiver with Diversity Receiver and 3G DigRF
Interface without SAW filters in Transmitter / 3G Receiver,” ISSCC Dig. Tech. Papers, Feb.
2009. [3] C. Jones, B. Tenbroek, et al., “Direct-Conversion WCDMA Transmitter With
163dBc/Hz Noise at 190MHz Offset,” ISSCC Dig. Tech. Papers, Feb. 2007. [4] J. Mehta, R.
Staszewski, et al., “A 0.8mm2 All-Digital SAW-Less Polar Transmitter in 65nm EDGE SoC,”
ISSCC Dig. Tech. Papers, Feb. 2010. [5] J. Oehm and D. Pham-Stabner, “Linear Controlled
Temperature Independent Varactor Circuitry,” Proc. ESSIRC, Sept. 2002. [6] A. Abidi,
“Linearization of Voltage-Controlled Oscillators Using SwitchedCapacitor Feedback,” IEEE J.
Solid-State Circuits, June 1987.
378
? 2011 IEEE International Solid-State Circuits Conference
978-1-61284-302-5/11/$26.00 ?2011 IEEE
ISSCC 2011 / February 23, 2011 / 11:45 AM
VTUNE VFB
CINT
VCO
Δf M = OUT = ΔVTUNE GVREF CS R L
CLK
fOUT
CLK CLK
1.2V 1.2V
ATOP
K VCO - FB
÷M
CLK
gm 2VREF CS/2 gm
R1 R2 C1 R1 R2 C2
Gxgm
ABOTTOM
RL VCM
IOffset
2 Real RC Poles
G × gm
IOffset
RL
gm
FLL Loop Filter
CS
VREF
CLK CLK 1.2V
Frequency-to-Voltage Converter (F/V)
Figure 21.8.1: Linearizing the VCO by means of a negative feedback loop.
Figure 21.8.2: Frequency-to-Voltage converter circuit.
240 -20°C, VDD
Matched DACs/LPFs Delay Eq DAC AM Path
rd
Off-chip Components in Gray
220 200 180
25°C, VDD 85°C, VDD 25°C, VDD-10% 25°C, VDD+10%
1/kVCO
10-b 3 Order 125MS/s 20MHz
KVCO (MHz/V)
DAC
PM HF Path
160 140 120 100 80 60
Open-Loop
IQ
I/Q to Polar
AM PM
d dt
REF
125MHz
PFD
CP PLL
+
+
_
÷2 FLL
F/V Converter
÷2
Out PA Driver
÷4
PM LF Path
1/fREF Channel Select
MMD
ΣΔ Modulator
Closed-Loop
0.5 0.6 0.7 0.8 0.9 1.0
40 0.4
VTUNE (Volt)
Figure 21.8.3: System block diagram.
Figure 21.8.4: Measured open- and closed-loop KVCO across temperature and supply corners.
Parameter 5-MHz ACLR (dBc) 10-MHz ACLR (dBc) RMS EVM (%) Noise @ 45MHz
(dBc/Hz) DG09 Current (mA)b Current @ 0-dBm (mA)b Area (mm ) Process
abcde
[1] –41
a
[2] –45 –70 2.1 –160 N/A 67c 6.0d 130nm
[3] –46 –70 3.7 N/A N/A 65 5.6e 180nm
This Work –42 –58 2.9 –159 25 40 0.7 65nm
3GPP Speci?ca?ons –33 –43 17.5 -----N/A 5.9a N/A N/A 48 8.1 180nm
21
2
At 23-dBm output power Battery-referred current Estimated as half the reported full duplex
current (135 mA) Estimated from the die micrograph Estimated from Fig. 10.2.7, ISSCC Dig. of
Tech. Papers, 2008
Figure 21.8.5: Measured WCDMA performance in GSM band.
Figure 21.8.6: WCDMA mode performance summary.
DIGEST OF TECHNICAL PAPERS ?
379
ISSCC 2011 PAPER CONTINUATIONS
Figure 21.8.7: Transmitter die micrograph.
? 2011 IEEE International Solid-State Circuits Conference
978-1-61284-302-5/11/$26.00 ?2011 IEEE