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Digital Design:
Principles and Practices
Chapter 3
Digital Circuits
3.1 Logic Signals and Gates
Digital Circuits
• We live in an analog world, not a digital one.
• Values of voltage, current, temperature, time and
speed are all continuous (analog).
• Digital circuits:
 are easier to design (than analog circuits)
 provide higher noise immunity (than analog circuits)
• Digital logic
 Two possible numbers (or logic values): 0 and 1
 A logic value (0 or 1) is often called a binary digit or bit.
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Physical States Representing Bits in Different Technologies
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Logic Signals
• When discussing electronic logic circuits (such as CMOS and
TTL), digital designers often use the words “LOW” and “HIGH”
in place of “0” and “1”.
• LOW: A signal in the range of algebraically lower voltages,
which is interpreted as a logic 0.
• HIGH: A signal in the range of algebraically higher voltages,
which is interpreted as a logic 1.
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Representation of a Logic Circuit
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Logic Circuits
• Combinational circuit: A logic circuit whose outputs depend
only on its current inputs.
 Truth table
• Sequential circuit: A circuit with memory, whose outputs
depend on the current input and the sequence of past inputs.
 State table
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Truth Table
• Table 3-2 is the truth table for a
logic circuit with three inputs X, Y
and Z and a single output F.
• This truth table lists all eight
possible combinations of values of
X, Y, and Z and the circuit’s output
value F for each combination.
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AND gate, OR gate, NOT gate
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AND gate, OR gate, NOT gate
• AND gate: produces a 1 output if and only if all of its inputs
are 1.
• OR gate: produces a 1 if and only if one or more of its inputs
are 1.
• NOT gate (inverter): produces an output value that is the
opposite of its input value.
• The symbols and truth tables for AND and OR may be
extended to gates with any number of inputs.
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NAND gate, NOR gate
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NAND gate, NOR gate
• NAND gate: produces the opposite of an AND gate’s output, a
0 if and only if all of its inputs are 1.
• NOR gate: produces the opposite of an OR gate’s output, a 0 if
and only if one or more of its inputs are 1.
• The symbols and truth tables for NAND and NOR may be
extended to gates with any number of inputs.
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Logic Circuit
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Timing Diagram
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3.2 Logic Families
Logic Families
• A logic family is a collection of different integrated-circuit
chips that have similar input, output, and internal circuit
characteristics, but that perform different logic functions.
• Chips from the same family can be interconnected to perform
any desired logic function.
• Chips from different families may not be compatible; they
may use different power-supply voltages or may use different
input and output conditions to represent logic values.
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Logic Families
• Transistor-Transistor Logic (TTL)
 Bipolar Junction Transistor (BJT)
• Metal-Oxide Semiconductor Field-Effect Transistor
(MOSFET)
 Complementary MOS (CMOS)
• NMOS and PMOS
• CMOS circuits now account for the vast majority of the
worldwide integrated-circuit market.
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3.3 CMOS Logic
CMOS Logic Levels
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MOS Transistors
• A MOS transistor can be modeled as a 3terminal device that acts like a voltagecontrolled resistance.
• As suggested by Figure 3-7, an input
voltage applied to one terminal controls
the resistance between the remaining
two terminals.
• In digital logic application, a MOS
transistor is operated so its resistance is
always either very high (and the
transistor is “off”) or very low (and the
transistor is “on”).
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MOS Transistors
• Two type of MOS Transistors:
 n-channel MOS (NMOS)
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3 terminals: gate, source, and drain
The drain is normally at a higher voltage than the source.
Vgs is normally zero or positive
Vgs = 0  Rds is very high ( > 1MΩ)
Increase Vgs  Rds decreases
 p-channel MOS (PMOS)
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•
•
•
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3 terminals: gate, source, and drain
The source is normally at a higher voltage than the drain.
Vgs is normally zero or negative
Vgs = 0  Rds is very high ( > 1MΩ)
Decrease Vgs  Rds decreases
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NMOS Transistor
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PMOS Transistor
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nMOS & pMOS Symbols
nMOS Symbols
pMOS Symbols
nMOS Transistor
D
Layout
G
S
nMOS Symbols
MOS Transistors
• The gate of a MOS transistor has very high impedance
(resistance).
• Almost no current flows from the gate to source, or from the
gate to drain.
• Leakage current
• Gate capacitance
• NMOS and PMOS transistors are used together in a
complementary way to form CMOS logic.
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Basic CMOS Inverter Circuit
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Basic CMOS Inverter Circuit
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Basic CMOS Inverter Circuit
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NOR Gate
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NAND vs. NOR -- Performance
• CMOS NAND and NOR gates do not have identical electrical
performance.
• For a given silicon area, an n-channel transistor has lower “on”
resistance than a p-channel transistor.
• Therefore, when transistors are put in series, k n-channel
transistors have lower “on” resistance than do k p-channel
ones.
• As a result, a k-input NAND gate is generally faster than and
preferred over a k-input NOR gate.
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3-Input NAND Gate
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Fan-In
• The number of inputs that a gate can have in a particular logic
family is called the logic family’s fan-in.
• In principle, you could design a CMOS NAND or NOR gate with
a very large number of inputs. In practice, however, the
additive “on” resistance of series transistors limits the fan-in
of CMOS gates, typically to 4 for NOR gates and 6 for NAND
gates.
• Gates with a large number of inputs can be made faster and
smaller by cascading gates with fewer inputs. (See Figure 317)
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8-Input NAND Gate
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CMOS Non-inverting Buffer
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AND Gate
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AND-OR-INVERT (AOI) Gate
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AND-OR-INVERT (AOI) Gate
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OR-AND-INVERT (OAI) Gate
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OR-AND-INVERT (OAI) Gate
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AOI and OAI
• The speed and other electrical characteristics of a CMOS AOI
or OAI gate are quite comparable to those of a single CMOS
NAND or NOR gate.
• As a result, these gates (AOI and OAI) are very appealing
because they can perform two levels of logic with just one
level of delay.
• CMOS VLSI devices often use these gates internally, since
many HDL synthesis tools can automatically convert AND/OR
logic into AOI gates when appropriate.
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3.4 Electrical Behavior of
CMOS Circuits
Electrical Behavior of CMOS Circuits
• Static behaviors
 a circuit’s input and output signals are not changing
• Dynamic behaviors
 a circuit’s input and output signals are changing
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Electrical Behavior of CMOS Circuits
- Topics
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Logic voltage levels
DC noise margins
Fanout
Speed
Power consumption
Noise
Electrostatic discharge
Open-drain outputs
Three-state outputs
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7400-series Pin Diagrams
Fig. 1-2. Pin diagrams for a few 7400-series SSI integrated circuits
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74HC vs. 54HC
• The 74HC00 is the commercial part.
• The 54HC00 is the military version.
• HC: High-speed CMOS
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3.5 CMOS Static Electrical
Behavior
CMOS Static Behavior
• Static behavior = DC behavior = Steady-State behavior
• Example: CMOS Inverter
 Figure 3-10(b) only considers “0” and “1” (or “LOW” and “HIGH”)
 Figure 3-25 depicts the inverter’s electrical behavior
• LOW: VIN < 2.4V (OK?)
• HIGH: VIN > 2.6V (OK?)
• The transition in the middle of the curve may become more or less
steep, and it may shift to the left or the right.
 Specifications (or “specs”) for LOW and HIGH voltages are usually more
conservative. (See Figure 3-26)
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Basic CMOS Inverter Circuit
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Input-Output Transfer Characteristic of
a CMOS Inverter
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Logic Levels & Noise Margins
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Noise Margins
• How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
NMH
VIH
VIL
NML
Logical Low
Output Range
Logical High
Input Range
VOH
VOL
GND
Indeterminate
Region
Logical Low
Input Range
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Logic Levels & Noise Margins
• VOHmin: The minimum output voltage produced in the HIGH
state.
• VIHmin: The minimum input voltage guaranteed to be
recognized as a HIGH.
• VILmax: The maximum input voltage guaranteed to be
recognized as a LOW.
• VOLmax: The maximum output voltage produced in the LOW
state.
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Logic Levels & Noise Margins
Table 3-3
• The input voltages are determined mainly by switching
thresholds of the two transistors, while the output voltages
are determined mainly by the “on” resistance of the
transistors.
• Two values for VOHmin and VOLmax
 Depending on whether the output current (IOH or IOL) is large or
small
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Typical CMOS Levels
• VOHmin: VCC – 0.1 V
• VIHmin: 70% of VCC
• VILmax: 30% of VCC
• VOLmax: ground + 0.1V
• In Table 3-3, VOHmin = 4.4 V
 Worst case VCC = 5.0 – 10% = 4.5 V
 4.5 V – 0.1 V = 4.4 V
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DC Noise Margin
• Table 3-3




VOHmin : 4.4 V
VIHmin : 3.15 V
VILmax : 1.35 V
VOLmax : 0.1 V
• The LOW-state DC noise margin = VIL – VOL = 1.25 V
• The HIGH-state DC noise margin = VOH – VIH = 1.25 V
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Current
• IIH: The maximum current that flows into the input in the
HIGH state.
• IIL: The maximum current that flows into the input in the
LOW state.
• The input current shown in Table 3-3 for the ’HC00 is only ±1 μA.
Thus, it takes very little power to maintain a CMOS input in one
state or the other. This is in sharp contrast to older bipolar logic
circuits like TTL and ECL, whose inputs may consume significant
current (and power) in one or both states.
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VDD, VCC, VSS
• VDD = VCC
 Power (Logic ‘1’ or HIGH)
 CMOS: the drain terminal of NMOS (inverter)
 TTL: the collector terminal of BJT
• VSS
 Ground (Logic ‘0’ or LOW)
 CMOS: the source terminal of NMOS
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A CMOS Inverter with a Resistive Load
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A CMOS Inverter with a Resistive Load
(Input = HIGH)
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A CMOS Inverter with a Resistive Load
(Input = LOW)
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IOLmax & IOHmax
• IOLmax : The maximum current that the output can sink in the
LOW state while still maintaining an output voltage no greater
than VOLmax.
• IOHmax : The maximum current that the output can source in
the HIGH state while still maintaining an output voltage no
less than VOHmin.
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IOLmax & IOHmax
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Output Loading Specs
• Most CMOS devices have two sets of loading specifications:
 CMOS loads : consume very little current
 TTL loads : consume significant current
• Table 3-4 summarizes Table 3-3 for output loading specs.
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Output Loading Specs
• By convention, the current flow measured at a device
terminal is positive if positive current flows into the device; in
the HIGH state, current flows out of the output terminal.
• As Table 3-4 shows, with CMOS loads, the CMOS gate’s output
voltage is maintained within 0.1 V of the power-supply rail.
• As Table 3-4 shows, with TTL loads, the output voltage may
degrade quite a bit.
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Estimation of Rp(on) and Rn(on)
• The actual “on” resistances of CMOS output transistors are
usually not published. However, we can estimate those “on”
resistances using the following equations:
Rp(on)
VDD  VOHminT

I OHmaxT
Rn(on)
VOLmaxT

I OLmaxT
• The CMOS transistors in Table 3-4, Rp(on) = 165 Ω and Rn(on) =
82.5 Ω. Note that VDD = 4.5 V for this calculation.
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Estimation of Sink & Source Current
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Circuit Behavior with Non-ideal Inputs
• So far, we have assumed that the HIGH and LOW inputs to a
CMOS circuit are ideal voltages, very close to the power supply
rails.
• However, the behavior of a real CMOS inverter circuit depends
on the input voltage as well as on the characteristics of the load.
• If the input voltage is not close to the power-supply rail, then
the “on” transistor may not be fully “on” and its resistance may
increase.
• Likewise, the “off” transistor may not be fully “off” and its
resistance may be quite a bit less than one megohm.
• These two effects combine to move the output voltage away
from the power-supply rail.
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CMOS Inverter with Non-ideal Input Voltages
• Iwasted = 1.72 mA
• Pwasted = 8.62 mW
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CMOS Inverter with Load and Non-ideal
Input Voltage
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CMOS Inverter with Load and Non-ideal
Input Voltage
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Fanout
• The fanout of a logic gate is the number of inputs that the
gate can drive without exceeding its worst-case loading
specifications.
• The fanout depends not only on the characteristics of the
output, but also on the inputs that it is driving.
• Fanout must be examined for both possible output states,
HIGH and LOW.
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Fanout
• In Table 3-4,
 LOW-state fanout = 20
• IOLmaxC = 20 μA (for an HC-series CMOS gate driving CMOS inputs)
• IImax = ±1 μA
 HIGH-state fanout = 20
• IOHmaxC = –20 μA (for an HC-series CMOS gate driving CMOS inputs)
• IImax = ±1 μA
• Note that the HIGH-state and LOW-state fanouts of a gate are not
necessarily equal.
• In general, the overall fanout of a gate is the minimum of its HIGHstate and LOW-state fanout (20 in the foregoing example).
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Effects of Loading
• Loading an output beyond its rated fanout has several effects:
1) In the LOW state, the output voltage may increase beyond
VOLmax.
2) In the HIGH state, the output voltage may fall below VOHmin.
3) Propagation delay to the output may increase beyond
specifications.
4) Output rise and fall times may increase beyond their
specifications.
5) The operating temperature of the device may increase,
thereby reducing the reliability of the device and eventually
causing device failure.
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Unused Inputs
• Sometimes not all of the inputs of a logic gate are used.
• Unused CMOS inputs should never be left unconnected (or
floating).
• In high-speed circuit design, (b) or (c) are preferred over (a).
• It is possible to tie unused inputs directly to power rails.
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How to Destroy a CMOS Device
• You can destroy a CMOS device by simply walking across a
carpet and then touch an input pin with your finger. (1000+
V)
• CMOS devices are subject to damage from electrostatic
discharge (ESD).
• In the case of a CMOS input, the dielectric is the insulation
between an input transistor’s gate and its source and drain.
ESD may damage this insulation, causing a short circuit
between the device’s input and its output.
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nMOS & pMOS Symbols
nMOS Symbols
pMOS Symbols
nMOS Transistor
D
Layout
G
S
nMOS Symbols
3.6 CMOS Dynamic Electrical
Behavior