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ELEC 5808 Assignment 3
In order to calculate approximate values for this assignment, several parameters were measured using
simulations of the transistors. The results of the simulation are as follows.
Figure 1 shows the drain current of the transistor with Vds varied from 0 to 1.8 V. The gate-source voltages used
are 0.5, 0.7, 0.9, 1.1, 1.4, and 1.8 V. The source-bulk voltage was kept at 0 V. The length used was 0.18 um and
the width was 0.5 um.
From these graphs, several parameters were approximated. The μn*Cox constant was estimated to be about
2.5e-4 A/V^2, and the parameter length modulation parameter λ was estimated to be 0.3.
Figure 1 Drain current of NMOS transistor with varied drain-source and gate-source voltages.
A similar plot with the gate-source voltage being swept with varied drain-source voltages can be seen in Figure 2. The
drain-source voltages used are 0.1, 0.3, 0.5, 0.7 and 0.9 V. In order to measure the threshold voltage, the same graph
was plotted using a logarithmic y-axis, which can be seen. The linear part of the graph up to about 0.5 V indicates that
the transistor is in sub-threshold mode of operation up to that point, giving VT=0.5 V.
Figure 2 Drain current of NMOS transistor with varied gate-source and drain-source voltages
Figure 3 Logarithmic plot of drain current with swept gate-source voltages.
A similar set of simulations was done using a PMOS transistor with the same dimensions. These graphs can be seen in
Figures 4,5 and 6. The threshold voltage was estimated to be about 0.5 V, while the μp*Cox parameter was estimated to
be 6e-5 A/V2 and the λ parameter was estimated to be 0.3.
Figure 4 Drain current of PMOS transistor with source-drain voltage swept
Figure 5 Drain current of PMOS transistor with source-gate voltage swept
Figure 6: Logarithmic plot of drain current of PMOS transistor with the source-gate voltage swept
Question 1
Figure 1 shows the schematic for the designed current mirror. From the graph in Figure 1, it can be seen that the gatesource voltage for a constant drain current of 10 uA is about 0.65 V. Thus, Vgs-VT = 0.15 V. The output transistor shares
the same gate voltage, so that in order to remain in saturation, the drain-source voltage must be greater than Vgs-VT.
Since the source is at -0.9 V, the drain must be greater than -0.9+0.15=0.75 V.
The output impedance of the current source can be calculated to be 1/(λ *Id) = 1/0.15*10e-6 uA = 330 kOhm.
Error! Reference source not found. shows the schematic used to test the current mirror. A bias current is fed into the
mirror, and the output voltage is varied from -0.9 to 0.9 V. In an idea current mirror, the output current from the output
voltage source should always be the same as the input source, regardless of output voltage. The plot of the output
current against voltage can be seen in Figure 8. As can be seen, the approximate minimum output voltage before the
output transistor enters the triode region is -0.75 V, while the output impedance was calculated to be (0.7857 V- -0.4821
V)/(13.5 uA – 9.188 uA) = 290 kOhm. These values roughly correspond to the calculated values.
Figure 7 Schematic of the first current mirror
Figure 8 Schematic of circuit used to test first current mirror
Figure 9 Plot of output current vs output voltage of the current mirror
Question 2
Figure 10 shows the schematic of the 3 current mirrors designed to source the other current values. The mirror was
constructed by using additional transistors sharing the same gate, only with differing widths. The output over a range of
voltage values can be seen in Figure 11. As can be seen, the minimum voltage across each transistor has not changed
from the 10 uA case (-0.75 V), since the transistors all share the same gate voltage.
Figure 10 Schematic of the second set of current mirrors
Figure 11: Output current vs. output voltage for the various current mirrors
Question 3
Figure 12 shows the schematic for the 10 uA cascade current mirror. In order to calculate its output impedance and
minimum output voltage, the parameters estimated from simulated transistors were used. At 10 uA, the gm was
calculated to be
gm 
2I D
Vgs  VT 
2  10uA
0.65  0.5
gm  0.133mA / V
gm 
Thus, the output impedance was calculated to be
Rout  rds2 gm
Rout  330k 2  0.133mA / V
Rout  14.5M
To estimate the minimum voltage, it is recalled that Vgs for 10 uA is about 0.65 V. Thus, the gate of the top pair of
transistors must be 1.3 V about VSS, since the source of the top left transistor is at 0.65 V above VSS. The top right
transistor’s source must also be around 0.65 V to maintain the same Vgs voltage. Thus, the output drain can be no more
than Vt volts below the gate, and so must be 1.3 V-0.5 V=0.8 V above VSS. With VSS of -0.9 V, this works out to about
- 0.25 V.
The output results can be seen Figure 13. The minimum output voltage the mirror can accept while still maintaining the
same output current is -0.25 V, which compares to the value calculated previously (many of the parameters such as Vgs
and Vt were based on estimates whose accuracy is not exact, leading to some calculation errors). Below this voltage, 1
and then both of the transistors enters the triode region. The output impedance can be calculated the values obtained
using the markers to measure the slope of the constant current region: (0.7995V- -.07459V) / (10.03uA/9.921uA)=
8.0MOhm, which is similar to the calculated value. Parameter value errors can account for the discrepancy.
Figure 12 Schematic of the cascode current mirror
Figure 13: Output response of the cascode current mirror
Question 3
In order to perform the necessary calculations needed to obtain the approximate transistor sizes, several parameters
were estimated. First of all, an approximate value of gm value was used, based on the fact that the bias current of each
transistor is only 5 uA (since both transistors are sharing the 10 uA bias current). The sizes were kept at W=500 um and
L=180 um.
Using this value, gmn can be calculated to be sqrt(2*μn*Cox*W/L*Id) = sqrt(2*2.5e-4A/V2*500um/180um*5uA)=8.3e-5
A/V. Similarly, gmp can be calculated to be sqrt(2*μp*Cox*W/L*Id) = sqrt(2*6e-5A/V2*500um/180um*10uA)=4.1e-5 A/V.
Rds for the PMOS and the NMOS transistors (since they share the same λ) can be calculated to be 1/(λId)=1/(0.3*5uA)=
670 kOhm.
For a differential amplifier, the gain can be calculated as Av=gmnRout||Rds=0.5*gmn*Rds=28 V/V. The max slew rate is
calculated from the max output current (10 uA) and the output capacitance (100 fF). Since I = C dV/dt, dy/dt = I/C=
10 uA/100 fF = 100 V/us. The maximum frequency can be calculated to be XXX.
These values at first appear to meet the specifications. However, when the circuit was constructed and simulated, the
gain was slightly below the required 20 V/V. The transistors were all resized and the new design was simulated. The
calculations are likely in error due to the simplified model used for the equations and due to the fact that many of the
parameters are only estimates. This is also why the new values were not used in calculations to verify the results.
Figure 14 shows the schematic of the amplifier, while Figure 15 shows the schematic of the testing schematic used for
simulating the frequency response of the amplifier. The results of this simulation can be seen in Figure 16. As can be
seen, the low frequency gain is about 27 dB, and so is 22.4 V/V. The 3 dB bandwidth can be seen to be about 5 MHz.
A similar circuit was used to measure the slew rate, only with the sinusoidal input replaced with a square wave
generator. The results can be seen in Figure 17. By looking at the results of the delta cursors, it can be seen that the
slew rate is 100 uV/s, which is above the required value. A similar value of -80 uV/s was recorded for the falling rate.
Figure 14 Schematic of the first amplifier
Figure 15 Schematic of the test circuit used for the frequency response of the first amplifier
Figure 16 Frequency and Phase response of the amplifier
Figure 17 Response of the amplifier to a sharp pulse showing the slew rate
Figure XXX shows the layout of the amplifier. The results of the simulation are seen in Figure XXX for the frequency
response and Figure XXX for the slew rate. The measured values are 27 dB for the gain, 5 MHz for the bandwidth, 100
uV/s for the slew rate (rising), and -80 uV/s for the slew rate (falling). These values are all identical to those done with
the simulations.
Figure 18 Frequency response of the extracted view of the first amplifier
Figure 19 Slew rate plot of the extracted amplifier
Question 5
The calculations to design the amplifier are as follows:
In order to reuse some of the values previously calculated, a bias current of 10 uA for both sides of the differential
amplifier is used. Also, the sizes of the transistor have been kept at W=500 um and L = 180 um. The output impedance
of the PMOS cascade stage is then Rout=gm*rds2=4.1e-5A/V * (670kOhm)2= 18 MOhm. To estimate the approximate gain
of the CS-CG stage, it is assumed that the CG stage acts as an ideal current buffer, and that the CS amplifier acts as a
transconductance amplifier with a transconductance of gmn. The NMOS stages are assumed not to have any output
impedance since an ideal current source is being used for biasing.
The gain is then Av=gmn*Rout = 8.3e-5*18MOhm=1500 V/V, which is above the minimum value.
The schematic of the amplifier can be seen in Figure 20 and the test schematic can be seen in Figure 21. The frequency
response can be seen in Figure 22. Although the input frequency does not do all the way down to 0 Hz, it goes low
enough to demonstrate constant low frequency gain of 55.14 dB (571 V/V), which is greater than the required 600.
Figure 20 Schematic of the second inverter
Figure 21 Schematic of the test circuit used on the second amplifier
Figure 22 Frequency response of the second amplifier