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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006
A Digitally Controlled Oscillator System for
SAW-Less Transmitters in Cellular Handsets
Chih-Ming Hung, Member, IEEE, Robert Bogdan Staszewski, Senior Member, IEEE, Nathen Barton,
Meng-Chang Lee, Member, IEEE, and Dirk Leipold
Abstract—A complete digitally controlled oscillator (DCO)
system for mobile phones is presented with a comprehensive
study. The DCO is part of a single-chip fully compliant quad-band
GSM transceiver realized in a 90-nm digital CMOS process. By
operating the DCO at a 4 GSM low-band frequency followed by
and
frequency dividers, the requirement of on-chip inductor
the amount of gate oxide stress are relaxed. It was found that a
dynamic divider is needed for stringent TX output phase noise
while a source-coupled-logic divider can be used for RX to save
power. Both dividers are capable of producing a tight relation
between four quadrature output phases at low voltage and low
power. Frequency tuning is achieved through digital control of the
varactors which serve as an RF DAC. Combining a MIM capacitor
array and two nMOS transistor arrays of the varactors for the
RF DAC, a highly linear oscillator gain which is also insensitive
to process shift is achieved. The finest varactor step size is 12 kHz
at the 1.6–2.0 GHz output. With a sigma-delta dithering, high
frequency resolution is obtained while having negligible phase
noise degradation. The measured phase noise of 167 dBc/Hz at
20 MHz offset from 915 MHz carrier and frequency tuning range
of 24.5% proves that this DCO system can be used in SAW-less
quad-band transmitters for mobile phones.
Index Terms—Cellular phone, channel hot carrier (CHC), deepsubmicron CMOS, digitally controlled oscillator (DCO), electromigration (EM), gate-oxide reliability, GSM, mobile phone, quantization noise, sigma-delta modulator, varactor, voltage-controlled
oscillator (VCO).
I. INTRODUCTION
HE cellular phone industry recently has been growing explosively. A cellular phone nowadays is not only an air
modem but integrates a variety of applications such as gaming,
e-mail, video streaming, and PDAs. As a result, the RF IC becomes only a small portion of the phone and the cost of RF functions is driven down more than ever. In order to reduce cost,
achieving a higher level integration for system-on-chip (SoC)
is demanded so that power consumption, bill-of-materials such
as pin count, external component count and PCB area, etc. are
minimized. That is, RF functions such as RF oscillators need
to be realized together with digital signal processors (DSPs),
memory, digital baseband, analog baseband and power management without any additional masks for analog extensions in a
CMOS process. However, what is advantageous to a DSP in a
digital CMOS process, such as low voltage and thin metal interconnects, is disadvantageous to RF circuits due to reduced
T
Manuscript received September 26, 2005; revised December 22, 2005.
The authors are with the Digital RF Processor (DRP ™) Department, Wireless
Analog Technology Center, Texas Instruments, Inc., Dallas, TX 75243 USA
(e-mail: [email protected]).
Digital Object Identifier 10.1109/JSSC.2006.872739
voltage headroom, low inductor , and reduced gate oxide reliability. Furthermore, to eliminate transmitter (TX) surfaceacoustic-wave (SAW) filters, the stringent requirement such as
GSM TX noise emission in receiver (RX) bands is now directly
applied to the TX local oscillator (LO). To alleviate these constraints, one approach is to realize as many traditional analog
functions as possible by digital logic gates. As a result, the difficulties of implementing analog functions in a nanometer-scale
CMOS process are greatly reduced. Instead, now, the newly implemented analog functions using digital logic gates can take
full advantage of CMOS process scaling.
In this paper, we present an RF digitally controlled oscillator
(DCO) system [1], [2] which can be directly connected to
an all-digital phase-locked loop (ADPLL) [3] with a straight
digital interface while satisfying the stringent GSM phase noise
requirements and covering all GSM quad-band frequencies between 824 and 1990 MHz without any external SAW filter. The
DCO system contains an oscillator core, two transmit and two
receive frequency dividers as well as several clock buffers. Since
at present, not every analog function in the transmit system is
implemented with digital logic gates, many common questions
on the analog-digital interface arise. In the rest of the paper, the
analog-digital interface will be described in detail including the
RF DAC characteristics, phase noise due to DAC quantization
noise, spurs due to digital signal processing, and how a very fine
frequency step is achieved with the DCO. In addition, reliability
concerns such as gate oxide integrity (GOI), channel hot carrier
(CHC) and metal electromigration (EM), as well as the output
buffer serving as a pre-power-amplifier (PPA) will also be
discussed.
II. OVERVIEW OF THE DCO SYSTEM
Shown in Fig. 1(a) is the DCO system. The DCO ASIC cell is
built with only digital I/Os even for the RF outputs at PCS band
and
)
(1900 MHz) since 10%–90% rise and fall time
of an inverter buffer in a 90-nm CMOS process is 40 ps. The
DCO ASIC cell contains a DCO core oscillating at 2 GSM
high-band (HB) frequencies, and frequency dividers for generating TX RF outputs and LO signals for RX mixers. Since GSM
is a half-duplex system, with a proper frequency planning, all
GSM quad bands can be covered with one single DCO core as
long as it has a 18.8% tuning range covering the frequencies
between 3296 and 3980 MHz. With a reasonable margin, realistically, 25% of frequency tuning range is required to cover all
four GSM frequency bands. Although it is typically a tradeoff
between phase noise and frequency tuning range, in order to
eliminate the need of an external TX SAW filter, the phase noise
162 dBc/Hz at 20-MHz offsets from all
still needs to be
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HUNG et al.: DCO SYSTEM FOR SAW-LESS TRANSMITTERS IN CELLULAR HANDSETS
Fig. 1. (a) DCO system, containing a DCO core, frequency dividers, and
buffers for both TX RF outputs and RX quadrature LOs. (b) DCO system
including the DCO ASIC cell and the input interface digital logic.
EGSM (GSM900) TX channels while satisfying the wide frequency tuning range.
As described in [4], typical difficulties of designing an RF
local oscillator for SAW-less and quad-band GSM TX are the
and the wide tuning range, where
low integrated inductor
the two performance parameters are commonly conflicting with
each other. Especially when using a standard digital CMOS
process which is optimized for digital logic speed, the metal
thickness and interconnect parasitic capacitance are typically
small resulting in a very high metal sheet resistance even though
the metal is made of copper. Hence, a typical inductor of 3.6
at 0.9 GHz is only 30% of that reported recently with an excellent 3-MHz offset phase noise [5]. Furthermore, to be able
to utilize a single DCO for all four GSM frequency bands, the
inductance of the LC tank must be reduced making it even more
difficult for the DCO to achieve low phase noise.
To overcome the obstacles surrounding the inductor and the
LC tank characteristics, it is instructive to revisit a phase noise
theory such as the well-known Leeson’s model [6]. For sim, where
plicity, assuming inductor quality factor
is the operating frequency, is the series inductance, and is
the parasitic series resistance. The Leeson’s phase noise model
can be rewritten as
(1)
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and
are noise transfer function and total noise
where
are
power injected into the LC tank, respectively; and
current consumption and voltage amplitude of the DCO, reand
are resonant frequency of DCO core
spectively;
, respectively; is the amplifier
and frequency offset from
noise factor; and are the tank quality factor and equivalent
parallel tank resistance, respectively. Referring to GSM900 fre, if
was increased from
to
, the
quencies as
product for the tank needed to be decreased to 1/16 of its
original value. Again, for simplicity, assuming that , , and
are constant,
and tank
, from
(1), increasing
from
to
would increase and
by four times, resulting in a 6-dB phase noise improvement.
may be reduced to decrease
The larger also implies that
the noise factor , further improving the phase noise. After the
DCO, the 4 stage will, in addition, improve phase noise by
12 dB if DCO noise dominates the overall system. There is al. For a
ways a concern of tuning range when increasing
and
, if decreased by a factor of , would stay
given
constant but would also decrease by a factor of , resulting in
a worse phase noise. In this work, was minimized with a constraint of tuning range. The challenging phase noise requirement
still remains but now moves to frequency dividers. However, it is
somewhat easier to design a low-noise divider than a DCO under
the process limitations. Consequently, the 162 dBc/Hz far-out
becomes achievable. Using dividers to
phase noise from
for GSM/EGSM bands and
for
generate quadrature
DCS/PCS bands from a
DCO core also has a great benefit of consuming a much less current and die area compared to
those using two oscillators or RC-CR networks.
Since the DCO core takes straight digital outputs from the
ADPLL, it needs to have a built-in RF DAC function. There
are four input data buses comprising the raw oscillator tuning
word (OTW) to the varactor banks, which are equivalent to the
tuning voltage controls in a conventional voltage-controlled oscillator (VCO). These data buses set the varactors to a desired
capacitance thereby establishing the desired DCO frequency.
The characteristics of the four varactor banks are summarized
in Table I. The PVT and acquisition banks (PB and AB) are
used for coarse tuning and have a large frequency step to calibrate process, voltage and temperature shifts as well as for
and
, are acticoarse channel acquisition. Their inputs,
vated sequentially during frequency locking and are frozen afterwards. The tracking banks (TIB and TFB) are used to perform
PLL tracking and data modulation. Their inputs, notated as
and
, are constantly toggled during normal operation. Highdithering operates on TFB to achieve fine frequency
speed
resolution. As will be discussed later, such varactor design of) characfers a highly linear frequency-code (DCO gain,
teristic, where code is the digital input tuning code. The digital
dithering of the tracking
logic, including the high-speed
bank varactors (Trk-F), and binary-to-unit weighted encoding
of the integer tracking (Trk-I) and acquisition (Acq) bank varactors, is tightly coupled to the DCO ASIC cell and constitute a
larger DCO system as shown in Fig. 1(b) that provides a digital
equivalence of a highly linear VCO with a wide dynamic range.
The conditioned OTW ( ,
and ) of the DCO system now
consists of three components, of which only one is normally ac-
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006
TABLE I
SUMMARY OF DCO VARACTOR BANKS
tive at a time. The DCO interface logic also performs conversion
from the signed to unsigned (binary-weighted or unit-weighted)
number representation.
For stringent far-out phase noise requirement of GSM900
band, the signal voltage level at DCO core is very high. This
imposes concerns on circuit reliability including GOI, CHC and
EM in an advanced digital CMOS process which has a low
for DCO
voltage rating. With the approach of increasing
core, the required SNR is relaxed and so is the reliability.
Fig. 2. Simplified circuit schematic of the DCO core.
III. BUILDING BLOCKS OF THE DCO ASIC CELL
As described earlier, the DCO ASIC cell consists of a DCO
core, four frequency dividers and several clock buffers. In addition to the required performance, each block was also designed
with silicon area and power consumption constraints. As a result, one DCO core and four different frequency dividers were
designed in this ASIC cell, which will be presented in detail in
the following sections.
A. DCO Core
A simplified DCO core schematic is shown in Fig. 2. The
topology is similar to that in [4] and [5].
and
are two
halves of a center-tapped inductor.
and
are metal–insulator–metal (MIM) capacitors forming the differential PB varrepresents the AB and TB varactor banks.
actor bank.
As stated in Section II, the 90-nm digital CMOS process used for
this work does not offer an inductor with a suitable . A 1- m
Al layer originally used to cover the bondpad is patterned and
connected in parallel with the inductor metal traces. So, the
inductor design is the first point of focus for the DCO core.
Inductor simulations were carried out using an in-house tool
which was calibrated with an array of test structures. Because
of the high resistivity of the metal trace, a tradeoff is needed between and parasitic capacitance of the inductor. The inductor
is formed with M2–M5 (copper) and an Al layer. The inductor
has width, spacing, and inner diameter of 12, 2, and 60 m, respectively, and has four turns. Using an
definition, the simulated single-ended is 4 and 6 at 0.9 and
3.6 GHz, respectively (Fig. 3). The differential phase-stability
[7] is 4 and 10.2 at 0.9 and 3.6 GHz, respectively. The peak
frequency with
definition is 2.3 GHz,
which is lower than the required lowest frequency of 3.296 GHz
definition, the peak
is
for GSM. With a phase-stability
3.6 GHz, so the inductor performance has been severely impacted by its shunt parasitic capacitance for the entire frequency
tuning range. The low peak and low self-resonant frequencies
are also tradeoff with metal electromigration which will be discussed in Section VI-C. With the metal stack, the technique of
using a patterned-ground shield underneath the inductor [8] is
not suitable.
Fig. 3. Simulated single-ended and differential phase-stability
ential is slightly 10 at the peak- frequency of 3.6 GHz.
Q
>
Q
Q. The differ-
There are three types of varactors available in this 90-nm
CMOS process: a MIM varactor (Fig. 2, [9]), a MOS varactor,
and a junction-diode varactor. In order to have a wide frequency
, a fully
tuning range while having a minimal VCO gain,
discrete tuning technique has been adopted [3], hence the
oscillator with digital control. Consequently, the junction-diode
varactor is not an option because there is no flat region in its
characteristic. Although the MOS varactor offers the best
of 80 @ 3.6 GHz with a good
ratio of 3.2,
while having the best process control in a CMOS process,
1.3 V across the terminals is needed to bias the capacitor at
curve under the large
the near-flat region of its effective
DCO signal swing as illustrated in Fig. 4, which is for the AB
varactor using nMOS transistors. When the MOS varactor is
connected in the DCO as C1/C2 and the poly gate terminal
is connected to OSCP/OSCM with a 1.4-V DC (Fig. 2), the
control voltage needs to be switched between 0.1 and 2.7 V.
The two control voltages not only make the DCO incompatible
with a low-voltage CMOS process, but also require two extra
low-dropout regulators (LDOs) which further cost two extra
external capacitors. In addition, considering the battery voltage
drop when an external high-power PA (HPA) is enabled during
data transmission, the headroom for the 2.7-V LDO is very
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HUNG et al.: DCO SYSTEM FOR SAW-LESS TRANSMITTERS IN CELLULAR HANDSETS
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Fig. 5. Measured frequency-code curve of the AB varactor. The straight line
is fairly constant.
implies that
K
Fig. 4. Measured CV curve (solid line) and derived effective CV curves under
large oscillator signal swings. With the intentional body effect, the measured
CV curve is not flat and does not have poly depletion in inversion region.
small. If the LDO loses regulation, the DCO will be vulnerable
to any noise and transient effects present at the battery terminal,
and the increased DCO frequency pushing could force the
ADPLL to be momentarily out of lock. As a result, a MIM
varactor was chosen for the PB which has the majority of the
tank capacitance.
As shown in Fig. 2, each bit of MIM varactor contains two
MIM capacitors connected differentially with a series switch
, two pull-up and two pull-down transistors to effectively
turn the varactor between its high and low-capacitance states.
Measured intrinsic of the MIM capacitor is 80 at 3.6 GHz.
is turned on, i.e., high-capacitance state, the varWhen
is turned off to be in low-caactor drops to 30. When
pacitance state, the parasitic capacitance of the MIM capacitor
and transistors has an effective of 50. The pull-down transisat 0 V so that
tors set the DC levels for drain and source of
can be efficiently turned into triode region while the weak
pull-up transistors set the DC level to VDDOSC to reduce the
thus increasing of the parasitic
parasitic capacitance of
capacitance. The pull-up pMOS can be implemented by either
resistors or transistors. The latter was chosen for silicon area efficiency. Compared to MOS varactors, MIM varactors have a
much lower . However, since the differential phase-stability
inductor is only 10, the impact of lower varactor is tolerable. When the MIM varactor is at its low-capacitance state,
the large DCO internal signal swing and the DC level of 1.4-V
supply voltage at source/drain of the pull-up transistors force the
-nwell junction diodes of the pull-up pMOS to modrain
mentarily go into forward-bias condition resulting in a latch-up
concern. However, since the forward-bias condition occurs only
in 50% of a 3–4 GHz period, the latch-up phenomenon with the
parasitic BJTs can not be triggered.
In order to achieve the frequency resolution summarized in
Table I, AB, TIB and TFB varactor banks need to have a small
C/LSB of 500, 50, and 50 aF, respectively. This is not possible
to implement using a MIM capacitor especially considering the
roughness of process control on metal interconnect relative to
critical dimensions (CD) of CMOS transistors. The variability
of frequency step among varactor bits (DNL) results in an inaccurate phase-locked frequency and errors in modulation, as well
as potentially increases phase noise due to random quantization
noise. Hence, gate oxide capacitance which has the tightest control in a CMOS process is used for AB, TIB, and TFB.
Instead of using an accumulation-mode MOS varactor, AB,
TIB, and TFB varactor banks are implemented using nMOS
transistors with a thicker gate oxide available to the base-line
process (intended for digital IO buffers) without any additional
cost. The electrical connection is also illustrated in Fig. 2. Gate
terminals are connected to oscillator nodes (OSCP/OSCM).
Source/drain nodes are connected together and are controlled
by ADPLL between VDDOSC and ground. Bulk is the substrate remaining at the ground potential. This arrangement
due to the body effect. The higher
results in a slightly higher
is desirable since it moves the transition between
and
toward VDDOSC/2. The measured
curve is shown
in Fig. 4 with solid line. With the intentional body effect, the
curve is not flat and does not have poly depletion
measured
in inversion region within the bias voltage range of interest.
After applying large oscillator waveforms, the effective
curves can be derived and are also shown in Fig. 4. The circles
at 0 and 1.4 V represent the operating points used in the DCO. It
can be observed that this varactor can easily tolerate 100-mV
shift which is larger than a typical process control limit.
curve for
Operating in the nonflat region of the effective
AB and TB varactor banks does not cause any phase noise nor
frequency pushing concerns since they are only a fraction of
the total capacitance of the LC tank.
In a conventional VCO where the frequency versus tuning
voltage is largely dependent of the varactor characteristic,
is typically highly nonlinear and requires compensation
to achieve a constant loop gain in a PLL [10]. In contrast,
is fairly constant (Fig. 5) over several MHz since the
curves.
varactors only operate between two states of their
does vary over large carrier frequency change but is
automatically calibrated and compensated on the fly in the
ADPLL [11].
and
, beNMOS is used for the cross-coupled pair,
noise than that of PMOS.
cause in this process it has a lower
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006
When
is operated in the saturation region, it can contribute
region.
as much as 15% to the total phase noise in the
Hence, it is biased in the linear region to reduce its noise contribution with a penalty of increased frequency pushing. Although
may be eliminated and the DCO current can
functionally,
be controlled by a programmable LDO, it was kept to somewhat increase PSRR so as to reduce the phase noise sensitivity
is configured with seven binary-weighted
to supply noise.
and providing high
bits. The second resonator operating at
is already low,
Z is especially important here since the of
improving effective/loaded tank is very critical.
B. Transmitter Dividers
A 4 frequency divider can improve phase noise of its input
signal from the DCO by 12 dB which is only true for close-in
but not far-out phase noise. At large frequency offsets, the divider noise limits the output phase noise. As described earlier,
it is difficult to design an oscillator core with a very low phase
noise floor especially when the resonator is poor. Therefore,
the noise should be budgeted such that after frequency division, DCO core noise still dominates. For example, assuming
the DCO core phase noise at 20-MHz offset from 3.6-GHz carrier is 153 dBc/Hz, theoretically, the phase noise should be
165 dBc/Hz after 4. If the intrinsic divider phase noise is
170 dBc/Hz at 20-MHz offset from 900-MHz output carrier,
when connected with 3.6-GHz DCO, the phase noise would become 163.8 dBc/Hz at 20-MHz offset from 900-MHz output
frequency. Because there is still a PPA cascaded with an external
high-power amplifier after divider, there is essentially no margin
with 163.8 dBc/Hz for EGSM band phase noise requirement.
Hence, the divider noise should be further reduced to 173
164.4 dBc/Hz. The DCO
dBc/Hz so the total phase noise is
far-out phase noise could also be further reduced by increasing
current consumption, but it is limited with transistor reliability.
For simplicity, if assuming the divider internal waveforms are
perfectly square, with the low 1.4-V supply, the divider output
, must be
nV Hz
dBc/Hz which is
noise,
very low.
Although an SCL divider [12] is commonly used for low
power, for quadrature outputs and for handling high input fre155 dBc/Hz is
quency, its broadband phase noise floor of
not low enough mainly due to its small internal signal amplitude,
long transistor turn-on time, and high conversion gain for both
AM and PM noise present in the divider. On the other hand, a
dynamic divider with square-wave internal signals can achieve
much lower noise floor. The only concern is the capability of
operating at a high input frequency. In order to handle the DCO
, two dynamic D flip-flops are cascaded with
frequency at
output feeding back to
input to form the 4 diinverted
vider as shown in Fig. 6. Unlike the flipflops in a standard digital
logic library, the sinusoidal input waveform does not represent a
simple ON and OFF, and the “latch” does not provide any mechanism to self-sustain the logic level but relies on the parasitic
capacitance to “memorize” the states. The principle is very similar to other high-speed prescalers [13] in order to achieve high
operating frequencies. The voltage headroom problem is alleviated by having only two stacked transistors (an inverter). Since
Fig. 6. Simplified circuit schematic of the
low phase noise floor.
44 dynamic frequency divider for
the waveform is square, and has a short rise and fall time, it contributes less noise and has a low sensitivity to AM and PM noise.
Similar to an SCL divider, if the switches of the passgate are
constantly closed, the dynamic divider will self-oscillate thus
becoming a ring oscillator. Although the dynamic divider can
be configured to generate quadrature outputs, it was designed to
generate only a single phase output for transmitters due to its
higher current consumption than that of the SCL divider. The
advanced CMOS process does have a strong advantage for the
dynamic divider to operate at a high frequency.
C. Receiver Dividers
As shown in Fig. 1, there are two receiver dividers. The first
frequency divider takes the DCO core waveform and performs
2. The outputs have quadrature phases and are buffered as
LO signals for HB receiver mixers. One of the 4 phases is also
buffered for ADPLL. Because this frequency divider needs to
handle the whole frequency tuning range from DCO especially
before ADPLL acquires locked condition, the maximum input
frequency could be as high as 4.5 GHz. The dynamic divider
used for transmitter does not have enough margin for 4.5-GHz
input frequency over PVT corners. Therefore, SCL latches
shown in Fig. 7 are used for the first 2. Although the phase
noise floor from an SCL divider is inferior to a dynamic divider,
it is satisfactory for the LO requirements of a GSM receiver.
The SCL frequency divider self-oscillates if the clock tranand
are continuously turned on [12] which is
sistors
possible when the input waveform is too small and the DC level
are high enough. Therefore, the diat gate nodes of
vider can be interpreted as an injection-locked oscillator. The
self-oscillation frequency is determined by delay time of the
latch which is dependent of transistor sizes and DC bias level.
As a result, it is expected to have an input amplitude versus input
frequency characteristic illustrated in Fig. 8 [14]. The sensitivity
is maximized at an input frequency twice the self-oscillation frequency. For a given input amplitude other than the maximum
sensitivity point, there are two potential circuit solutions. The
one with larger delay time could be used to save current consumption.
The second 2 frequency divider for producing quadrature
RX LB LO is designed with a dynamic divider. Because the
maximum input frequency has been reduced and the input waveform is square, it is advantageous to use a dynamic divider for
low power and low noise. The transistor sizes are much smaller
than TX dividers. Two cross-coupled connections are used for
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4
Fig. 9. Simplified schematic for the RX LB frequency divider. The 2 dynamic divider is capable of producing quadrature outputs at low power and low
noise.
Fig. 7. Schematic of the RX HB divider. Two SCL latches connected in a ring
with a negative feedback form a divide-by-2.
Fig. 10. Simplified schematic of the PPA. The power control is also done digitally similar to the frequency control for DCO.
Fig. 8. Characteristic of input amplitude versus operating frequency of an SCL
frequency divider. For a given input amplitude other than the maximum sensitivity point, there are two potential circuit solutions. The one with larger delay
could be used to save current consumption.
quadrature generation. The simplified schematic is illustrated in
Fig. 9.
D. Output Buffer (PPA)
The PPA [15], shown in Fig. 10, operates as a pseudo-class-E
amplifier. The input is driven by a square wave from the TX divider, which is the phase modulated signal from the ADPLL.
, are
In Fig. 10, nMOS transistors M1x, where
used as on/off switches. A radio-frequency choke (RFC) acts
as a bi-directional current source, connecting the switch to the
on-chip supply voltage regulator. C1 represents the on-chip capacitor connected in parallel to the switch and includes, for analysis purposes, the equivalent capacitance over one cycle given
of M1x. The residual second harmonic of
by the nonlinear
the transmit frequency is filtered by C2 and L1, allowing the
PPA itself to remain a single-ended circuit, reducing needed
matching network components and pin count. The remaining
matching network components are chosen to approach the condition where the switch output is critically damped such that the
drain voltage is low when the output current is high and vice
versa. Furthermore the extra input circuitry and output filtering
circuitry of class F type amplifiers are not required since the inverter delay is small enough for maximum GSM channel near
2 GHz.
Power control is accomplished in the PPA by recognizing
the impairments that a pseudo-class-E PPA suffers when implemented in a CMOS process. First, the MOS switch has a significant on-resistance and can only draw a limited current from the
RFC when the input waveform is high. Second, the rise and fall
times of the input digital waveform are not negligible although
they are typically less than 100 ps in this CMOS process. By reducing the effective switch size and increasing the effective ON
impedance, the output power of the PPA is reduced. The effective switch size is controlled by using an array of parallel nMOS
devices (M1x in Fig. 10). That is, by using some portion of the
array, arbitrary output power levels below the maximum output
power can be achieved. The control logic for each M1x switch
comprises an AND gate whose inputs are the phase-modulated
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006
output of the ADPLL and part of the amplitude control word
from a digital control block. The AND gate is implemented as
a pass-gate rather than an actual fully static AND gate, so that
thermal noise from the AND function is minimized, reducing
the ultimate broadband phase noise floor of the PPA.
IV. PHASE NOISE DUE TO
DITHERING
As shown in Table I, the tracking bank varactor provides a
frequency resolution of 20 kHz at GSM HB carrier frequencies,
which is relatively large. By nature of the PLL, the TIB varactor
will be dithered at the update rate of the digital input which is
26-MHz reference frequency, , in this design to achieve the
desired frequency. Assuming the digital input is a series of impulses and TIB capacitance changes instantly following the impulses, the PLL is effectively making a white dithering on TIB
rate. However, in reality, both the digital input
varactor at
and the varactor capacitance switching are not impulses, but
square waves corresponding to a zero-order hold operation, the
white noise assumption is not strictly correct and the quantization noise needs to be multiplied by a sinc function. The quantization noise can be expressed as
(2)
and can be calculated to be 111 dBc/Hz at 400-kHz offset
from a GSM LB carrier and has a 20-dB/dec slope below
10-MHz frequency offset. Such phase noise is too high to
meet GSM modulation mask specification. To reduce the quantization noise, the oversampling rate can be increased from
to
, thereby reducing the quantization noise by 10 dB.
The resulting phase noise marginally satisfies requirements
for all GSM bands. To increase the margin, a second-order
dithering at
on TFB is implemented. The
MASH
dithering moves the quantization noise energy to
and greatly reduces the close-in DCO phase noise. For instance,
using (2), with an additional 8-bit resolution, the 400-kHz
offset phase noise at GSM HB would be theoretically reduced
160 dBc/Hz.
to
and
of the digital
Another nonideality is the finite
inputs to the TFB bits. To investigate this second-order effect,
a simulation approach was taken. A Verilog-A model was built
block to co-simulate with the transistor-level
for the MASH
DCO. Because the simulations need to have both the accuracy
for 3.6-GHz DCO signals and a large transient data length for
observing the close-in phase noise, a simplified DCO circuit
larger TFB varactor and
were used. The
with
results are shown in Fig. 11. It can be clearly seen that when
and
are increased from 100 to 200 ps, the close-in
phase noise has a trend of increasing 10 dB. Below 100 ps, no
significant difference is observed from the 100-ps curve. This
is in line with the 90-nm CMOS process capability that typical
and
are 40 ps.
10%–90%
Fig. 11. Simulated phase noise contribution with respect to T
the TFB digital inputs.
and T
of
V. PRINCIPLE OF SYNCHRONOUSLY OPTIMAL DCO
TUNING WORD RETIMING
Fig. 12 illustrates the principle of synchronously optimal
DCO input tuning word retiming method [16]. This idea is
based on the observation that when changing the tuning control
input of an oscillator in order to adjust its phase/frequency in a
normal PLL operation, it is quite a disturbing event to the oscillation, which reveals itself as phase noise at the oscillator output
[17]. This is especially noticeable in case of a sample-mode
oscillator such as the DCO, where its oscillating frequency is
commanded to change at discrete times. Since the oscillating
frequency of an LC tank is controlled by a voltage-to-capacitance conversion device, i.e., varactor, the worst moments to
change the capacitance is at the instances when the oscillating
energy is fully stored in a capacitor because
is maximized as shown in Fig. 13(a). These perturbations
are AM-to-PM translated by the oscillator circuit into phase
noise. On the other hand, changing the varactor capacitance
at times when it is fully discharged would hardly affect the
as illustrated in Fig. 13(b).
oscillator phase noise since
The intuitive solution is to control the timing moments so the
perturbations are minimized. This is implemented by feeding
the delayed oscillator edge transitions back as the clock input
to the synchronous register retiming stage, as shown in Fig. 12.
The retiming stage ensures that the input control data seen by
the oscillator is at a precise and optimal time near the oscillator
zero-crossings. The actual delay control is accomplished both
by digital logic and by a voltage-controlled delay line such as
an inverter string with a tunable supply voltage. As long as the
total delay exceeds the DCO clock period, the full 360 degree
coverage is guaranteed.
Fig. 14 plots the measured GMSK modulated spectrum
at 400-kHz offset versus the total delay around the DCO.
The round trip starts from the LC-tank differential output
zero-crossing to the nearest transition time of the DCO tuning
word input. Depending on the timing skew between the varactor
state transition and the LC-tank state, the phase noise of the
modulating spectrum can vary as much as 4 dB. The flyback
delay is set algorithmically to minimize the phase noise. The
algorithm to determine the optimal delay takes advantage of the
fact that the phase error which is related to the DCO phase noise
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HUNG et al.: DCO SYSTEM FOR SAW-LESS TRANSMITTERS IN CELLULAR HANDSETS
1167
Fig. 12. Synchronously optimal sampling and timing adjustment of the DCO
input.
Fig. 14. Measured 400-kHz phase noise of the modulated spectrum versus the
total round-trip delay. The phase noise is measured in the resolution bandwidth
of 30 kHz and compared against the phase noise integrated in the 30-kHz region around the center frequency. The operating TX frequency of 824.2 MHz
corresponds to 303 ps of the resonating LC-tank period.
and gate voltage waveforms shown in Fig. 15, the effective
overshoot, denoted as
, can be calculated using the
following equation [18]:
(3)
Fig. 13. Waveforms for capacitance change of an LC-tank oscillator.
is already in digital form for processing. Mean-squared-error
statistics of the digital phase-error samples are optimized by
utilizing the readily available digital signal processing hardware.
VI. RELIABILITY
For a stringent phase noise requirement, both signal power
level and signal-to-noise ratio (SNR) need to be very high so
that the absolute noise power from the far-out spectral skirt is
still above the broadband phase noise floor. This imposes concerns on GOI, CHC and metal EM in an advanced digital CMOS
process since the gate oxide is thin with a low voltage rating, the
channel length is short and the metal thickness is thin. Although
from
to
, the required SNR is reby increasing
laxed, thus the reduced internal voltage and current swings of
the DCO core, there are still concerns on marginality.
A. Transistor Reliability—GOI
Referring to Fig. 2, assuming the oscillator nodes, OSCP
and OSCM, have 0.9-V voltage amplitude, in order to be
as
better than 153 dBc/Hz at 20-MHz offset from
described in Section III-B, the noise level of DCO core must
nV
for transistors operating under a sinusoidal
be
waveform. With a 1.4-V supply voltage, the maximum absolute
voltage on drain and gate nodes would be at least 2.3 V on
1.3-V rated transistors. Applying a statistical model on the drain
is
where is a constant, is the oscillation period, and
waveform. The calculated
is 1.9 V for
the transient
167 dBc/Hz at TX divider output, which means equivalently,
stays at 1.9 V for 25% of , 1.4 V for another 25% of
and 0 V for the rest of . This result is within the process limit.
would drop to 1.7 V, resulting in a
For 162 dBc/Hz,
reasonable margin in reality.
B. Transistor Reliability—CHC
The transistor degradation due to CHC include decreased
channel current, increased threshold voltage and decreased
transconductance over time [19]. The transistors of concern
and
, in Fig. 2.
are again the cross-coupled transistors,
,
CHC life time is dependent of several factors such as
and channel length. In general, the worst-case operating
. In the DCO waveform shown in
condition is when
occurs at the points where
Fig. 15, the condition of
the waveforms have the largest absolute value of slope. That
is very short. For the extreme
is, the duration of
and
, there is no
conditions such as
and
are not the
CHC concern. The channel length for
minimum allowed dimension of this process further reducing
the CHC concern.
C. Metal Electromigration (EM)
In advanced digital CMOS processes, although the interconnect metal is typically made of copper (Cu), the metal thick-
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1168
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006
Fig. 15. Voltage waveforms for the cross-coupled transistors in Fig. 2. The calis 1.9 V to have 167 dBc/Hz at 20-MHz offset for EGSM freculated V
quencies.
0
ness is very small in order to reduce the parasitic capacitance
between adjacent metal lines for higher logic operating speed.
Compared to Al, Cu can tolerate much higher current density for
the same thickness and width. However, after the Cu thickness
being scaled down for digital logic speed, the EM capability of
Cu per layer is only slightly better than Al. The EM degradation
would cause metal sheet resistance to increase, thus degrading
circuit performance.
Typical EM concerns can be resolved by increasing metal
width and/or metal stack. However, on-chip spiral inductor is
one exception that the metal cannot be arbitrarily changed. As
shown in Fig. 3, the DCO operates around the inductor peakfrequency, there is only a small flexibility to increase the inductor metal width or number of metal layers. The main concerns here are: 1) the current distribution between Cu and Al
metal layers such that there may be too much current flowing
in Al especially when the Al layer is able to increase overall
inductor significantly and 2) the Cu-Al interface may have
degraded EM than the metal layers alone. Upon a detailed calculation, it was determined that combining M3–M5 Cu layers
and the Al layer for the inductor would offer minimum-required
for DCO while peak- frequency is higher than the maximum GSM channel in PCS band. However, there is essentially
no margin for EM and phase noise requirement. Therefore, M2
was added and the metal width is limited to 12 m. The addition
of M2 moved the differential phase-stability-peak- frequency
to 3.6 GHz which means there is excessive parasitic capacitance from the inductor and has an adverse effect on the overall
frequency tuning range. As a result, iterations for distributions
between and values were exercised to achieve the needed
and to cover GSM quad bands with one single DCO core.
VII. EXPERIMENTAL RESULTS
The measurement was done with the DCO system, an internal regulator supplying 1.4 V to DCO system and the PPA.
The Aeroflex PN9000B delay-line phase noise measurement
170 dBc/Hz. After de-emmodule has a phase noise floor of
bedding the noise floor from the measured raw data, the DCO
phase noise plot is shown in Fig. 16. At 400-kHz, 3-MHz and
20-MHz frequency offsets, the phase noise is 123.5, 149,
Fig. 16. Measured phase noise of DCO system + LDO + PPA. The phase
noise at 400-kHz, 3-MHz and 20-MHz frequency offsets are 123.5, 149,
and 167 dBc/Hz, respectively, from a 915-MHz carrier.
0
0
0
TABLE II
SUMMARY OF THE PERFORMANCE
and 167 dBc/Hz, respectively, from a 915-MHz carrier, which
is the highest frequency requiring 20-MHz offset phase noise
162 dBc/Hz. There is no visible difference between
to be
turning on and off the
dithering, indicating that the
noise is below the phase noise of the DCO system [1]. The
171 dBm at 8-dBm output
PPA alone has a noise floor of
power. Hence, the PPA degrades the phase noise at TX LB divider output by 0.27 dB. The measured TX LB phase noise at
20-MHz offset has a 5-dB margin which is more than enough to
cover process and temperature corners. There is a small hump
in the data between 10- and 20-MHz offset which is due to the
PCB.
Unlike [4] whose phase noise corner between 20 and
30 dB/dec is 500 kHz, the corner for this design is at
1 MHz. When programming
to have a smaller capacitance, the close-in phase noise such as that at 400-kHz offset
has too much capacitance
improves. It is believed that
causing the voltage waveforms at OSCP/M to be unsymmetrical resulting in a higher 20–30 dB/dec corner [17].
The DCO system has a frequency tuning range of 893 MHz
at DCO core frequency. Since GSM quad band needs 684 MHz,
there is a 210 MHz margin for PVT corners. Temperature does
not have a significant impact on frequency tuning range. The
measured DNL of TIB is 4 kHz corresponding to 20% of TIB
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HUNG et al.: DCO SYSTEM FOR SAW-LESS TRANSMITTERS IN CELLULAR HANDSETS
1169
1.2-V supply. Finally, the approach is naturally suitable for SoC
and enables the software-defined radio.
REFERENCES
Fig. 17. Die photo of the DCO system. It only occupies 550
cluding >200-pF supply bypass capacitor.
2 800 m
in-
frequency step. A dynamic element matching is implemented in
the ADPLL to mitigate the DNL.
The DCO system is supplied by a single LDO. The DCO core
draws 18 mA when the PPA output has 167 dBc/Hz phase
noise at a 20-MHz offset from the highest EGSM channel. The
current can be reduced for 20-MHz offset phase noise in normal
operation. The dependence of close-in phase noise to DCO core
current consumption is 1 dB when the current is programmed
between 3 and 18 mA. Table II summarizes the measurement results with performance targets. A die photo is shown in Fig. 17.
The DCO system occupies only 550 800 m .
VIII. CONCLUSION
An RF digitally controlled oscillator system including a DCO
core with a built-in RF DAC and frequency dividers for SAWless cellular transmitter has been implemented and described
in detail. Using a standard digital 90-nm CMOS process, the
DCO system has been demonstrated with excellent performance
that exceeds the requirements of the most popular cellular standard, GSM. The fully digital frequency tuning enables to employ all-digital frequency synthesizers, which would typically
include a digital phase detector and a digital loop filter, in the
most advanced low-voltage digital deep-submicron CMOS processes. The varactor (RF DAC) design results in a highly linear
DCO gain and is insensitive to process variations such as
shift. The
dithering helps to achieve a fine frequency resolution and contributes negligible phase noise in the DCO output.
The total narrowband frequency dynamic range is equivalent
to 23 bits since it extends 400 MHz with the open-loop frequency resolution of 40 Hz in the 1.6–2.0 GHz bands. The measured phase noise at 20-MHz offset is 167 dBc/Hz including
the noise from LDO and PPA. Although the internal oscillator
swing is large, detailed analyses with design tradeoff result in no
concerns on gate oxide integrity, channel hot carrier and metal
electromigration. This work not only demonstrates feasibility of
a DCO system in fully digital RF frequency synthesizers for mobile phones but also promotes the most cost-effective integration
of the RF oscillator with the digital back-end onto a single silicon die. Because of the digital nature, the DCO system can be
scaled down for future CMOS process such as 65-nm node with
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Chih-Ming Hung (S’98–M’00) received the B.S.
degree in electrical engineering from the National
Central University, Chung-Li, Taiwan, R.O.C., in
1993, and the M.S. and Ph.D. degrees in electrical
and computer engineering from the University of
Florida, Gainesville, in 1997 and 2000, respectively.
In July 2000, he joined Texas Instruments, Inc.,
Dallas, TX, where he is currently a Senior Member,
Group Technical Staff. He has focused on R&D of
advanced CMOS RF IC for wireless cellular applications. Since 2002, he has been a Design Manager
responsible of RF front-ends and integration of RF, analog and digital SoC for
the digital RF processor (DRP). He has authored or coauthored 43 journal and
conference publications. He has 2 granted patents and 10 patents pending. He
also serves as a reviewer for various technical journals and conferences. His interests include CMOS RF IC design, integrated passive components, and SoC
integration.
Dr. Hung received several research grants and a fellowship between 1996
and 2000 working on high-performance fully integrated CMOS PLLs and
VCOs between 900-MHz and 30-GHz frequency range including developing
on-chip passive components in CMOS processes suitable for those frequencies.
In November 1999 and February 2000, he and his colleagues received the
Semiconductor Research Corporation Copper Design Contest winner awards,
respectively with a 15-GHz fully integrated CMOS on-chip wireless clock
distribution system. He has received 2004 Engineer of the Year Awards from
both IEEE Dallas and Texas Society of Professional Engineers.
Robert Bogdan Staszewski (M’94–SM’05) received the B.S.E.E. (summa cum laude), M.S.E.E.,
and Ph.D. degrees from the University of Texas at
Dallas in 1991, 1992, and 2002, respectively.
From 1991 to 1995, he was with Alcatel Network
Systems, Richardson, TX, working on Sonnet
cross-connect systems for fiber optics communications. He joined Texas Instruments, Inc., Dallas,
TX, in 1995, where he is currently a Distinguished
Member of Technical Staff. From 1995 to 1999,
he was engaged in advanced CMOS read channel
development for hard disk drives. In 1999, he co-started a Digital Radio
Frequency Processor (DRP) group within Texas Instruments with a mission to
invent new digitally intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. He currently leads the DRP
system and design development for transmitters and frequency synthesizers.
He has authored or coauthored 40 journal and conference publications and
holds 25 issued U.S. patents. His research interests include deep-submicron
CMOS architectures and circuits for frequency synthesizers, transmitters, and
receivers.
Nathen Barton received the B.S.E.E. degree from
Washington State University, Pullman, and the
M.S.E.E. degree from Oregon State University,
Corvallis, in 1998 and 2002, respectively.
He first joined Texas Instruments, Inc., Dallas, TX,
as an intern in 1997. His research interests include
ultra-low phase noise LC oscillators, frequency dividers, ultrahigh-frequency oscillators, and designautomation software.
Meng-Chang Lee (S’00–M’02) received the B.S.
degree from National Taiwan University, Taipei,
Taiwan, R.O.C., in 1999, and the M.S. degree from
the Georgia Institute of Technology, Atlanta, in
2002, all in electrical engineering.
In 2001, he interned with Texas Instruments,
Dallas, TX, and worked on a high-speed serial link
interface for base station application. Since 2002, he
has been with the RF-CMOS group at Texas Instruments as an RFIC Designer working on single-chip
solutions for GSM/GPRS/EDGE.
Dirk Leipold received the Diploma in physics from
the University of Konstanz, Konstanz, Germany, in
1991. From 1991 to 1995, he worked in the Paul
Scherrer Institute Zurich on Smart pixel optoelectronics. He received the Ph.D. degree in physics
from the University of Konstanz in 1995.
He joined Texas Instruments in Germany in 1995
where he worked in RF process integration, device
characterization, and modeling, in particular the development of RF-CMOS technologies on high resistivity substrates. From 1998 to 1999, he represented
Texas Instruments in the ETSI Hiperlan2 committee, where he was editor for
the PHY layer technical specification. In 1999, he moved to Texas Instruments,
Inc., Dallas, TX, where he is currently a Design Manager of the Digital RF Processor (DRP) group. His research interests include advanced RF architectures,
nanometer-scale CMOS, and quantum electronics.
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