Download Free research poster template

Survey
yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Document related concepts

Spectrum analyzer wikipedia, lookup

Resistive opto-isolator wikipedia, lookup

Switched-mode power supply wikipedia, lookup

Three-phase electric power wikipedia, lookup

Mathematics of radio engineering wikipedia, lookup

Time-to-digital converter wikipedia, lookup

Solar micro-inverter wikipedia, lookup

Bode plot wikipedia, lookup

Variable-frequency drive wikipedia, lookup

Rectiverter wikipedia, lookup

Power inverter wikipedia, lookup

Islanding wikipedia, lookup

Mains electricity wikipedia, lookup

Chirp spectrum wikipedia, lookup

Wien bridge oscillator wikipedia, lookup

Utility frequency wikipedia, lookup

Phase-locked loop wikipedia, lookup

Superheterodyne receiver wikipedia, lookup

Heterodyne wikipedia, lookup

Transcript
A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity
605410069 李奕增
605410136 李銘軒
Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Seok Kim, and Kee-Won Kwon,
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 10, pp. 632-636, October 2011
Abstract
This brief presents a wide frequency range
digitally controlled oscillator (DCO) with low
supply sensitivity and low power
consumption. We propose a compensation
scheme employing feedforward inverters to
suppress supply noise. Both wide frequency
range and fine resolution are obtained using
a hierarchical architecture consisting of a
coarse delay chain and an interpolator. The
proposed DCO was fabricated in a 0.13-μm
CMOS process. It successfully eliminates
noise components due to supply variation.
The phase noise at 1-MHz frequency offset
from the carrier frequency of 700 MHz is
−106.3 dBc/Hz. The frequency range of the
DCO is measured from 320 MHz to 1.25 GHz.
Introduction
Analog-based phased-locked loop(PLL)
accompanies low supply voltage and has gate
leakage of transistors problem. Therefore,
ADPLL is adopted.
ADPLL can implemented in an LC tank type
with digitally controlled varactors or a ring
oscillator type. Ring oscillator type is used.
Architecture
Results
Conclusion
A wide-frequency-range DCO that is
insensitive to supply variation due to a
feedforward inverter in a single delay.
(a)
Fig. (a) shows the proposed supply compensation
scheme using only a single delay chain. This
method utilizes the feedforward inverter as a
supply compensator (“C”). The compensating
inverter transports the signals before the two
consecutive main drivers (“M”) do, unless the
delay of C is longer than twice theM delay. The
opposite polarities of the compensating and
main paths can annihilate the supply
dependence. If the delay of C is comparable with
that of two main inverters, C cancels supply
dependence without damaging absolute delay as
much as in the conventional latch compensator
because the proposed compensating inverter did
not complete transition when the node is flipped
back by the main driver. As a consequence, the
frequency of a ring oscillator with the proposed
compensator can operate at higher frequency.
The smaller the compensator is, the faster the
speed is, if it satisfies the condition of oscillation.
We designed a feedforward inverter whose pullup and pull-down path consists of two seriesconnected transistors. As we aforementioned,
this makes the delay of the stage independent of
supply variation in the same manner as
conventional supply compensation.
This paper presents an improved
compensation scheme for supply noise using
feedforward stages.
This figure shows the DCO architecture using
the proposed compensation scheme.
 This method can reduce the silicon area of
the DCO core by about half and its power
consumption by two thirds.
(b)
Fig. (b) shows the layout diagram.
(d)
(c)
The Fig (c) and (d) shows the frequency
spectra without and with supply
compensation.
(e)
The measured single-sideband (SSB)
phase noise with the proposed scheme is
shown in Fig. (e).The phase noise is −106.3
dBc/Hz at 1-MHz frequency offset from the
carrier frequency of 700 MHz. Although there
are some spurs in the region of the high
frequency offset, the spur level of the worst
case is below −100 dBc/Hz. The test chip
works at the frequency range from 320 MHz
to 1.25 GHz with integral nonlinearity of 4.0
LSB and differential nonlinearity of 0.6 LSB at
nominal voltage. The proposed compensator
eliminates almost all the spurs at various
carrier frequencies.
 The phase noise is 106.3 dBc/Hz at 1-MHz
freuqency offset from the carrier frequency of
700MHz.The proposed compensation worked
at a frequency range from 320 MHZ to
1.25GHz.
Acknowledgements
This work was supported in part by the
Information Technology
Research and Development Program of the
Ministry of Knowledge Economy of
Korea/Institute of Information Technology
Advancement under Grant 2009-F-015-01 and
in part by the IC Design Education Center at
Korea Advanced Institute of Science and
Technology. This paper was recommended
by Associate Editor S. Palermo.
Contact Information
Please contact e-mail: [email protected]
Color versions of one or more of the figures
in this paper are available online at
http://ieeexplore.ieee.org.
Digital Object Identifier
10.1109/TCSII.2011.2164146