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VARIABLE GAIN AMPLIFIER USING GAIN COMPENSATION IN 0.18um CMOS TECHNOLOGY 1 1 MOOKAMBIKA.K, 2K.C NARASIMHAMURTHY PG Scholar, Dept. of Telecommunication Engg. SIT, Tumakuru, India. 2 Professor, Dept. of Telecommunication Engg. SIT, Tumakuru, India. E-mail: [email protected], [email protected] Abstract— In this paper, Variable gain amplifier (VGA) has been designed using the gain compensation technique on H-SPICE platform using 180nm Predictive Technology Model (PTM). VGA with the larger bandwidth, along with lower power consumption, dynamic variable gain has been designed. The feedback and feed forward bank of resistors have been implemented in order to compensate for the gain. For the better performance and to increase the common mode rejection ratio, the common mode feedback technique is used. The gain varies from -1 to 40dB with 0.5dB gain steps with bandwidth of 1MHz and the power consumption is 1.98mW. two cascade signal summing VGA stages. This attains a gain range of 70dB and a gain error less than 2dB and power dissipation is 36mW. The signal summing VGA operates well with respect to low power high frequency operation when compared to other conventional methods. But the signal summing method has narrower gain range for linear in dB which increases power dissipation[3]. I. INTRODUCTION Variable gain amplifier is one of the important building blocks of the transceiver. Whenever the RF signals are received from antenna, it’ll have large amplitude variation. In order to make these different signal amplitudes get the correct demodulation, RF receiver’s usually use VGA to control gain. VGA will adjust the amplitudes of received signal so as to keep the voltage level constant signal level at ADC input. VGA is used to provide a fixed output for different and large variations of input in order to improve the dynamic range of the transceiver. VGAs are continuously tuned by analog control signals. A high frequency CMOS VGA implementing a new gain stage cell based. This technique enhances the operating frequency at 350MHz and the gain control range of 84dB. With 1.8V power supply VGA is implemented using 180nm technology. This VGA is considered to be suitable for an IF amplifier [4]. In this paper, to implement VGA and to compensate for the gain, array of feedback resistors and feed forward resistors are use along with the common mode feedback circuit (CMFB) technique. This CMFB includes the cascode differential amplifier, current mirror in order to steer the current and CS amplifier with capacitor in order to compensate for the gain. The resistor bank will provide the required gain which varies from -1dB to 40dB. In order to achieve dB linear characteristics of the VGA, the implementation of exponential function is required which was done in standard 65nm CMOS technology rather than bipolar technology. This achieves a variable gain of 76dB with gain error of ±0.5dB. Due to the square and linear characteristics of MOSFET, only the first and second order terms of the Taylor’s series of the exponential function is realized. Gain error will be the caused by the higher order terms and hence those are omitted. Even for small gain error and good accuracy, additional circuits are needed to be implemented to compensate for those higher order terms. This leads to higher power consumption and larger bandwidth [1]. Wideband exponential gain controlled VGA are introduced. This proposed circuit is based on a pseudo exponential polynomial. This pseudo exponential polynomial gain control function is implemented by the source coupled pair with diode connected loads. But this is for only low power supply and high speed devices. 0.5µm CMOS process is used to obtain the bandwidth of 150MHz of the proposed amplifier. With the power supply of 3.3V, 15dB gain control range is obtained along with the power consumption 12.5mW [2]. VGA consists of II. VGA ARCHITECTURE A. Differential feedback VGA architecture VGA must convert the single ended to differential output for ADC input and the architecture of differential feedback VGA architecture is shown below with the output voltages. Proceedings of 43rd IRF International Conference, 29th May, 2016, Chennai, India, ISBN: 978-93-86083-23-4 48 Variable Gain Amplifier Using Gain Compensation in 0.18um CMOS Technology Fig (2) Single ended feedback VGA architecture III. ARCHITECTURE OF COMMON MODE FEEDBACK CIRCUIT Fig (1) Differential feedback VGA architecture B. Single ended feedback VGA architecture Single ended feedback VGA gives more linearity than differential feedback VGA and hence the required number of resistors is also less and hence the noise that is contributed is less. But the noise that is contributed by the transistors in the output stage common mode feedback circuit (CMFB) at the single ended is more. This increases the overall noise of the circuit. But in case of differential amplifier, that noise will be cancelled by the differential feedback. Hence overall noise of differential feedback circuit will be less. Below shown is the architecture of single ended feedback circuit. In order to obtain larger output swing giving low voltage supply for the small size technology, use of fully differential amplifier is necessary. Hence the use of common mode feedback (CMFB) circuit is compulsory. This common mode feedback circuit will increase the common mode rejection ratio to yield a better performance. Here, the common mode signals are first monitored and then compared it with the reference voltage. The corrected signal obtained will be fed back to the input of differential amplifier. The circuit diagram of CMFB is shown. Fig (3) Common mode feedback architecture The voltage is supplied at the node named Vdd, ac input is given at Vin and the bias voltages are given to the gate of the transistors. Capacitors are used to compensate for the gain. IV. COMPLETE VGA ARCHITECTURE The variable gain amplifier varies from -1dB to 40dB in steps of 0.5dB to obtain linear in dB gain steps also Proceedings of 43rd IRF International Conference, 29th May, 2016, Chennai, India, ISBN: 978-93-86083-23-4 49 Variable Gain Amplifier Using Gain Compensation in 0.18um CMOS Technology with the resistor values increasing linearly, we need to consider the gain decrement of 0.5dB from initial gain Go to a gain of G. For particular value R10 and R20, the R1 and R2 values are changed for 0.5dB gain decrement. The values are as shown below in the table. Fig (5) Feedback resistor bank Table(1): R10 and R20 values for different gain. Fig (6) Overall VGA schematic Table (2) Performance summary In order to implement the variable gain amplifier using the gain compensation method, the feed forward resistor bank and feedback resistor bank are implemented. Both the banks consist of transistors acting as switches. These switches are implemented using NMOS transistors. Output of the feed forward resistor bank is connected to the input of the OpAmp. Input terminal of the feedback is connected to the output terminal of the OpAmp and output is connected to the input of the OpAmp. Equivalent circuit of the OpAmp is the CMFB as shown earlier. Below shown is the complete circuit of VGA. Fig (7) Frequency Response of the Variable Gain Amplifier CONCLUSION A variable gain amplifier using gain compensation technique is presented by this paper. Common mode feedback circuit with feed forward and feedback bank of resistors are implemented to obtain the required higher dynamic range of gain in dB to yield better performance with low power consumption in the higher bandwidth. REFERENCES [1] Fig (4) Feed forward resistor bank I. Choi, H. Seo and B. Kim, “aaccurate dB-linear variable gain amplifier with gain error compensation,” IEEE J. Solid-State Circuits, vol.48, no. 2, pp. 456-464, feb. 2013. Proceedings of 43rd IRF International Conference, 29th May, 2016, Chennai, India, ISBN: 978-93-86083-23-4 50 Variable Gain Amplifier Using Gain Compensation in 0.18um CMOS Technology [2] [3] [4] [5] P. Huang, L. Y. Chiou, and C. K. Wang, “A 3.3-V CMOS wideband exponential control variable-gain-amplifier,” in Proc. 1998 IEEE Int. Symp. Circuits Syst. (ISCAS), Jun. 1998, pp. 285–288. S. Otaka, G. Takemura, and H Tanimoto, “ A low power low noise accurate linear in dB Variable gain amplifier with 500MHz bandwidth,” IEEE J. Solid state circuit, vol. 35, no. 12, Dec. 2000, pp. 1942-1948. Dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications,” Electron Lett., vol. 39, no. 10, pp. 759–760, May 2003. Hang Liu, Xi Zhu, Chirn Chye Boon, Senior Member, IEEE, and Xiaofeng He, “Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology,” IEEE journal of solid-state circuits, VOL. 50, NO. 2, FEBRUARY 2015. [6] [7] [8] [9] Edgar Sánchez-Sinencio, “Common-Mode Control Techniques for Low Voltage Continuous-Time Analog Signal Processors,” Texas A&M University Analog and Mixed-Signal Center Dept. of Electrical Engineering, College Station, TX 77840, USA. Amrith Sukumaran, Kunal Karanjkar, Sandeep Jhanwar, Nagendra Krishnapura, Shanthi Pavan, “A 1.2V 285µA Analog Front End Chip for a Digital Hearing Aid in 0.13µm CMOS,” IEEE Asian solid-state circuits conference 2013. Phillip. E. Allen and Douglas. R. Holberg, CMOS analog circuit design, 2nd ed. New York, Oxford University. 2002. Adel. S. Sedra and Kenneth. C. Smith, Microelectronic circuits, 5th ed. New York, Oxford University.2004 Proceedings of 43rd IRF International Conference, 29th May, 2016, Chennai, India, ISBN: 978-93-86083-23-4 51