Download Final Exam W0809

Course
Number
Electronics II
ELEC 312/4
Examination
Date
Final
Time
April 27, 2009
3 hours
Instructor(s)
Dr.R. Raut
Materials allowed:
X
Calculators allowed:
No
No
Yes
(Please specify)
X
Yes
Students are allowed to use ENCS faculty approved calculators
Special Instructions:
You MUST attempt Q.1 (soft skill component) .
For Q.2-Q.7, answer any FOUR questions.
Fill in the Table below indicating the answers that the instructor need to mark.
If you do not fill in the Table, the instructor will mark your answers according to his discretions
Show all steps clearly in neat and legible handwriting.
Students are required to return the question paper together with exam booklet(s).
Table
Answers to be
marked
Marks
Q.1
(compulsory)
Some Useful Formulae
MOSFETs (Saturation region):
g m  2k WI D L , ro  V A / I D ,   1 / V A
BJTs:
g m  I C / VT , VT  25 mV , r  h fe / g m , h fe  ic / ib , ro  V A / I C
Section
W
# of pages
6
Compulsory ( soft skill component)
Q.1: In many electronic communication systems, a circuit to obtain signals in phase
quadrature (i.e., 90o out of phase) is required. An OP-AMP based all-pass filter circuit
shown below could serve this purpose.
R1
R1
vi
A
R
vo
C
Figure 1:
(i) By appropriate analysis, establish the condition under which the signals vi , and vo
v
can be at phase quadrature, i.e., the angle of T ( s)  o will be -90o ? Assume
vi
that the OP-AMP is ideal.
(ii) In an FM communication system we need two phase quadrature signals at 10.7
MHz. Given that R=10 k Ω, what value of C should be used?
Some Useful Formulae
MOSFETs (Saturation region):
g m  2k WI D L , ro  V A / I D ,   1 / V A
BJTs:
g m  I C / VT , VT  25 mV , r  h fe / g m , h fe  ic / ib , ro  V A / I C
Answer any FOUR questions
Q. 2: For the class B output stage shown below, let VCC = 6 V and RL =4 Ω. The output
vo is a sinusoid with 4.5 V peak value.
Figure 2:
Find
(i) the average output power.
(ii) the average power drawn from each DC power supply.
(iii) the power conversion efficiency.
(iv) the maximum power that each transistor must be capable of dissipating safely.
Q.3: A common-emitter amplifier with the ac equivalent circuit shown below
has:
C  10 pF , C   0.5 pF , C L  2 pF , g m  20 mA / V , h fe  100, rx  200 ,
RL  5 k, and RS  1 k.
RS
rx
C

vs


v


r
C
Figure 3:
The voltage gain function of the amplifier is given by:
g m v
RL
CL
vo

 g s ( g m  sC  )
vo
 2
v s s (C C L  C  C L  C C  )  s[ g s (C   C L )  g  (C   C L )  g L (C  C  )  g m C  ]  g s g L  g  g L
In the above, we have used g s 
1
1
1
, g  , g L 
RS  rx
r
RL
Find (i) the mid-band gain AM, (ii) the frequency of the zero fZ , (iii) the dominant highfrequency pole fH , and (iv) the gain-bandwidth of the amplifier.
Q.4: Consider a feedback amplifier with an open loop gain function
1000
A( s ) 
(1  s / 10 4 )(1  s / 10 5 ) 2
If the feedback factor β is independent of frequency, find
(i) The frequency at which the phase margin of the loop gain function A(s)  is zero
(i.e., the angle of A(s)  is 180 degrees).
(ii) The critical value of β at which oscillation will commence.
Q.5: The schematic below shows a typical two-stage CMOS Operational amplifier
circuit. The transistors M5, M6, M8 serve to provide the bias currents. The current ISS is
40 µA, and the bias current through the column M7,M91,M101,M8 is 20 µA. The small
signal gain of the common source stage (M7 transistor) is (approximately)
g m7  (r07 || r08 ). The small signal gain of the output buffer is 1.
M3
M7
M4
C
VDD
R
M91
vi1
M1
M2
vi 2
vout
M101
I SS
M5
M9
M10

M6
M8
VSS
Diff. Amp. Stage
Figure 5:
CS Amp.
Stage
Output
Buffer
M3, M4, M7, M10, M101 are PMOS, and M1,M2, M5, M6, M8, M91, M9 are NMOS
transistors.
Given
K
(PMOS)=30
µA/V2,
K
(NMOS)=100
µA/V2,
VA ( PMOS )  30 V , VA ( NMOS )  20 V , and the dimensions of the pertinent transistors
as below
Transistor
L (µm)
W(µm)
M1
5
15
M2
5
15
M3
5
50
M4
5
50
M7
5
50
M8
5
15
Calculate the voltage gain vout/vid of the Operational amplifier, where vid =vi1 –vi2.
Q.6: The schematic below presents the input stage of a wide-band trans-impedance
amplifier using CMOS transistors.
VDD
I REF
VDD
M3
VG
Io

ii
vo
M2
M1
V SS
Figure 6:
Using the high frequency ac equivalent circuit model for the MOS transistors,
find an expression for the gain vo/ii
Q.7: Consider the single stage BJT amplifier below with a shunt-shunt negative feedback
applied via RF= 82 kΩ. The bias current is IC = 0.5 mA, and all C = infinity. Further,
hfe=99, VBE(ON) =0.7 V, and VA = infinity.
Some Useful Formulae
MOSFETs (Saturation region):
g m  2k WI D L , ro  V A / I D ,   1 / V A
BJTs:
g m  I C / VT , VT  25 mV , r  h fe / g m , h fe  ic / ib , ro  V A / I C
10V
10 k
51k
C
RF
10 k
vo
C
Q
Rsig
vsig


5.5 k
500 
C
Figure 7:
Modeling the source terminal vsig, Rsig by it’s Norton equivalent, draw the loaded
amplifier circuit under feedback. Now find the gain vo/vsig of the amplifier with feedback.
Two-port network models
Feedback
Connection
(In – Out)
Series-shunt
Network model
name
Equation model
Hybrid-h
h11I1 +h12 V2 = V1
h21 I1 +h22 V2 =I2
Equivalent circuit model
I1
I2
h11
+
+
V1
h12 V 2
h22
h21I 1
_
Shunt-series
Hybrid-g
g11V1 + g12 I2 = I1
g21V1 +g22I2 = V2
V2
_
I1
I2
g22
+
V1 g11
+
V2
g21V1
_
_
g12I2
Seriesseries
Impedance
parameters
z11 I1 +z12 I2 = V1
z21 I1 + z22 I2 =V2
I1
I2
z11
z22
+
V1
-
+
V2
z12*I2
z21*I1
-
Shunt-shunt
Admittance
parameters
y11V1 +y12 V2 =I1
y21 V1 + y22 V2 =I2
I
I
1
+
V
1
-
2
+
y
11
y
y V
2
12
y V
1
21
22
V
2
-