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Application Report SLEA038 – July 2004 Implementation of Power Supply Volume Control Tomas Bruunshuus Texas Instruments Copenhagen ABSTRACT This document gives design guide lines for applications using the power supply volume control (PSVC). The power supply volume control increases system performance by: • Volume can be decreased without loss of audio resolution, in the range where PSVC is active. • When supply voltage for PVDD is decreased, the noise voltage at the output decreases as well. The ratio between noise voltage and maximum RMS voltage (DNR) then increases. The user experiences better noise performance at usual listening levels. E.g. a system having 102 dB in DNR and a power supply range of 18 dB will have a SNR up to 120 dB. • Reduces power consumption and heat in the system at usual listening levels, thereby increasing the lifetime of the system. • Many EMI tests are performed at a reduced volume setting. FTC requires 1/8 of maximum output power equal to a volume setting of -9 dBFS. By use of the PSVC operating voltage during EMI, the test will be reduced giving reduced switching noise in the system. The PSVC is supported in Texas Instruments PWM processors like the TAS5508, which makes implementation easy. For other modulator types like the TAS5066 and TAS5076, the PSVC can also be implemented. However, on these devices all calculations and control must be handled by the micro controller. This document gives design guidelines, how to implement PSVC correctly for the TAS5508. To implement PSVC for other PWM processors like the TAS5066 and TAS5076, contact the Texas Instruments digital audio applications team. 1 SLEA038 Contents 1 Introduction .....................................................................................................................................3 1.1 PSVC Advantages.....................................................................................................................3 1.2 PSVC Concept ..........................................................................................................................3 2 General Structure............................................................................................................................5 2.1 Examples of Gain Settings ........................................................................................................7 2.1.1 Gain Setting Within the PSU Range..............................................................................7 2.1.2 Gain Setting Higher Than the PSU Range ....................................................................7 2.1.3 Gain Setting Lower Than the PSU Range.....................................................................7 2.2 Power Supply Control................................................................................................................8 2.3 TAS5508 PSVC PWM Output ...................................................................................................9 2.4 Programming the TAS5508 for PSVC.....................................................................................10 3 Power Supply Implementation.....................................................................................................12 3.1 TAS5508 0% Duty Cycle Handling..........................................................................................12 3.2 Power Supply Sink / Source....................................................................................................13 4 DC/DC Converter Application Example ......................................................................................15 4.1 Implementation........................................................................................................................15 References.............................................................................................................................................16 Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figures Digital and Power Supply Gain .........................................................................................4 Resulting Gain ....................................................................................................................4 Volume Calculation Flow Chart ........................................................................................6 Control of the Power Supply .............................................................................................8 PSVC PWM Pulse ...............................................................................................................9 Configuration Using PWM .................................................................................................9 PSVC Output of the TAS5508..........................................................................................10 PSVC With Saturation ......................................................................................................12 PSVC With Shutdown ......................................................................................................13 Basic Schematic for a Buck Converter ..........................................................................13 Buck Converter Using Synchronous Rectification .......................................................14 Use of a Bleeder Resistor to Sink Current.....................................................................14 Table 1. Table 2. Table 3. Tables System Control Register 1 (0x03) ...................................................................................10 PSVC Range Register (0xDF) ..........................................................................................11 General Control Register (0xE0) .....................................................................................11 2 Implementation of Power Supply Volume Control SLEA038 1 Introduction 1.1 PSVC Advantages Using a combination of digital gain and power supply to the control volume setting gives several advantages: • Volume can be decreased without loss of audio resolution, in the range where PSVC is active. • When supply voltage for PVDD is decreased, the noise voltage at the output decreases as well. The ratio between noise voltage and maximum RMS voltage (DNR) then increases. The user experiences better noises performance at usual listening levels. E.g. a system having 102 dB in DNR and a power supply range of 18 dB will have an SNR up to 120 dB. • Reduces power consumption and heat in the system at usual listening levels. Thereby increasing lifetime of the system. • Many EMI tests are performed at reduced volume setting. FTC requires 1/8 of maximum output power equal to a volume setting of -9 dBFS. By use of PSVC, the operating voltage during EMI test will be reduced, giving reduced switching noise in the system. With only a minimum extra complexity audio performance can be improved and EMI tests become easier to pass. 1.2 PSVC Concept Speaker output voltage can at be calculated as: VSPEAKER (t ) = d (t ) ⋅ VPSU Where d is the duty cycle that varies according to the audio signal and VPSU is the power supply voltage. From this equation it can be seen that the output volume can be controlled from either the duty cycle or the power supply voltage. Note that when the output volume level is calculated in dB, the following formula is used: VSPEAKER (dB) = d (dB ) + VPSU (dB) Using this formula it becomes easier to calculate total output volume. The concept pf PSVC is to have the power supply to control from 0 dBFS to e.g. -24 dBFS and then use digital gain to control volume above 0 dBFS and below -24 dBFS. The lower crossover point (e.g. -24 dBFS) can be selected differently depending on the power supply configuration. Implementation of Power Supply Volume Control 3 SLEA038 Digital & Power Supply Gain (dB) Power Supply Volume Control 30 20 10 0 -10 -20 -30 -40 -50 -60 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 Gain (dB) Digital Gain Figure 1. Power Supply Gain Digital and Power Supply Gain Figure 1 shows gain settings for both digital circuits and a power supply at different desired gains. The resulting gain (or volume level) is the two gains, digital and power supply gain, added together. This is shown in Figure 2 according to the previous formula. Power Supply Volume Control 60 Resulting Gain (dB) 40 20 0 -20 -40 -60 -80 -100 -80 -60 -40 -20 0 20 40 60 Desired Gain (dB) Digital Gain Figure 2. Power Supply Gain Digital Gain Resulting Gain The resulting gain is linear to the desired gain, where the power supply controls the gain from -24 dBFS to 0 dBFS. 4 Implementation of Power Supply Volume Control SLEA038 Note that minimum power supply gain (lower crossover point of -24 dBFS) must be selected different depending on the power supply capability, e.g. -18 dBFS or -12 dBFS. 2 General Structure To set the volume correctly, the volume setting must be split into a digital gain setting and a power supply gain setting. Care must be taken to get these calculations right. Especially the calculations at the two crossover points can cause non linear volume control if not done correctly. The TAS5508 automatically calculates settings for digital gain and power supply gain. A flow chart to calculate volume settings is shown in Figure 3. The principle is to set the power supply volume according to the channel having the highest volume setting and then recalculate gain setting for the digital circuits. The TAS5508 uses a sequence based on this flow chart to calculate gain settings for digital gain and power supply gain. Implementation of Power Supply Volume Control 5 SLEA038 Channel1_volume Channel2_volume . . Channel n_volume Find Channel with highest volume setting - channel_x Calculate PSU setting for channel_x Higher Is PSU setting within PSU range Lower Within range PSU_volume = 0 dB PSU_volume = min. dB Calculate digital gain as: Channel1_digital = Channel1_volume - PSU_volume Channel2_digital = Channel2_volume - PSU_volume . . Channel n_digital = Channel n_volume - PSU_volume Figure 3. 6 Volume Calculation Flow Chart Implementation of Power Supply Volume Control SLEA038 2.1 Examples of Gain Settings The following examples are for a three channel system. The power supply can be controlled from -18 dB to 0 dB. 2.1.1 Gain Setting Within the PSU Range System requirement settings: Channel1_volume = -14 dB Channel2_volume = -28 dB Channel3_volume = -22 dB Channel 1 is found to have the highest volume setting of -14 dB. The PSU_volume is then set to -14 dB. Digital gain is then calculated as: Channel1_digital = -14 dB – (-)14 dB = 0 dB Channel2_digital = -28 dB – (-)14 dB = -14 dB Channel3_digital = -22 dB – (-)14 dB = -8 dB 2.1.2 Gain Setting Higher Than the PSU Range System requirement settings: Channel1_volume = -14 dB Channel2_volume = 4 dB Channel3_volume = -22 dB Channel 2 is found to have the highest volume setting of +4 dB. The PSU_volume is then set to 0 dB, which is highest setting for the power supply. Digital gain is then calculated as: Channel1_digital = -14 dB – 0 dB = -14 dB Channel2_digital = 4 dB – 0 dB = 4 dB Channel3_digital = -22 dB – 0 dB = -22 dB 2.1.3 Gain Setting Lower Than the PSU Range System requirement settings: Channel1_volume = -28 dB Channel2_volume = -28 dB Implementation of Power Supply Volume Control 7 SLEA038 Channel3_volume = -22 dB Channel 3 is found to have the highest volume setting -22 dB. The PSU_volume is then set to -18 dB, which is lowest setting for the power supply. Digital gain is then calculated as: Channel1_digital = -28 dB – (-)18 dB = -10 dB Channel2_digital = -28 dB – (-)18 dB = -10 dB Channel3_digital = -22 dB – (-)18 dB = -4 dB 2.2 Power Supply Control The output voltage of the power supply PVDD is controlled by adjusting the reference voltage. The control loop in the power supply uses this reference voltage to regulate the output. When the reference voltage is changed, PVDD will change accordingly. PVDD Feed Back SMPS -1 DC reference Figure 4. Control of the Power Supply The reference voltage must be controlled from the TAS5508. If the reference voltage is an analog voltage that has to pass from the TAS5508 at the amplifier board to the power supply board, the output voltage of the power supply will be erroneous. The voltage may drop when crossing from one board to the next. This makes the volume setting inaccurate. Also, if noise or hum is injected into the reference voltage, this noise will be coupled into the power supply output and then into the speaker output. This is solved in the TAS5508 by using a PWM signal instead of an analog reference voltage. 8 Implementation of Power Supply Volume Control SLEA038 Lowest Power Supply Voltage Pulse Maximum Power Supply Voltage Pulse Figure 5. PSVC PWM Pulse The PSVC PWM pulse has a duty cycle corresponding to the power supply volume setting. The advantage is that all volume information is independent of the voltage level. This means that any voltage drop can be compensated by reclocking the PWM signal at the power supply board. PWM pulses are then converted to the analog reference voltage through a low-pass filter. PVDD Feed Back SMPS -1 Reference 100 nF Figure 6. 1 kΩ 10 kΩ PSVC PWM 1 uF 74LVC126 Configuration Using PWM The PSVC PWM frequency must be above 20 kHz to insure that no audible leftovers from PSVC PWM are coupled into the speaker outputs. 2.3 TAS5508 PSVC PWM Output When PSVC is enabled, the TAS5508 generates a PWM signal at a frequency of 44.1 kHz or 48 kHz. The PWM frequency is synchronized to the LRCLK of the I2S. Implementation of Power Supply Volume Control 9 SLEA038 Lowest Power Supply voltage Pulse > 120 out of 2048 Maximum Power Supply Voltage Pulse = 1944 out of 2048 Figure 7. PSVC Output of the TAS5508 The output has a maximum duty cycle of 95% corresponding to 0 dBFS and a minimum duty cycle of 6% corresponding to -24-dB attenuation. Note that during start up, error recovery, and reset the duty cycle is 0%, 0 V. This can be changed by programming system control register 1 (0x03). Table 1. D7 System Control Register 1 (0x03) D6 D5 D4 D3 D2 D1 D0 - - - - - - - PWM High Pass Disabled 1 - - - - - - - PWM High Pass Enabled - 0 - - - - - - /Auto Clock Set - 1 - - - - - - Manual Clock Set - - - 0 - - - Soft Unmute on Recovery from Clock Error 0 Function - - - 1 - - - Hard Unmute on Recovery from Clock Error - - - - 1 - - - PSVC Hi-Z Enable - - - - 0 - - - PSVC Hi-Z Disable 0 0 0 1 0 0 0 0 Default Setting D0 to D2 is unused bits. If D3 bit is set high, the PSVC output will go into Hi-Z during error recovery. This is however not recommended, since this interferes with the reclocking gate at the power supply board, causing PVDD voltage to be too high. For most applications, PSVC Hi-Z must remain disabled. The function of D4 to D7 is not covered in this document, see Reference 1. 2.4 Programming the TAS5508 for PSVC The TAS5508 modulator has a PWM output for the power supply control. This provides an easy implementation of the PSVC. The modulator does all calculations to get the correct volume setting and generates the PSVC PWM pulse required at a frequency of 44.1 kHz or 48 kHz, depending on the audio sample rate. 10 Implementation of Power Supply Volume Control SLEA038 The TAS5508 can be configured to provide PSVC with 12.04-dB, 18.06-dB, or 24.08-dB attenuation of the power supply. The attenuation level should be selected as high as possible. The limiting factor is that the power supply must remain stable at all power levels. Some power supplies can have difficulties when regulating over a wide voltage range. Hence, the PSVC range must be selected smaller. The PSVC control range is set in register 0xDF. Table 2. PSVC Range Register (0xDF) D31 – D2 D1 D0 Function 0 0 0 0 12.04-dB control range for PSVC 0 0 0 1 18.06-dB control range for PSVC 0 0 1 0 24.08-dB control range for PSVC 0 0 1 1 Ignore – retain last value 0 0 1 0 Default Setting Subwoofer configuration must be selected. In case that the subwoofer output is a line output, the digital volume setting is not to be affected when setting the power supply volume. This is done in register 0xE0. This register also enables/disables the PSVC. Table 3. D31 – D4 D3 General Control Register (0xE0) D2 D1 - 0 /8 Channel Configuration 0 - 1 6 Channel configuration 0 0 - Power Supply Volume Control Disable 0 1 - Power Supply Volume Control Enable 0 D0 Function 0 0 - - Subwoofer Part of PSVC 0 1 - - Subwoofer Separate from PSVC 0 0 0 0 0 Default Setting The D1 bit is used to select between eight channel configuration and six channel configuration. This item is not covered in this document. The D2 bit is used to enable/disable PSVC. Default is disabled. When PSVC is disabled, the output of PSVC is 0. All volume control is performed using digital gain only. Enabling of the PSVC starts the PSVC PWM. The TAS5508 automatically calculates the volume setting for the power supply and digital volume for all channels based on the flow chart shown in Figure 3. If D3 is set to 1, the subwoofer channel (channel 8) is not included in the PSVC, only digital volume is used. This is needed if the subwoofer output is a line out (e.g. a 7.1 system using active subwoofer). Implementation of Power Supply Volume Control 11 SLEA038 3 Power Supply Implementation 3.1 TAS5508 0% Duty Cycle Handling As discussed in the previous section, the TAS5508 during start up and error recovery has a PSVC output of 0% duty cycle. The power supply must then be able to handle this situation properly. When the reference voltage to the power supply is 0 V, PVDD will also be 0 V if no special arrangements are made. NOTE: Texas Instruments power stages can handle PVDD being 0 V, since no audio is present during these events. Texas Instruments power stages does not need protection against PVDD = 0 V. However, the power supply must not be damaged nor become unregulated during these events. If the power supply cannot handle a 0-V output, the following arrangements can be made: PVDD Feed Back SMPS -1 Reference 100 nF Figure 8. 1 kΩ 10 kΩ PWM ref 1 uF 74LVC126 PSVC With Saturation Figure 8 shows a power supply implementation, where PVDD is kept at a minimum voltage when PWM is 0%. The voltage is set by a resistor divider and the forward drop of the diode. Another way of controlling 0% situation is to shut down the power supply when the duty cycle falls below a given level. This is shown in Figure 9. 12 Implementation of Power Supply Volume Control SLEA038 PVDD Feed Back SMPS -1 Reference 10 kΩ 1 kΩ 1 uF 100 nF PWM ref 74LVC126 /shutdown 74LVC126 10 nF Figure 9. 3.2 10 kΩ PSVC With Shutdown Power Supply Sink / Source Most power supplies are only capable of sourcing current. This is due to implementation of the rectifying circuit on output. In most cases, this is done by using a rectifying diode. Figure 10 shows basic components for a buck converter. The buck converter creates an output voltage (PVDD) lower than its input voltage (VI). It can be seen that current can only flow out of the converter due to the direction of the diode and since the input voltage is higher than the output voltage, no current can flow from the PVDD to VI. Decreasing of the output voltage can only happen by loading the output. Current Source VI PVDD Figure 10. Basic Schematic for a Buck Converter Implementation of Power Supply Volume Control 13 SLEA038 When using PSVC, this can cause a problem when ramping down volume. When the volume is ramped down, the PVDD voltage must decrease. If the power supply can only source current, only the amplifier load can decrease the PVDD voltage. This causes an uncontrolled ramp down of the volume. To make the power supply able to sink current as well, one of following solutions is recommended. Use of synchronous rectification. The basic theory is to replace the rectifying diode with a controlled MOSFET. A controlled MOSFET has the advantage to allow current in both directions when turned on. Actual implementation of a synchronous rectification depends on the power supply topology. Figure 11 shows an example of synchronous rectification for a buck converter. Current Sink/Source PVDD VI Figure 11. Buck Converter Using Synchronous Rectification Use of bleeder resistor. A resistor can be placed at the PVDD output to bleed down the output voltage. In order not to decrease efficiency, this resistor must be connected through a switch or a transistor. The bleeder resistor will then only be active when needed. Figure 12 shows how a controlled bleeder resistor can be used to decrease the output voltage. The bleeder resistor is turned on by the switch when the PVDD voltage is too high. Current Source VI PVDD Current Sink Figure 12. Use of a Bleeder Resistor to Sink Current 14 Implementation of Power Supply Volume Control SLEA038 4 DC/DC Converter Application Example The following application example is a dc/dc converter optimized for the full advantage of the TAS5508. The converter is designed for: 4.1 • Input voltage 50 V to 55 V • Output voltage 2 V to 40 V, giving the full 24.08-dB attenuation provided by the TAS5508 • Current limitation level set to 12 A Implementation The power supply is designed with the possibility to use remote voltage sensing, which improves audio performance, see Reference 2. The output voltage is sensed through a separate connector J704 pin 2. The voltage can then be sensed at the amplifier board eliminating impedances in wires and connectors. For using the PSVC, a jumper must be placed at J703 between pin 1 and pin 2. If a manual voltage setting is required, the jumper must be placed between pin 2 and pin 3. The PWM input for power supply control from the TAS5508 is at J703 pin 5. The input has a pulldown resistor, R827, to insure that the output voltage drops to 0 V in case of loss of PWM input. To restore the PWM signal and adapt it to the power supply reference voltage, the PWM input is reclocked in an AND-gate, U703. This removes voltage drops and noise that might have been injected in the transmission from the modulator to the power supply. Converting the PWM signal level to the power supply reference voltage improves the accuracy of the output voltage. The converter itself is a BUCK topology. Basic components can be identified as: C708, C710, C711, and C712 as the input capacitor, Q706 and Q707, L704 and C725 plus capacitors at the amplifier board as the output capacitor. U706 is an integrated power supply controller. Synchronous rectification is used in this application. Q707 is the synchronous rectifier instead of a diode. The dc/dc converter is then capable of transferring current from output side to the input side. Since the dc/dc converter can be supplied from a rectified transformer output, there must be a bleeder at the primary side, to be able to sink current. The bleeder resistor is R707 and is controlled by Q701. Q701 is turned on by U701C, if the input voltage exceeds 65 V. Implementation of Power Supply Volume Control 15 SLEA038 References 1. TAS5508 – 8 Channel Digital Audio PWM Processor (SLES091) 2. Power Supply Considerations for A/V Receivers (SLEA028) 16 Implementation of Power Supply Volume Control 4 3 No.: 49 PSU Input voltage filter 2 No.: 47 PSU Power stage L701 1u VIN VIN 1 2 VIN-POS J701 C707 10n C706 100n C711 1000u C712 1000u R713 20k 1 VIN-RTN C704 10n R714 10k Q703 C718 2 R717 0 1 0 + C780 47u 0 C782 100n connector4 C722 100n 0 C724 10n R726 R696 2R7 R727 2R7 2R7 R695 2R7 L704 57uH / T131-8/90 3 R697 20k Q712 2 1 2 C728 NU R728 R729 NU 0R018 C725 1000u 4 C727 10n 1 C726 100n 2 3 +12V Q705 VIN-RTN 0 B 4 +5V J706 connector4 -I-sense 2 0 R731 10R +I-sense R730 0R018 3 1 1 47k R719 47k C723 10n 3 Q707 IRF540 R725 0R 220n C721 0 R716 +5V + C783 47u RUN 0 R724 HIP2100 C720 22p connector4 J707 +VPWR Q706 IRF540 3R3 U702 Vdd 1 HB 2 HO 3 HS 4 8 LO 7 Vss 6 LI 5 HI R718 10k 100R 0 4 C719 22p 2 22p R715 PSU-PWM C781 100n Q704 3 1 20k 0 2 3 C717 22p R721 4k7 3 +12V J705 B 75nH + L702 1u R702 10R R720 4k7 R722 20k 1 2VIN-NEG C703 100n L703 3R3 + C710 1000u + C708 1000u + C705 1000u + + C702 10n R700 10R 0 J702 R723 +12V R701 10R C701 100n 1 0 0 0 0 0 No.: 48 PSU Input voltage bleeder No.: 46 PSU Controler 3 1 BAV70 VIN +12V +V-sense 2 D708 R821 120k R820 +5VREF C745 R751 5k6 0 R752 5k6 100k 12 VIN-RTN C715 47u R709 100k V+ C716 100n + LM339 Q701 IRF540 10 - 0 VIN-OV 13 U706 24 SHARE 12 0 PSU-PWM 0 0 0 +12V R745 +5VREF No.: 44 Temperature detector for PSU R794 +12V 82k R801 3k A R798 33k R795 1 +12V U701A 5 + V+ V- 4 LM339 12 R797 100R +12V CA- 6 18 GND CAO 7 17 OUT CS+ 8 16 VCC CS- 9 15 RUN CSO 10 14 VREF ENBL 11 13 KILL SEQ 12 CAC749 22p 100R R823 100R R747 27k R748 8k2 C750 4n7 0 0 R750 C755 82R 0 VOLUME R757 C754 10u 0 0 R758 510R CS+ +I-sense CSR749 3k3 R760 5k6 C756 220p 0 R761 8k2 0 C758 220n R759 510R -I-sense +5VREF R762 1k5 0 A C784 100n 0 R793 10k 3 1 TP-PSU VOLUME V12 TITLE R825 2k DC/DC converter POT R826 10k 2-40V max 12A SIZE DWG NO 0 A3 SCALE NONE 3 Confidential All rights belongs to Texas Instruments Inc. Texas Instruments Denmark A/S 0 J703 0 4 100p 1k5 R756 27k R763 C753 10u 0 C751 220p R822 C752 100n TBLK-A/B/C/G Y 4 1 R800 30k 10k VAO +5VREF 3 GND 2 R802 33k NTC 0 4k7 3 C779 10n 19 VEE 1 2 3 6 LM339 0 2B +5VREF V+ 1k D705 BAV70 0 U703 5 1A VCC 100n R827 U701B 7 + 2 +VPWR 0 82k 0 C778 R796 R799 10k VIN-OV TW-PSU 2 0 R753 1k0 R746 270k VA+ 4 VAO 5 C744 100n 0 C748 1n J704 5_pol_pow 11 22 33 44 55 R824 R792 10k 3 1k TP-PSU 0 C746 VA100p C747 22p +V-sense D710 +5VREF 5k6 C743 100n No.: 45 Remote sense, voltage control VA- 3 RT 7k5 20 CLKSYN R744 510R 100n ADJ 1 ILIM 2 R743 21 VU701D LM339 UC3849DW 23 OSC R742 100R22 RDEAD + V- 8 - 1nF 3 11 + 3 R708 10k C741 0 + C713 220p R699 2k7 R712 10k 1 V+ R704 10k C714 100n 14 R711 470k 2 +5VREF 1k8 2 3 R710 8k2 D701 BAV70 1 3 9 + R707 82R 1 U701C R706 2k7 R755 1k0 D704 BAV70 3 +12V R705 220k R703 120k R754 2 RUN R698 8k2 VIN 2 A706-SCH-001 2004-05-23 1 SHEET REV 1.0 1 OF 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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