Download A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18

230
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-m CMOS
Yalcin Alper Eken, Student Member, IEEE, and John P. Uyemura, Senior Member, IEEE
Abstract—This paper presents the design of three- and
nine-stage voltage-controlled ring oscillators that were fabricated
in TSMC 0.18- m CMOS technology with oscillation frequencies
up to 5.9 GHz. The circuits use a multiple-pass loop architecture
and delay stages with cross-coupled FETs to aid in the switching
speed and to improve the noise parameters. Measurements show
that the oscillators have linear frequency-voltage characteristics
over a wide tuning range, with the three- and nine-stage rings
resulting in frequency ranges of 5.16–5.93 GHz and 1.1–1.86 GHz,
respectively. The measured phase noise of the nine-stage ring
oscillator was 105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz
center frequency, whereas the value for the three-stage ring
oscillator was simulated to be 99.5 dBc/Hz at a 1-MHz offset
from a 5.79-GHz center frequency.
Index Terms—CMOS, LC oscillators, multiple-pass architecture, phase-locked loop (PLL), phase noise, ring oscillators, VLSI,
voltage-controlled oscillators (VCOs).
I. INTRODUCTION
T
HE phase-locked loop (PLL) is a critical component in
many high-speed systems as it provides the timing basis
for functions such as clock control, data recovery, and synchronization. The voltage-controlled-oscillator (VCO) is perhaps the
most crucial element of the PLL because it directly provides
the output signal of the PLL. A CMOS VCO can be built using
ring structures, relaxation circuits, or an LC resonant circuit. The
LC design has the best noise and frequency performance owing
to the large quality factor Q achievable with resonant networks
[1]. However, adding high-quality inductors to a CMOS process
flow increases the cost and complexity of the chip, and also introduces problems such as the control of eddy currents.
Ring oscillators, on the other hand, can be built in any
standard CMOS process and may require less die area than LC
designs. The design is straightforward, and ring architectures
can be used to provide multiple output phases and wide tuning
ranges. In this brief, we present a design that improves the
overall characteristics of CMOS ring oscillators to be comparable to those of LC designs. The prototype circuits were
implemented in a standard TSMC 0.18- m non-epi CMOS
process, and achieved maximum oscillation frequencies up to
5.9 GHz with linear frequency–voltage characteristics. The
architecture of multiple-pass ring oscillators and the use of
saturated gain stages to increase the frequency and voltage
swing at the output are examined in Section II. Details of the
design and measurement of the prototype circuits are presented
Manuscript received November 21, 2002; revised July 24, 2003. This work
was supported by Integrated Device Technology, Inc.
The authors are with the School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332-0250 USA (e-mail:
[email protected]).
Digital Object Identifier 10.1109/JSSC.2003.820869
Fig. 1.
N -stage multiple-pass ring oscillator.
in Section III, along with a comparison of the results with other
published circuits.
II. MULTIPLE-PASS RING OSCILLATORS
WITH SATURATED STAGES
Because of the frequency limitations of a single-loop ring
oscillator, other architectural techniques are necessary to explore the maximum frequency levels of ring oscillators. Some
of these techniques include the use of subfeedback loops [2],
output-interpolation methods [3], multiple-feedback loops [4],
and dual-delay paths [5], [6].
The multiple-pass loop architecture, which is shown in Fig. 1
for an -stage ring, is the basic architecture chosen in this work.
This technique adds auxiliary feedforward loops that work in
conjunction with the main loop. The main idea is to reduce
the delay of the stages below the smallest delay that is possible inside a simple ring oscillator loop. This is achieved by
and
, to every stage
adding a set of secondary inputs,
and switching these earlier than the primary inputs during the
operation. Although the illustration is for an oscillator with an
odd number of stages with the feedforward loops passing over
a single stage, other configurations are possible to obtain a different frequency increase or decrease.
It is important to note that the majority of the frequency-increase techniques discussed above [2], [4]–[6] depends on the
use of intercoupled feedback loops to increase the maximum
frequency, similar to the multiple-pass loop architecture used
in this work. Basically, all of these methods are fundamentally
same and they are based on a one-dimensional variation of the
coupled-oscillator structure introduced in [7] and discussed as
the look-ahead ring oscillator in [8].
Changing the architecture increases the oscillation frequency,
but phase noise and jitter are also important considerations.
Many ring oscillators use analog gain stages, but biasing
the transistors into continuous conduction increases their
contribution to the total noise. To overcome this problem, the
gain transistors can be periodically switched in and out of
0018-9200/04$20.00 © 2004 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
231
Fig. 2. Saturated gain stage with cross-coupled PMOS transistors.
conduction, which reduces the noise. The reduction of the noise
by switching is shown by [5] as
(1)
where
is the output noise power of the oscilis the output
lator that incorporates switching,
is the conducting
noise power if there was no switching, and
time of the transistors in a period . Another problem with
using standard gain stages is the output signal amplitudes that
are much smaller than rail-to-rail values. Larger signal levels
correspond to better noise performance because the noise performance of a system is expressed by using signal-to-noise-ratio
(SNR) values instead of the absolute noise power values. These
imply that the best characteristics are obtained with a full-rail
output signal.
A design that provides both of these characteristics is the saturated gain stage with regenerative cross-coupled PMOS transistors as shown in Fig. 2 [5]. This provides for rail-to-rail output
signals and full switching of the FETs in the stage. From a qualitative viewpoint, it can be seen that the feedback properties of
the latching transistors M1 and M2 speed up the signal transitions at the output. This improves both the oscillation frequency
and the noise performance of the VCO. The stage also avoids
the use of cascode connections and a tail current-source transistor that would limit the signal swing and add more noise to
the output.
III. PROTOTYPE OSCILLATOR DESIGNS
A primary goal of the research was to explore the maximum
frequency limitations and noise performance levels of ring
VCOs built in a standard CMOS process. To this end, threeand nine-stage multiple-pass ring oscillators were designed
and fabricated using a non-epi TSMC 0.18- m CMOS process
V. The circuits were
with a power supply value of
designed with MOSIS SCMOS rules that required a minimum
drawn channel length of 0.20 m. The test chip also included
other circuits such as an integrated LC oscillator, charge pump
prototypes, and phase-frequency detector networks, but these
are not discussed in this brief.
The prototype oscillators employ the saturated stage design
given in Fig. 2 with the transistor ratios provided on the figure.
The delay of the stage, and thus, the VCO frequency, is con-
Fig. 3. Frequency–voltage characteristics of (a) the three- and (b) the ninestage ring oscillator.
trolled by altering the strength of the latch using the control terthat is connected to the NMOS switches M3 and
minal
M4. Higher control voltages result in a stronger coupling between M1 and M2, making it more difficult to switch the output
voltage, and hence decreasing the frequency. Hwang [9] uses a
similar method to control the VCO frequency. Two pairs of inputs are used to adapt the stage to a multiple-pass architecture.
To ease the requirements on the needed testing equipment,
high-speed current-mode-logic (CML) buffers and frequency
dividers were used to divide the frequency of the oscillators
from 1/2 to 1/64 of their actual value. The output of the divider
circuits is then fed to a high-speed driver chain to the output
pads for measurement.
The performance of the three-stage multiple-pass design
was simulated and measured with the results given in Fig. 3(a).
Spectre simulations of the oscillator predicted an operation
range of 5.18–6.11 GHz for control voltages of 0.3–1.8 V. The
measured silicon output was from 5.16 GHz up to 5.93 GHz,
indicating a maximum difference of 3.7% with the simulations.
The peaking of the simulated characteristics is attributed to
the limitations of the simulator tool in the subthreshold region.
Removing test circuitry and reducing the drawn channel length
to 0.18 m predicts a maximum oscillation frequency of
7.7 GHz as shown in the plot.
The nine-stage multiple-pass ring oscillator employed the
same gain stage as that used in the three-stage design. The frequency–voltage curves shown in Fig. 3(b) were extracted from
232
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 5. Maximum frequencies versus minimum channel length.
Fig. 4. (a) Phase noise of the three- and nine-stage ring oscillators extracted
from Spectre RF simulations. (b) Power spectrum at the divide-by-two output
of the nine-stage oscillator.
simulations and measurements and show good agreement with
a maximum difference of 4%. When the control voltages were
varied between 0.3 and 1.8 V, the measured and the simulated
frequency ranges were 1.1–1.86 GHz and 1.16–1.93 GHz,
respectively. It should be noted that the frequency range of
a multiple-pass architecture does not scale linearly with the
number of stages.
The phase noise values were estimated using SpectreRF
simulations and the published techniques that apply to this type of
stage design. As illustrated in Fig. 4(a), simulations predicted the
phase noise of the three-stage design as 99.5 dBc/Hz at a 1-MHz
offset from a 5.79-GHz center frequency, whereas the value for
the nine-stage design was 112.84 dBc/Hz at a 1-MHz offset
from a 1.82-GHz center frequency. Simulations also showed that
the dividers and buffers have negligible contribution to the output
phase noise. Dai’s equation [10] gives the single-sideband phase
noise for oscillators with clipped signals as
where
(2)
where
is the single-sideband phase noise, is the excess
noise factor,
is the maximum output slew rate,
is the
angular frequency offset from the center frequency
is
Fig. 6.
Phase noise versus minimum channel length.
the thermal energy,
is the power supply voltage, and is the
equivalent output resistance of a delay cell. Using this equation,
the phase noise of the three- and nine-stage multiple-pass ring
oscillators was calculated to be 95.05 dBc/Hz and 120.99
dBc/Hz, respectively, at the same offset and center frequencies
as given in the simulation results. The large difference for the
nine-stage design is accounted to the additional noise sources
because of the increase in the number of stages. This could
be compensated by using a larger excess noise factor in the
equations.
Fig. 4(b) shows the measured power spectrum at the divide-by-two output of the nine-stage design. The phase noise
of the nine-stage design was extracted as 105.5 dBc/Hz at
a 1-MHz offset from a 1.81-GHz center frequency; this value
accounts for the bandwidth of the input low-pass filter of
the spectrum analyzer and the division factor. Supply/ground
disturbances and flicker noise sources, which were ignored in
the calculations and simulations, are considered to be the main
sources of the difference between the measurements and the
estimations.
In an effort to compare the oscillators’ performance, two
scatter plots were created using designs published in the open
literature. Fig. 5 shows the maximum oscillator frequency as
a function of the minimum CMOS feature size, and Fig. 6
provides information on the phase noise. The points were
measured, calculated/simulated, or taken from the referenced
papers. To provide consistency in the comparison, phase noise
data from the papers were scaled to a 1-MHz offset from the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
center frequencies with an assumed 20-dB/decade drop. The
maximum frequency values for circuits with the present design
were obtained from Spectre/HSPICE simulations, with the
exception of the measured values cited for the 0.18- m points.
The simulation results showed that the three-stage circuit is
capable of oscillation frequencies up to 4.5 and 12 GHz in
0.25- m and 0.13- m processes, respectively.
IV. CONCLUSION
We have demonstrated the use of a multiple-pass loop ring
oscillator architecture with latching saturated gain stages as a
technique for achieving high-frequency CMOS VCO circuits.
The performance curves show that the design can be extrapolated to other processes with good results. The attractive features of this approach are the simplicity of the design and the
fact that rings can be implemented in any CMOS process. The
results of this study suggest that it is not always necessary to
resort to integrated LC networks for high-frequency VCO/CCO
modules, but that simpler ring designs may suffice.
ACKNOWLEDGMENT
The authors would like to thank B. Butka, D. McDonagh,
P. Murtagh, and P. Platt of the IDT Atlanta Design Center for
their help in the design and testing, and B. Terlemez of Georgia
Tech for his contributions to the chip project.
233
REFERENCES
[1] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. SolidState Circuits, vol. 31, pp. 331–343, Mar. 1996.
[2] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage
controlled ring oscillator based on three-stage subfeedback loops,” in
Proc. Int. Symp. Circuits and Systems, vol. 2, Orlando, FL, 1999, pp.
176–179.
[3] Y. Sugimoto and T. Ueno, “The design of a 1 V, 1 GHz CMOS VCO
circuit with in-phase and quadrature-phase outputs,” in Proc. Int. Symp.
Circuits and Systems, vol. 1, Hong Kong, 1997, pp. 269–272.
[4] D.-Y. Jeong, S.-H. Chai, W.-C. Song, and G.-H. Cho, “CMOS current-controlled oscillators using multiple-feedback loop architectures,”
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1997, pp.
386–387.
[5] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-m
CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 586–591, May
1999.
[6] S.-J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed-delay
scheme,” IEEE J. Solid-State Circuits, vol. 32, pp. 289–291, Feb.
1997.
[7] J. Maneatis and M. Horowitz, “Precise delay generation using coupled
transistors,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273–1282, Dec.
1993.
, “Multiple interconnected ring oscillator circuit,” U.S. Patent
[8]
5,475,344, Dec. 12, 1995.
[9] I.-C. Hwang and S.-M. Kang, “A self regulating VCO with supply sensitivity of <0.15%-delay/1%-supply,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, 2002, pp. 140–141.
[10] L. Dai and R. Harjani, “Design of low-phase-noise CMOS ring-oscillators,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 328–338, May 2002.