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Design and Implementation of a High-Performance Power Supply
Satisfying Energy Star Requirements
Po-Jung Tseng, Shih-Jen Cheng, Chung-Yi Lin, Shu-Wei Kuo, Yu-Kang Lo, and Huang-Jen Chiu
Department of Electronic Engineering, NTUST, Taiwan, ROC
Corresponding author: Yu-Kang Lo
Email: [email protected]
Add.: No.43, Sec.4, Keelung Road, Taipei, Taiwan, ROC
Keywords: SEPIC Power Factor Corrector, coupled
inductors, continuous conduction mode, transition mode,
series resonant converter.
Abstract
This paper presents a high-efficiency power supply topology.
The front stage is a power factor corrector (PFC) utilizing the
single-ended primary inductor converter (SEPIC) topology.
The presented SEPIC PFC is operated under continuous
conduction mode (CCM) with a transition-mode (TM) PFC
controller and coupled inductors. The input current waveform
remains continuous to reduce the size of the EMI filter and
increase power density. Due to the inherent voltage stepup/down features of the SEPIC PFC, the input voltage of the
post-stage half-bridge series resonant converter (HB-SRC)
can be decreased to reduce the voltage stresses on the power
switches. High efficiency and low cost can be achieved.
Circuit topologies and design considerations for the studied
high-performance power supply are analyzed and discussed in
detail. High-efficiency requirements for the Energy Star
standards can be satisfied.
The proposed topology can minimize the EMI filter and
increase the power density. Also the high efficiency
requirement listed in Energy Star can be met. It is verified by
the measured results of a laboratory prototype that meets the
power factor and efficiency requirements and reduces the
complexity of circuitry and number of components. This
power supply circuit features the advantages of high
efficiency, high power factor, simple topology, and low cost.
In the following section, some experimental results will be
given.
2 Operating Principles
Analysis of the SEPIC PFC
The control IC is L6561, which operates under TM
condition. Nevertheless, by utilizing coupled inductors, the
input current can be maintained continuous. The main
components of the PFC circuit are the coupled inductors L1
and L2 (with a turns ratio n smaller than 1), capacitors Cbus
and Co, an output diode Do, and a switch S. Fig. 1 shows the
presented coupled-inductor SEPIC PFC circuit. Some
important waveforms and conduction paths of each switching
mode are described in Fig. 2 and Figs. 3(a) to (c).
1 Introduction
The quality of a power supply has a direct influence on
the stability and safety of electronic products. Compared with
the conventional linear regulator, a switching power supply is
a better alternative for achieving high efficiency and small
size requirements. Regulations on energy use and power
quality have been set up in developed countries to meet the
standards of the International Electro-technical Commission
(IEC) [1] and Energy Star [2]. This paper utilizes the coupledinductor SEPIC PFC [3, 4] and a half-bridge series resonant
DC-DC converter [5-8], as seen in Fig. 1, to implement a high
performance switching power supply. The output voltage of
the SEPIC PFC is designed at 200V to reduce the voltage
stress on power devices. Both high efficiency and low cost
can be realized. With the utilization of coupled-inductors and
a transition mode (TM) control IC in the front-end PFC
circuit, a continuous input current can still be obtained. Thus
the power factor (PF) value can be raised.
Do
Cbus
Llk2
Iin
N2
Vbus
Llk1
Vin
S
Co
Lm
Vo
Lz
N1
Fig. 1 Coupled-inductor SEPIC PFC Circuit
Mode 1:
Switch S is turned on at t0. L2 is charged. The turns ratio
of the coupled inductors, n, is smaller than 1. L2 discharges.
The output diode Do is reversely biased. The output capacitor
Co supplies energy to the load. The voltage across Do is
VD  Vo  Vin
(1)
Mode 2:
Switch S is turned off at t1. As the voltage across S, Vs,
starts to raise, Do conducts. When Vs reaches Vo+Vin, the
switch current reaches zero. At this moment,
VS  Vo  Vin
(2)
The current of the output diode, IDo, begins to decrease
until IL2 reaches zero, which ends this mode.
Mode 3:
The switch is turned off. IL1 increases linearly, and IL2 is
negative. Do is still conducting until the sum of IL1 and IL2
reaches zero. Then the operation will return to Mode 1. Zerocurrent-switching (ZCS) characteristics on the output diode
and the switch can be fulfilled.
Fig.4 shows the equivalent circuit of the coupled
inductors, where Llk1 and Llk2 are leakage inductances, and LM
is the magnetizing inductance. The governing equations are
arranged as follows [3].
dI
dI (t)
(3)
V (t)  L  2  L  M
2
lk2
(4)
dI M (t) dI 2 1 dI1

 
dt
dt n dt
(5)
ILlk2
|ILlk2|+ILlk1
ILlk1
t0
t2
t1
IDr
t3
Fig. 2 Key Waveforms of the Coupled-inductor SEPIC PFC
N2
Vbus
Llk1
S
Co
Lm
(a)
dt
dI1 (t)
V1 (t)  Leq1 
dt
Llk2  Llk1  L M  Llk1  (1/n)2  L M  Llk2
Leq2 
Llk1  1/n  [(1/n)-1]  L M
Llk2  Llk1  L M  Llk1  (1/n) 2  L M  Llk2
Llk2 -[(1/n)-1]  LM
2
L M  Llk2
N2
Vbus
Llk1
Vin
S
Co
(b)
Llk2
Iin
(9)
N2
Vbus
Llk1
Vin
S
Co
Lm
(c)
Fig. 3 Conduction Paths of (a) Mode 1, (b) Mode 2, and (c) Mode 3
LIk2
+
I2
n:1
Ideally, by using the coupled-inductor SEPIC PFC, the
input inductance will be assumed indefinitely large to produce
zero ripple current.
LIk1
I1
+
IM
+
+
(13)
Vo
Lz
N1
2
(11)
Dr
Cbus
(8)
As long as the above conditions are met, the input
inductor ripple current of the proposed SEPIC PFC will be
zero. Equations (12) and (13) can then be simplified as
(12)
Leq2  L M  Llk2
Leq1  
Vo
Lz
N1
(7)
Under the same applied voltages
LM
n
L M  Llk2
Dr
Cbus
Llk2
Iin
Lm
Supposing that the secondary-side current is zero, then
voltage V1 can be written as V11.
LM
(10)
V  V 1  (1/n)  V 1  (1/n) 
V
1
Vo
Lz
N1
eq2
Leq1 
Dr
Cbus
Llk2
Iin
Vin
The following equations can be derived, taking into the
consideration that the same voltages are applied on the
inductors.
dI (t)
(6)
V (t)  L  2
1
IS
M
dt
dt
dI1 1
dI (t)
V1 (t)  Llk1 
  LM  M
dt n
dt
2
Vgs
1
V2
V2
LM
V1
1
V1
Fig. 4 Equivalent Circuit of Coupled Inductors
Analysis of the Half-bridge Series Resonant Converter
Fig.5 shows the basic topology of half-bridge series
resonant converter (HB-SRC) [5-8], Fig. 6 is the operating
principles diagram of HB-SRC. Main components in primary
side are Q1, Q2, resonant capacitor Cr, resonant inductor Lr
(the series combination of transformer leakage inductance and
extra-added inductor), while the secondary one includes
center-tapped transformer, rectifier diodes D3 and D4, filter
capacitor C2. Primary-side active switch Q1 and Q2 is driven
with complementary signals, and during these switching
durations, energy is transferred from primary to secondary
side, with the zero-voltage-switching (ZVS) characteristics
resulting from the resonance between switches’ parasitic
capacitances Coss1 and Coss2 with resonant inductor Lr
appearing in the dead-time of both switches. What makes this
topology different from two-capacitor symmetrical halfbridge converter is that the Cr here acts as DC-blocking
capacitor and resonant capacitor, and there will be a DC
voltage of Vin/2 on it.
The voltage stress of both switches is the input voltage,
while the voltage stress of output rectifier diodes will not be
high, thus it will be better to choose low voltage stress diodes
to decrease their conducting loss. Provided the ZVS
technique, the switching losses will be low, thus raising
circuit efficiency. For simpler analysis, two assumptions are
made:
1.
Output capacitor is extremely large, thus can be
assumed as voltage source.
2.
No loss on every component.
Cr
D1
Q1
C2
vLCrm
Ro
iLr
t
VDS1
t
VGS2
t
VDS2
t
iLr
t
t4 t5 t0
Fig. 6 Key Waveforms of the Half-bridge Series Resonant Converter.
(a).
First energy transfer phase (t0 < t < t1)
From Fig. 7(a), it is seen that during this mode, S2 is ON
and S1 is OFF. D3 conducts, and the energy is transferred
from input stage to the load. The first energy transfer
equivalent circuit is shown in fig. 7b, and from this circuit, ILr
and VCr can be formulated.
 V  nVo  v Cr (t 0 )
Lr i Lr (t 0 )  in
(14)
s
I Lr (s) 
1
sLr 
sCr
VCr (t 0 )
1
(15)
VCr (s) 
 I Lr (s) 
sCr
s
(14) and (15) can be changed by inverse-Laplace to become:
 Vin  nVo  v Cr (t 0 ) sin(ω
Z0
0
(t  t 0 ))
(16)
VCr (t)= Vin -nVo  - Vin -nVo -v Cr (t 0 ) cos(ω0 (t-t 0 ))+ZoiLr (0)sin(ω0 (t-t0 ))
(17)
where Z  Lr ， ω 
0
0
Cr
Lm
D2 Coss2
S12
D4
＋
VDS2
－
VGS2
(a)
Lr i Lr (t 0 )
sLr
vCr (t0 ) 1
sC r
s
nVo
s
iLr (s )
(b). First resonance phase (t1 < t < t2)
As seen from Fig. 8(a), in this duration S1 and S2 are
OFF, the current on resonant inductor Lr will still be
continuous, and will charge Coss2, meaning discharging Coss1,
until Coss2 voltage reaches Vin and Coss1 voltage reaches zero,
thus resulting in ZVS turn-on for the next conducting switch
S1. When the resonant current on the primary side is still
larger than the coupled current from secondary side, D 3 will
still be ON, and during this time the load current is supplied
by resonant inductor.
Fig. 8(b) is the equivalent circuit during this phase, so I Lr
and VCr can be obtained:
VGS1
i Lr (t)  i Lr (t 0 )cos(ω0 (t  t 0 )) 
＋
Vo
－
(b)
Fig. 7 (a) Conduction Path and (b) Equivalent Circuit during the First Energy
Transfer Interval.
Tr
Fig. 5 The Schematic of Half-bridge Series Resonant Converter.
t1 t2 t3
RL
VGS1
＋
Vin
－
Vin
s
Coss 2
t0
D3
Co
＋
VDS1
－
Vo
D4
C1
Q2
n:1:1
iLm
iLr
Vp
Lr
D2
Cr
Lr
Coss1
D3
n :1 :1
iLm
Coss1
Vin
D1
S1
1
Lr Cr
.
I Lr (s) 
Lr i Lr (t1 )+
 nVo  v Cr (t1 )
sLr 
s
1
1

sC sCr
(18)
VCr (s) 
V (t )
1
 I Lr (s)  Cr 1
sCr
s
(19)
i Lr (t)  i Lr (t1 )cos(ω1 (t  t1 )) 
-nVo -v Cr (t1 ) sin(ω (t  t ))
Z1
1
1
(20)
VCr (t)   nVo    nVo  v Cr (t1 ) cos(ω1 (t  t1 ))  Z1i Lr (t1 )sin(ω1 (t  t1 ))
(21)
where Z 
1
Lr ，
ω1 
 C//Cr 
1
，
L r  (C//Cr )
C=2Coss=2Coss1=2Coss2.
Coss of the switches is the function of Vds, and can be
formulated as:
V'oss
8
Coss  Cstary  C'oss
3
VDS
(22)
(b)
Fig. 9 (a) Conduction Path and (b) Equivalent Circuit during the
Commutation Interval.
where C’oss is the drain-to-source capacitance of switches
when Vds = V’oss, which can be referred from IC application
notes.
S1
D1
Cr
Lr
Coss1
＋
VDS1
－
n:1:1
D3
iLm
iLr
Co
RL
＋
Vo
－
Lm
VGS1
＋
Vin
－
D2 Coss2
S2
capacitor is
D4
＋
VDS2
－
VGS2
(a)
Lr iLr (t1 )
1
sCcoss1
1
sCcoss 2
Vin
s
Vin
s
vCr (t1 )
s
sLr
1
sC r
iLr (s )
nVo
s
(b)
Fig. 8 (a) Conduction Path and (b) Equivalent Circuit during the First
Resonant Interval.
(c).
Commutation phase (t2 < t < t3)
As seen from Fig. 9(a), S1 and S2 are OFF during this
phase, the current on Lr is still continuous, with the charging
of Coss2 and discharging of Coss1 have ended, simultaneously
making D1 to conduct. Input side does not transfer energy to
the secondary side, and the load current is supplied by output
capacitor. Fig. 9(b) is the equivalent circuit for this phase,
which then ILr anc VCr can be obtained:
I Lr (s) 
 VCr (t 2 )
s
1
1
sLr 

sC sCr
(Lr  Lm )i Lr (t 2 )+
enough to supply energy to the load. Fig. 10(b) is the
equivalent circuit for this phase, which then ILr and VCr can be
obtained:
nVo -v Cr (t 3 )
Lr i Lr (t 3 ) 
s
I Lr (s) 
1
sLr 
sCr
(27)
V (t )
1
VCr (s) 
 I Lr (s)  Cr 3
sCr
s
(28)
i Lr (t)  i Lr (t 3 )cos(ω3 (t  t 3 ))+
D1
Lr
Coss1
iLr
Cr
n:1:1
D3
iLm
Co
RL
＋
Vo
－
Lm
VGS1
＋
Vin
－
D2 Coss2
S2
(25)
n:1:1
D4
＋
VDS2
－
VGS2
(26)
(a)
VCr(t3)
s
1
sCr
Lr×iLr(t3)
sLr
ILr(s)
D3
iLm
＋
VDS1
－
))
where Z  Lr ， ω  1 .
3
3
Cr
L r Cr
＋
VDS1
－
 v Cr (t 2 )
sin(ω2 (t  t 2 ))
Z2
iLr
3
(30)
(24)
Cr
Lr
Coss1
3
Z3
vCr (t)  nVo  nVo  vCr (t 3 )cos(ω3 (t  t 3 ))  Z3i Lr (t 3 )sin(ω3 (t  t 3 ))
1
where Z  Lr  Lm ， ω 
.
2
2
Cr
(Lr +Lm )  Cr
D1
 nVo  v Cr (t 3 ) sin(ω (t  t
(29)
S1
v Cr (t)  v Cr (t 2 )cos(ω2 (t  t 2 ))  Z2i Lr (t 2 )sin(ω2 (t  t 2 ))
S1
1
1 , making this voltage high
Vin  i Lr 
2
2πfCr
(23)
1
V (t )
VCr (s) 
 I Lr (s)  Cr 2
sCr
s
i Lr (t)  i Lr (t 2 )cos(ω2 (t  t 2 ))+
(d). Second energy transfer phase (t3 < t < t4)
From Fig. 10(a), we can observe that S2 is OFF and S1 is
ON, with D4 is conducting, the voltage across resonant
Co
RL
nVo
s
＋
Vo
－
Lm
VGS1
＋
Vin
－
S2
D2 Coss2
(b)
Fig. 10 (a) Conduction Path and (b) Equivalent Circuit during the Second
Energy Transfer Interval.
D4
＋
VDS2
－
VGS2
(e).
(a)
( Lr  Lm )iLr (t2 ) sL
r
vCr (t2 )
s
1
sC r
iLr (s)
sLm
Second resonance phase (t4 < t < t5)
As seen in Fig. 11(a), S1 and S2 are OFF, the current on
Lr is still continuous, charging Coss1 and discharging Coss2,
until Coss1 voltage reaches Vin and Coss2 voltage reaches zero,
thus resulting in ZVS turn-on for the next conducting switch
S2. Fig. 11(b) is the equivalent circuit for this phase, which
then ILr and VCr can be obtained:
Lr i Lr (t 4 ) 
 nVo -v Cr (t 4 )
s
1
1
sLr 

sC sCr
V (t )
1
VCr (s) 
 I Lr (s)  Cr 4
sCr
s
I Lr (s) 
(32)
 nVo  v Cr (t 4 ) sin(ω
)) 
(34)
where Z 
4
Lr ，
1
，
ω4 
 C//Cr 
Lr (C//Cr )
C=2Coss，Coss=Coss1=Coss2.
S1
D1
Lr
Coss1
iLr
＋
VDS1
－
Cr
n:1:1
D3
iLm
Co
RL
＋
Vo
－
Lm
VGS1
＋
Vin
－
S2
F(K v ) 
Po  fs (1  K v_min )
e
(33)
4 (t  t 4 ))
Z4
v Cr (t)  nVo   nVo  v Cr (t 4 ) cos(ω4 (t  t 4 ))  Z4i Lr (t 4 )sin(ω1 (t  t 4 ))
i Lr (t)  i Lr (t 4 )cos(ω 4 (t  t 4
ac
1
sin(377  t)  sin(377  t)
(37)

dt
Tac 0 1  K v_min  sin  (377  t)
Le is defined the equivalent inductance of the parallel of
L1 and L2.
0.9  Vin_min  F(K v_min )
(38)
L 
T
(31)
D2 Coss2
I pk 
VGS2
Next, the capacitance Cp can be obtained from Ipk.
2
L I
1
(40)
Cp  e  pk 
15 2 Vo  2  Vin_min
HB-SRC parameters design
Transformer design and assembly, n calculation:
Vin
NP
n
 2
NS Vo
ma x
(a)
L r i Lr t 4 
1
sCcoss 2
1
sCcoss1
sL r
nVo
s
Vin
s
Vin
s
(b)
Fig. 11 (a) Conduction Path and (b) Equivalent Circuit during the Second
Resonant Interval.
Design of the Circuit Parameters
The specifications of the SEPIC PFC and HB-SRC
implemented in this paper are listed in Tables 1.
SEPIC PFC
85~265 Vrms
200 V
1.45 A
300 W
45 ~ 100 kHz
95 %
(41)
HB-SRC
DC 200 V
12 V
20 A
240 W
50 ~ 150 kHz
96 %
SEPIC PFC parameters design
The duty cycle of the switch can be derived from the
voltage gain.
Vo
D
(35)

Vin_ min 1  D
Kv is defined as the ratio between the input voltage and
the output voltage.
V
 2
(36)
K v  in_ min
Vo
From Eq. (36), a function F(Kv), that will influence the
PF value, can be calculated as
k  N  Ae  f
k  Bmax  A e  f
k value for square wave is 4, for sinusoidal wave is 4.4, Ae is
the effective flux area, Bmax is the flux density, f is the
switching frequency, and from Faraday’s law in equation
(42), the turns number of primary windings can be obtained
from input voltage Vin and above variables. On the
transformer design, if the turn number is larger than this
value, the saturation condition can be avoided. After the
transformer finished its assembly, use instrument to measure
its leakage inductance Lk, for the reference of resonant
inductor design, and then can be used to calculate resonant
capacitor along with the required resonant frequency. Because
Lr=Lk+Lr1, and leakage inductance is in series with the
resonant tank path, Lr minimum value is decided by L k.
1
1
1
(43)
fr 
Table 1. Circuit Parameters of the SEPIC PFC & HB-SRC.
Circuir
Input voltage
Output voltage
Maximum output current
Maximum output power
Switching frequency
Efficiency
(39)
0.9  2  K v_min  F(K v_min )
where Np is the primary winding turns, Ns is the secondary
winding turns.
Calculate the minimum primary winding turns Np:
Vin
E
(42)
B

 108  N 
 108
D4
＋
VDS2
－
VCr t 4  1
sCr
i Lr t 
s
0.9  Vin_min  F(K v_min )
2π Lr Cr
 Cr 
(2π  f r )2  Lr
 Cr 
(2π  f r )2  Lk
3 Experimental Results
Figs. 12(a) and 12(b) show the input voltage and current
of the proposed switching power supply at full load during
low-line and high-line inputs, respectively. Figs. 13(a) and
13(b) depict the inductor currents, including the input
inductor current, the output inductor current, and the
summation of both, at full load during low-line and high-line
inputs, respectively. Figs. 14(a) and 14(b) illustrate the
rectified input voltage, the input inductor current, and the
output inductor current at full-load during low-line and highline inputs, respectively. Fig. 15 shows the driving signal of
the switch, the input inductor current, and the output inductor
current. Fig. 16(a) to 16(d) show the waveforms of gate-tosource voltage signal for S2 and S1, and resonant inductor
current of HB-SRC at different load levels. Fig. 17 (a) and
17(b) show the waveforms of gate-to-source voltage signal
for S2 and S1, drain-to-source voltage signal for S2, and drainto-source voltage signal for S1 of HB-SRC at 50 % loading
and 100 % loading, respectively. It can be seen apparently
that both S1 and S2 achieve ZVS turn-on characteristics. Table
2 shows that the input PF and overall conversion efficiency
have met the requirements set by Energy Star Standards.
Input voltage: 200 V/div
Input voltage: 100 V/div
Input current: 5 A/div
Input current: 2 A/div
(a)
(b)
Fig. 12 Input Voltage and Input Current at Full Load with (a) Low-line Input,
and (b) High-line Input Conditions. (Time: 4 ms/div)
(c)
(d)
Fig. 13 Input Inductor Current (Ch2), Output Inductor Current (Ch3), and
Summation of Both Currents (ChM) at Full Load with (a) Low-line Input
(Ch2: 2 A/div, Ch3: 5 A/div, ChM: 5 A/div, Time: 10 μs/div), and (b) Highline Input Conditions (Ch2: 1 A/div, Ch3: 5 A/div, ChM: 5 A/div, Time: 4
μs/div).
(c)
(d)
Fig. 16 Gate-to-source Voltage Signal for S2 (Ch1) and S1 (Ch2), and
Resonant Inductor Current (Ch4) of HB-SRC at (a) 20 % Loading (Ch1: 10
V/div, Ch2: 10 V/div, Ch4: 1 A/div, Time: 4 μs/div), (b) 50 % Loading (Ch1:
10 V/div, Ch2: 10 V/div, Ch4: 2 A/div, Time: 4 μs/div), (c) 75 % Loading
(Ch1: 10 V/div, Ch2: 10 V/div, Ch4: 2 A/div, Time: 4 μs/div), and (d) 100 %
Loading (Ch1: 10 V/div, Ch2: 10 V/div, Ch4: 5 A/div, Time: 4 μs/div).
(a)
(b)
Fig. 17 Gate-to-source Voltage Signal for S2 (Ch1) and S1 (Ch2), Drain-tosource Voltage Signal for S2 (Ch3), and Drain-to-source Voltage Signal for
S1 (Ch4) of HB-SRC at (a) 50 % Loading and (b) 100 % Loading. (Ch1: 10
V/div, Ch2: 10 V/div, Ch3: 250 V/div, Ch4: 250 V/div, Time: 4 μs/div)
Table 2 Measured PF and Efficiency at Different Load Conditions.
110V Input
20%
50%
75%
100%
Efficiency
89.17%
89.96%
88.89%
88.01%
PF
0.978
0.995
0.997
0.993
220V Input
20%
50%
75%
100%
Efficiency
90.07%
91.2%
90.79%
90.10%
PF
0.901
0.935
0.972
0.976
4 Conclusion
(a)
(b)
Fig. 14 Rectified Input Voltage (Ch1), Input Inductor Current (Ch2) and
Output Inductor Current (Ch3) at Full Load with (a) Low-line Input (Ch1:
100 V/div, Ch2: 2 A/div, Ch3: 5 A/div, Time: 4 ms/div), and (b) High-line
Input Conditions (Ch1: 200 V/div, Ch2: 2 A/div, Ch3: 5 A/div, Time: 4
ms/div).
This paper studies a power supply that meets the power
factor and efficiency requirements in the Energy Star
Standards and reduces the complexity of circuitry and number
of components. The DC output voltage of the SEPIC PFC is
set at 200 V to supply the post-stage HB-SRC. The voltage
stress and switching loss are reduced, which improves the
overall efficiency. The proposed topology is verified by the
measured results of a laboratory prototype. This power supply
circuit features the advantages of high efficiency, high power
factor, simple topology, and low cost.
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Fig. 15 Gate Signal (Ch1), Input Inductor Current (Ch2), and Output Inductor
Current (Ch3) at Full Load Conditions. (Ch1: 20 V/div, Ch2: 2 A/div, Ch3: 5
A/div, Time: 10 μs/div)
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