Download 1 - Georgia Tech

ECE 2030
Section E
Exam III - Makeup
November 30th, 2010
1:35 pm 2:55 pm
1. The Georgia Tech Honor Code governs this examination.
2. There are 6 questions and 9 pages including two blank worksheets. Make sure you have all of them.
3. Please write/draw legibly. Use the work sheets for generating the solutions before providing the
final answer.
4. State any assumptions you feel you have to make or ask for clarification
5. Keep in mind it is difficult to give partial credit without written material. Please make sure you
document any partial solutions.
6. All problems are weighted equally. Plan your work!
7. The exam is 50 minutes.
Problem
1
2
3
4
5
6
Total
Max Points
10
10
10
10
10
10
60
Student Name: __________________________________
Student Number: ________________________________
Graded
1. Perform the following operations.
a. Perform the following signed operations. The numbers are represented in two’s complement
form. Identify the operations for which overflow occurs assuming they are 6 bit two’s
complement numbers.
101011
+ 111101
___________
Overflow? ____
011111
- 010001
________
Overflow? ____
b. Perform the addition of the following unsigned numbers and identify those operations for which
overflow occur assuming the number of bits available is the number of bits in the operands.
101011
+ 111101
___________
Overflow? ____
011111
+ 100001
________
Overflow? ____
2
2. The following questions relate to IEEE 754 format floating point numbers.
a. Provide the hexadecimal representation of the following base 10 quantities using single
precision.
1. –0.0
2. 1.0625
c. Assuming that we have 6 significant digits (including the implicit bit), does the following
calculation produce any error? If so what is the magnitude of the error?
1.001 x 2121 + 1.1 x 2128.
3
3.
Fill in the timing of A, B, C, & D. Assume all latches are initialized to 0.
4
4. Draw the state diagram and state transition table for a state machine that will have the following
behavior.
a. Takes as input a sequence of bits, one bit at a time (on each clock)
b. Recognizes the pattern 110
c. Resets to the initial state when the pattern is found
d. Outputs a value of 1 when the patter is recognized
e. How many flip flops will be required to implement this state machine?
5
5. Show the design of a 3-bit register that can perform the following operations - i) complements the
contents of the register, ii) shifts the contents right one bit position with zero fill, iii) initialize the
contents to 011, and iv) clear the contents. i.e., set to 0. Use any basic gates and building blocks. Define
the control signals necessary. Use the D flip flop below as a building block. Show the truth table for the
operation of this register, i.e., what the control signals mean.
D
Q
FF
Q
Φ1
Φ2
6
6. This question concerns counters.
a. Show the design of a toggle cell using a D flip flop and basic gates. It should include a toggle
̅̅̅̅̅̅).
enable (TE) and an active low clear (𝐶𝐿𝑅
b. Modify this toggle cell design to enable the load of a new value under the control of a write
enable (WE) signal. Show a 4-bit modulo 5 counter using this new toggle cell.
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8
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