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Department of Electrical and Computer Engineering
University of Minnesota
EE2301
Introduction to Logic Design
Fall 2008
L. L. Kinney
Discussion V Solutions
10/2-3: Review topics are number systems, negative number arithmetic, gate conversions and
minimization. Exam I is Tues. 10/7.
1.
Problem 1.4 from Roth.
(a) Convert 1457.1110 to hexadecimal. Round to two digits past the hexadecimal point.
(b) Convert your answer to binary and then to octal.
(c) Devise a scheme for converting hexadecimal directly to base 4. Convert the answer
to Part (a) to base 4.
(d) Convert DEC.A16 to decimal.
(a) 16)1457(1
16) 91(11 = B
16) 5(5
0
16(.11) = 1.76
16(.76) = 12.16
16(.16) = 2.56
1457.1110 = 5B1.1C16
(b) 5B1.1C16 = 101 1011 0001.0001 112 = 2661.078
(c) Each hex digit converts to two base 4 digits. 5B1.1C16 = 11 23 01.01 34
(d) DEC.A16 = [(13)(162) + (14)(161) + (12)(160) + (10)(16-1)]10 = 3564.62510
2.
Problem 1.7(a), (b) and (e) from Roth. (Note that (b) cannot be done for 1’s
complement.) Add the following numbers in binary using 2’s complement to represent
negative numbers. Use a word length of 6 bits (including sign) and indicate if overflow
occurs. Repeat using 1’s complement to represent negative numbers.
(a) 21 + 11
(b) (-14) + (-32)
(e) (-11) + (-21)
(a)
21
2’s
010101
1’s
010101
1
3.
+ 11
32
001011
100000
overflow
001011
100000
overflow
(b)
(-14)
+ (-32)
32
2’s
110010
100000
010010
overflow
1’s
110001
--------100000
overflow
(e)
(-11)
+ (-21)
32
2’s
110101
101011
100000
1’s
110100
101010
(1)011110
000001
011111
overflow
Assume there exists an implication ‘gate’ as shown below where z = x′ + y.
Convert the following two-level circuit consisting of implication ‘gates’ into a two-level
circuit containing just AND and OR gates. Only two gates are required. Assume the
inputs are available both uncomplemented and complemented. (Note: This can be done
using gate conversions without writing any switching algebra expressions.)
Convert implication ‘gate’ to OR with inverted on upper input:
2
Move inverter on upper input of output gate to output of preceding gate.
Convert the OR with an output inverter to an AND with input inverters.
Combine the two OR gates.
4.
Consider the 4-variable functions f(A, B, C, D) = Σ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15),
g(A, B, C, D) = Σ m(2, 3, 5, 6, 7, 10, 11, 14, 15) and h(A, B, C, D) = Σ m(6, 7, 8, 9, 13,
14, 15).
(a) Use Karnaugh maps to find the simplest SOP expressions for f, g and h. Are the
answers unique?
(b) How many NAND gates are required to implement f, g and h?
(c) If f, g and h are multiple outputs from the one circuit, is it possible to share gates
among the outputs? Show your derivation. (Hint: Consider non-minimal SOP
expressions for f, g and h; in particular consider f•g and f•h.)
(a) f = AB’+BD+B’C
g = C+A’BD
h = BC+AB’C’+ABD(or AC’D)
(b) five 2-input NANDs
five 3-input NANDs
3 inverters (if the inputs are not available complemented).
(c) f = B’C+AB’C+A’BD+ABD
g = C+A’BD
h = BC+AB’C’+ABD
Underlined products are shared with f.
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