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CS:APP Chapter 4 Computer Architecture Control Logic and Hardware Control Language Selected Slides from Randy Bryant, CMU CS:APP Overview of Logic Design Fundamental Hardware Requirements Communication How to get values from one place to another Computation Storage Bits are Our Friends Everything expressed in terms of values 0 and 1 Communication Low or high voltage on wire Computation Compute Boolean functions Storage Store bits of information –2– CS:APP Hardware Control Language (HCL) And a b Or out a b out = a && b Not out a out = a || b out out = !a Bit Equality Bit equal a HCL Expression eq b Generate 1 if a and b are equal Very simple hardware description language bool eq = (a&&b)||(!a&&!b) Boolean operations have syntax similar to C logical operations –3– We’ll use it to describe control logic for processors CS:APP Word Equality Word-Level Representation b31 Bit equal eq31 B = a31 b30 Bit equal A eq30 a30 HCL Representation Eq b1 Bit equal a0 –4– Bit equal bool Eq = (A == B) eq1 a1 b0 Eq eq0 32-bit word size HCL representation Equality operation Generates Boolean value CS:APP Bit-Level Multiplexor s Bit MUX HCL Expression bool out = (s&&a)||(!s&&b) b out a –5– Control signal s Data signals a and b Output a when s=1, b when s=0 CS:APP Word Multiplexor Word-Level Representation s s B b31 out31 a31 out30 a30 A int Out = [ s : A; 1 : B; ]; Select input word A or B depending on control signal s HCL representation Case expression b0 out0 –6– Out HCL Representation b30 a0 MUX Series of test : value pairs Output value for first successful test CS:APP HCL Word-Level Examples Minimum of 3 Words C B A MIN3 Min3 int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ]; Find minimum of three input words HCL case expression Final case guarantees match 4-Way Multiplexor s1 s0 D0 D1 D2 D3 –7– MUX4 Out4 int Out4 = [ !s1&&!s0: D0; !s1 : D1; !s0 : D2; 1 : D3; ]; Select one of 4 inputs based on two control bits HCL case expression Simplify tests by assuming sequential matching CS:APP Arithmetic Logic Unit 0 Y A X B 1 A L U Y A X+Y OF ZF CF X A L U B 2 Y A X-Y OF ZF CF X B 3 Y A L U A X&Y OF ZF CF X B A L U X^Y OF ZF CF Combinational logic Continuously responding to inputs Control signal selects function computed Corresponding to 4 arithmetic/logical operations in Y86 –8– Also computes values for condition codes CS:APP Registers Structure i7 D C Q+ o7 i6 D C Q+ o6 i5 D C Q+ o5 i4 D C Q+ o4 i3 D C Q+ o3 i2 D C Q+ o2 i1 D C Q+ o1 i0 D C Q+ o0 I O Clock Clock Stores word of data Different from program registers seen in assembly code –9– Collection of edge-triggered latches Loads input on rising edge of clock CS:APP Register Operation State = x Input = y Output = x x – 10 – State = y Rising clock Output = y y Stores data bits For most of time acts as barrier between input and output As clock rises, loads input CS:APP State Machine Example Comb. Logic 0 A L U 0 Out MUX In 1 Load Accumulator circuit Load or accumulate on each cycle Clock Clock Load In Out – 11 – x0 x1 x0 x0+x1 x2 x0+x1+x2 x3 x4 x3 x3+x4 x5 x3+x4+x5 CS:APP Random-Access Memory valA srcA A valW Register file Read ports valB srcB W dstW Write port B Clock Stores multiple words of memory Address input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Register identifier serves as address » ID 8 implies no read or write performed Multiple Ports Can read and/or write multiple words in one cycle – 12 – » Each has separate address and data input/output CS:APP Register File Timing Reading valA srcA x A valB srcB x Register file 2 After some delay B 2 Writing 2 Like register Update only as clock rises x valW Register file W Clock – 13 – Like combinational logic Output data generated based on input address dstW y 2 Rising clock 2 y valW Register file W dstW Clock CS:APP Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, … int: words A, B, C, … Does not specify word size---bytes, 32-bit words, … Statements – 14 – bool a = bool-expr ; int A = int-expr ; CS:APP HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a || b, !a Word Comparisons A == B, A != B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D } » Same as A == B || A == C || A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, … in sequence Return word expression A, B, C, … for first successful test – 15 – CS:APP Summary Computation Performed by combinational logic Computes Boolean functions Continuously reacts to input changes Storage Registers Hold single words Loaded as clock rises Random-access memories Hold multiple words Possible multiple read or write ports Read word when address input changes Write word as clock rises – 16 – CS:APP