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Experiment No.1
PN Junction Diode
Object:
To plot the characteristics curve of PN junction diode in Forward & Reverse bias.
Apparatus Required:
S.No. Apparatus
Specification
Required No.
1.
Bread Board
6*2 inch
01
2.
Voltmeter
0-10 volt D.C.
01
3.
Ammeter
0-100 mA.
01
4.
DC power supply
0-10 Volt
01
5.
Connection Wire
single wire
08-10
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CIRCUIT DIAGRAM:REVERSE BIAS & FORWARD BIAS:
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The Basic Diode Symbol and Static V-I Characteristics.
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THEORY:- This is a two terminal device consisting of a P-N junction formed either in Ge or
Si crystal. A P-N junction is illustrated in fig. shows P-type and N-type semiconductor pieces
before they are joined.
P-type material has a high concentration of holes and N-type material has a high concentration of
free electrons and hence there is a tendency of holes to diffuse over to N side and electrons to Pside. The process is known as diffusion.
VOLT-AMPERE CHARACTERISTICS OF P-N JUNCTION
Fig.shows the circuit arrangement for drawing the volt-ampere characteristics of a P-N junction
diode.when no external voltage is applied the circuit current is zero. The characteristics are
studied under the following two heads:
(i) Forward bias
(ii) Reverse bias
(i)Forward bias:- For the forward bias of a P-N junction, P-type is connected to the
positive terminal while the N-type is connected to the negative terminal of a battery.The
potential at P-N junction can be varied with the help of potential divider. At some forward
voltage (0.3 V for Ge and 0.7V for Si) the potential barrier is altogether eliminated and
current starts flowing. This voltage is known as threshold voltage(Vth) or cut in voltage or
knee voltage .It is practically same as barrier voltage VB. For V<Vth, the current flow is
negligible. As the forward applied voltage increases beyond threshold voltage, the forward
current rises exponentially.
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(ii)Reverse bias: - For the reverse bias of p-n junction, P-type is connected to the negative
terminal while N-type is connected to the positive terminal of a battery.
Under normal reverse voltage, a very little reverse current flows through a P-N junction. But
when the reverse voltage is increased, a point is reached when the junction break down with
sudden rise in reverse current. The critical value of the voltage is known as break down
(VBR). The break down voltage is defined as the reverse voltage at which P-N junction
breakdown with sudden rise in reverse current.
Observation table:
Forward BiasS.No.
Forward voltage Vf (volt)
Forward Current If( mA)
Forward voltage Vf (volt)
Forward Current If( μA)
Reverse BiasS.No
Result:
The V-I characteristics of junction diode in forward and reverse bias condition has been be
plotted on the graph
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Experiment No. -1
Object :
Study RC coupled amplifier and plot the frequency response.
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
1.
RC Coupled Amplifier Trainer kit
ETB-45
01
2.
Cathode Ray Oscilloscope
30 MHz
01
3.
Function Generator
30 MHz
01
4.
BNC Cable
75 Ω
03
5.
Patch Chords
Banana Pin
05
Theory:
(a)
Frequency Response: The voltage gain of amplifier base varies with frequency the curve
between voltage gain and signal frequency of an amplifier is known as frequency response.
The gain of the amplifier increases from 0 till it became maximum at Fr called resonance
frequency is the frequency increases beyond fr the gain decreased.
(b)
Bandwidth : The range of the frequency over with the gain is equal to or greater than 70.7%
of the maximum gain is known as bandwidth from the figure it is clear that f1 – f2 is
bandwidth f1 is the lower cutoff frequency and f2 is the higher cutoff frequency. The
frequency f1 and f2 is also called 3DB frequency or half power frequency.
R – C Coupled Amplifier:
It is the most popular type of coupling dives use for the voltage amplification in figure it is seems
that a coupling capacitor Cc is used to connect the output of the first stage to the input of the second
stage. Resistance R1, R2 and RE used for the biasing and stability.
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When an AC signal i9s apply to the bias of the first transistor it amplify across the load RC this
amplified signal is faid to the bias of the second stage through CC in this way we get the overall signal
increase at the output of the second stage.
Frequency Response of RC Coupled Amplifier:
(i)
At the lower frequency (<50 Hz) the reactance of CC is very high hence very small part of the
signal will pass from one stage to another stage.
(ii)
At high frequency (>20 kHz) the reactance of CC is very small and it behave the short circuit
thus because of the loading effect reduce the voltage gain.
(iii)
At mid frequency (50 to 20 KHz) the voltage gain of amplifier is constant the effect of the CC
in this frequency range is such as to mention uniforms voltage gain.
Procedure :
(1)
Take the frequency response of the individual stage.
(2)
Measure the output of the first stage at point A.
(3)
Measure the output of the second stage at point B.
(4)
Draw the frequency response of the R – C coupled amplifier.
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Observation Table :
S.No.
Fin (Hz)
Vin (Volts)
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Vout (Volts)
Gain (dB) = 20 log10 (Vout/Vin)
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Experiment No.
Transistor Characteristics
Object:
To study and plot the Transistor input and output characteristics in the following configurations:
(a)
Common Emitter Mode
(b)
Common Base Mode
(c)
Common Collect Mode
Features:
The board consists of the following built-in parts:
1.
Two 0-10V D.C at 200mA, continuously variable power supplies for Baes Emitter and Collector
Emitter functions.
2.
Two D.C Ammeters, 65mm rectangular dial with switch selectable ranges of 200µA & 10mA.
3.
Two D.C Voltmeters, 65mm rectangle dial with switch selectable ranges of 1V and 10V.
4.
Two Silicon (NPN &PNP) transistors and two Germanium (NPN &PNP) transistors.
5.
Adequate no. of other electronic components.
Theory:
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The construction of a transistor is best understood by two diode analogy where two diode are
connected back to back as shown in fig.1 (A) and fig.2 (A). A PNP transistor analogous to two diodes with
their cathodes (N-Type ) connected together to form its base terminal see fig.1(a).An NPN transistor is
analogous to two diodes with their anodes (P-type) connected together to form its base terminal, see
fig.2(A) The remaining two terminals are collector and emitter. Fig.1 (B) and fig.2 (B) show the
diagrammatic form of PNP and NPN transistor. The circuit symbols of PNP and NPN transistor are shows
respectively in fig.1(c) and fig.2(c).
Circuit Configurations:
A transistor has three terminals hence when it is connected in a circuit one of its terminals in
common to input and output parts of the circuits. Three circuits configurations in which a transistor can
be connected are discussed below (discussion has been limited to NPN transistor):
1. Common Emitter Configuration
When a transistor is used in common emitter configuration the input is fed between its base
and emitter terminal and output is taken between the collector and emitter terminal as shown in fig.4
shows the circuit for determining the input and output characteristics of NPN transistor in common
emitter configuration. Fig 6 shows the wiring diagram for practically determining the common emitter
characteristics using this training board.
Input Characteristics:
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For input characteristics, the collector voltage i.e. Vc is kept constant. The base voltage is varied
in small steps and corresponding values of base current are observed. The readings are plotted on a
graph sheet with the base voltage Vb on the X-axis and the base current Ib on the Y-axis. Fig shows the
practical curves obtained for various transistors.
From the practical curves obtained, it is observed that the curve does not start from zero base
voltage (Vb). Appreciable base current flows when the base voltages are 0.3 volts for germanium
transistor and 0.6 volts for silicon transistor. From the curve we can obtain the input resistance of the
transistor.
Input Resistance Rin = Vb/Ib, at certain Vc value
Output Characteristics:
For obtaining the output characteristics, the base current is kept fixed at a certain value. The
collector voltage is increased in certain steps and corresponding readings of collector current are noted.
The reading can be repeated for another value of base current. The graph of Vc Vs. Ic is plotted for each
fixed value of Ib. fig shows the practical curves obtained for various transistors. From the curves it is
observed that:
1.
No collector current flows when Ib=0
2.
For a certain fixed value of base current the collector current does not vary, much with the
change of collector voltage.
The output resistance of a transistor can be obtained as:
R0 = Vc/Ic, at certain value of Ib.
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Also the current gain B of the transistor can be calculated as:
B = Ic/Ib, for a certain value of Vc.
3. Common Base Configuration:
INPUT CHARACTERSTICS
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Here the input is given between base and emitter and output is taken between collector and
base as shows in fig .9 fig.10 shows circuit diagram and fig.11 shows the wiring diagram for practically
determining the characteristics in the common base configuration.
Input Characteristics:
For input characteristics in the common base configuration the collector Vc is kept constant at a
certain value. The emitter voltage Ve is varied and corresponding value of emitter current Ie are
observed. Fig.11 shows the practical curves obtained for various transistors. From these curves we
observe the following:
1.
The curves start from zero.
2.
The emitter current increases sharply at an emitter voltage which is about 0.2V for a Ge and
about 0.6V for a Si transistor can be obtained as follows:
Ri = Ve/Ie, for a certain of Vc.
Output Characteristics:
For the output characteristics of a transistor in common base configuration, the emitter current
Ie is kept constant at a certain value. The collector variations corresponding to variations of the collector
voltages are observed. Fig shows the practical curves for various transistors. From the curves, we
observe as follows:
1.
The curves start from a point 0 instead of zero.
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2.
This point is about 0.2V for a Ge. Transistor and about 0.6V in case of a Si transistor.
3.
Point 0 is of polarity to the usual polarity of collector voltage.
4.
This point 0 is nearly same for all values of emitter current.
This output resistance of a transistor in common base configuration can be determined as
follows:
R0 =Vc/Ic, for a certain of Ie.
The current gain can also be calculated as:
α = Ic/Ie, for a certain value of Vc.
CIRCUIT DIAGRAM
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3.
Common Collector Configuration:
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Basic circuits are shown in fig. 12.
Input Characteristics:
For input characteristics, the emitter to collector voltage is kept constant. The base voltage is
varied in small increments and corresponding values of base current are noted. The graph is plotted
between IB and VCB from this graph, input resistance of the transistor can be determined:
Rin = VCB / IB, at certain value of VCE.
Output Characteristics:
The output characteristics show the relationship between output current IE and output voltage
VCE, at a constant value of input current IB.
Procedure:
Common Emitter:
Input Characteristics:
1.
Using suitable batch cords make connections as per shown in fig. For NPN transistor.
2.
Keep the knobs of both 0 – 10 V DC supplies to fully anticlockwise position.
3.
Switch on the power to the training board.
4.
Set the collector voltage to a certain value say 1 V.
5.
Vary the base voltage VB in 15 mV (20 mV) steps and observe the corresponding base current by
keeping the current meter in 200 A ranges.
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6.
Take the observations as per table 1 and plot the readings on a graph sheet. Take VB on the Xaxis and IB on the Y-axis.
Table – 1
S.No.
VC = .... Volt
VB
VC = .... Volt
IB
VB
IB
1.
2.
3.
4.
5.
Output Characteristics:
1.
Using suitable batch cords make connections as per shown in fig. For NPN transistor.
2.
Keep the knobs of both 0 – 10 V DC supplies to fully anticlockwise position.
3.
Switch on the power to the training board.
4.
Set the base current to a certain value say 25 A with the help of 0 – 10 V DC supply of the input
circuit.
5.
Now vary the collector voltage from 0 – 10 V in steps say 1 V and note down the corresponding
values of the collector current IC as per table 2.
6.
Repeat the collector voltage and collector current for different settings of the base current.
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7.
Plot the of collector voltage along X-axis and collector current along Y-axis.
Table – 2
IB = .... A
S.No.
VC
IB = .... A
IC
VC
IC
1.
2.
3.
4.
5.
Result :
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Experiment No. -3
Object : To study the RF oscillators using LC Colpitt‘s Oscillator.
Apparatus Required:
S.No.
6.
7.
8.
9.
Name of Instruments/Kit
Colpitt‘s Oscillator Trainer kit
Cathode Ray Oscilloscope
BNC Cable
Patch Chords
Specifications
ETB-25
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
08
COLPITTS OSCILLATOR:
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Above figure gives the circuit diagram of a Colpitts oscillator. Also stabilized divider method. The
three connections providing positive feedback are connected to the two ends, of the coil, and to the
junction of in this circuit C1 is in parallel with the output capacitance of the transistor and C2 is in
parallel with the input capacitance. Thus the transistor capacitances have an effect on the oscillation
frequency and if the capacitances change (for example due to a change in supply voltage or ambient
temperature) there is a corresponding change in the operating stability achieved, by making C1 and C2
large compared with the transistor capacitances. The Hartley and colpitts oscillators are very similar
circuits, with just inductance and capacitance interchanged. Therefore the circuit determinant for
colpitts is identical to the determinant described for Hartley oscillator, except that for colpitts circuit
jxc1 and jxc2 must replace jxl1 and jxl2 and jxl must replace jxc
The A.C equivalent circuit of oscillator is drown in Fig. with common emitter h parameter. An
analysis similar to that made for the Hartley circuits result in, for the oscillating frequency of the colpitts
oscillator.
PROCEDURE:
1. Trace the circuit according to practical circuit diagram shown on the panel.
2. Connect A to D, D to L, N to B,C to F,F to J,and G to H. now the circuit is same as shown in Fig
switch ON the supply provided at the left hand corner on the panel. Detect the oscillation by
absorption CRO and measure the frequency of oscillation for different position of gang
condenser.
RESULT:
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Experiment No. -4
Object:-
To study the RF oscillators using L-C Hartley Oscillator.
Apparatus Required:
S.No.
10.
11.
12.
13.
Name of Instruments/Kit
Hartley Oscillator Trainer kit
Cathode Ray Oscilloscope
BNC Cable
Patch Chords
Specifications
ETB-25
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
08
HEATLEY OSCILLATOR:
Figure 1
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Above figure gives the circuit diagram of a heartily oscillator. The study component of the
collector current is stabiles by the potential divider method and, except of the components required for
stabilization, the circuit is similar to that of a value Hartley oscillator. The frequency determining section
L, C is connected between collector (anode) and base (grid). The emitter (cathode) is effectively
connected to the tapping point on the inductor because the impedance of the power supply can be
assumed to be negligible at the frequency of oscillation.
PROCEDURE:
1. Trace the circuit according to practical circuit diagram shown on the panel.
2. Connect B to D , D to L, C to F, F to H and E to K. now the circuit is same as shown in figure
3. Switch ON the supply provided on the left hand corner on the panel. Detect the oscillation on
Absorption CRO and measure the frequency of oscillation for different position of gang condenser in
degrees.
RESULT:
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EXPERIMENT NO.- 5
Object: To study the phase shift audio oscillator.
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
14.
RC Phase Shift Oscillator kit
ETB-24
01
15.
Cathode Ray Oscilloscope
30 MHz
01
16.
BNC Cable
75 Ω
01
17.
Patch Chords
Banana Pin
06
Theory:
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Figure 2
The phase shift oscillator exemplifies all the oscillator principles discussed so far.fig shows a common
emitter transistor amplifier stage. This stage introduces a 180* phase shift to the signal applied to its
input.
Thus the RC phase shift network as shown in fig must provide additional 180* phase shift to
make an oscillator.
Let us study the phase shift provided by a CR circuit of fig. consider a current I to flow through both R
and C. than using I as the reference vector, V0 is in phase with I while Vc the voltage across the capacitor
is 90* behind I, but Vi is the sum of Vc and V0 hence Vo is θ degrees ahead of Vi and represents a phase
shift of θ degree as shown in fig
Procedure:
3. Trace the circuit according to practical circuit diagram shown on the panel.
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4. Observe the waveform by CRO.
Observation Table:
Calculated Value
S.No.
Value of Capacitor
f 
(pf)
1
2 6CR
Observed Frequency by
CRO
(Hz)
(Hz)
1.
1000 pf
2.
3300 pf
3.
6800 pf
RESULT:
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Experiment No.-6
Object:
To use the given U.J.T. as a relaxation oscillator.
Apparatus Required:
S.No.
18.
19.
20.
21.
Name of Instruments/Kit
UJT Relaxation Oscillator Trainer kit
Cathode Ray Oscilloscope
BNC Cable
Patch Chords
Specifications
ETB-73
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
05
Introduction
Figure 3
If EE is made greater than nEBB the diode is forward biased with a large emitter current and a low
forward voltage drop exists between E and B1. The holes introduced from the P region make the E to B1
region positive, and electrons are attracted there. As a result of the greatly increased in the numbers of
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charge carriers, the resistance falls the current through B1 rises, and the voltage falls, giving a the
negative resistance characteristics in region ‘B’.
Tern-on occurs when EE is equal to EP the peak point voltage, which is given as approximately Ep = n
EBB + 0.7 V.
Where 0.7 volt is as approximation of the usual diode voltage drop. The parameter n is called the
‘intrinsic stand of ratio’ and lies between 0.47 and 0.75 depending on UJT characteristic.
n = RB1/RB1 =RB2
the UJT with its negative resistance action makes a fast switch for gating the SCR. For such and
application the basic circuit as shown in fig. is employed. In the circuit, capacitor c1 charges through R1
until EE reaches the peak point voltage Ep, when the UJT triggers and discharges C1 through RB1. When
EE reaches a low value perhaps, the capacitor can no longer supply the necessary emitter base current
and the UJT turns off. The period of oscillation is given by
T =R1 C1 In 1/1-n sec.
Base resistor RB1 provides an output voltage pulse during the very short high current transition through
the negative resistance region.
Resistance RB1 should be low enough to prevent the d.c voltage due to inter base current from
exceeding the minimum gating voltage for the SCR. RB1 will usually be below 100 ohms the resistor R1
has its maximum value set by the requirement, that the emitter current, at the peak point must be
greater than Ip1 for the UJT to turn on. The lower limit on R1 should place its load line in the region of
max. Curvature of the characteristics, a value of 3000 ohms with EE = 20v might be suitable. The
frequency of oscillation can be controlled through adjustment of R1.
The amplitude of the output pulse is reduced by an increase in UJT temperature, but an increase in
temperature result in a smaller required gating pulse for an SCR. Therefore the two temperature effects
are compensatory.
Procedure
1. Make the connection as shown in fig.
2. Fix the voltage EBB as 5 volts.
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3. See the output wave shape across G & H and across J & H using C.R.O the wave shape will look
like show tooth shown in fig.
RESULT:
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EXPERIMENT NO:-8
OBJECT:
To study operational amplifier in following modes.
(1) Inverting amplifier
(2) Non-inverting amplifier
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
22.
Operational Amplifier Trainer kit
OAD-14
01
23.
Dual Trace Cathode Ray Oscilloscope
30 MHz
01
24.
Function Generator
30 MHz
01
25.
BNC Cable
75 Ω
03
26.
Patch Chords
Banana Pin
08
THEORY:
THE INVERTING AMPLIFIER:
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Figure 4
Fig:(1) illustrates the first basic OP-AMP configuration the inverting amplifier. In this circuit, the (+) input
is grounded and the signal is applied to the input through Rin, with feedback returned from the output
through Rf.By applying the ideal OP-AMP properties, the distinguishing features of this circuit may be
analysis as follows :
Since the amplifier has infinite gain, it will develop its output voltages Eo with zero input
voltages, since the deferential input to A is Es, Es=0. If Es is zero, than the full voltage, in must appear Rin
making the circuit in Rin.
Iin = Ein / Rin
Also, since Is = 0 due to infinite impedance, the input current, Iin must also flow in Rf. The output
voltage, Eo appears across Rf and is negative due to a sign inversion.
Amplifier starting If in the terms of Eo and Rf than,
If = Eo / Rf
Since Iin and If are equal, we may state
Ein / Rin = -Eo / Rf
This equality may be restated in terms of gain as
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Eo / Ein = Rf / Rin = Avo
Which is, in fact, the characteristics gain equation for the ideal inverting amplifier.
The gain of inverting amplifier can be verified by adjusting either Rf or Rin. If Rf is varied from zero to
infinity, the gain will also vary from zero to infinity since it is directly proportional to Rf. The input
impedance is equal to Rin and Ein and Rin alone determine Iin. Thus If =Iin for any value of Rf.
The input of the amplifier or the junction of the input and feedback signals is a node of zero voltage
regardless of the magnitude of Iin. Thus the junction is a virtual ground a point that will always be at the
same potential as the (+) input. Since the input and output signals sum at this junction, it is also known
as summing point. This final characteristic leads to a third basic OP-AMP which applies to closed loop
operation. With the loop closed, the (-) input will be driven to the potential of the (+) or reference input.
THE NON-INVERTING AMPLIFIER
Figure 5
The second basic configuration of the ideal OP-AMP is the non-inverting amplifier, shown in fig:2, in this
circuit voltage Ein is applied to the (+) Rin voltage divider. Since on input current flows into either input
terminal, and since Es = 0, the voltage Ein is equal to E.
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Hence by the thevenin's theorem
Rin / (Rin+Rf) * Eo = Ein
EoRin = (Rin+Rf)
Eo / Ein = (Rin+Rf) / Rin
Eo / Ein = 1+(Rf / Rin)
Which are the characteristics gains for the ideal non-inverting amplifier? Additional characteristics of
this configuration can also be deducted. The lower limit of gain occurs when Rf = 0, which yields a gain
of unity. In the inverting amplifier, the current Iin always determines If, which is independent of Rf. Thus
Rf may be used as a liner gain control capable of increasing gain from a minimum of unity to a maximum
of infinity. The input impedance is infinite, since an ideal amplifier is assumed.
PROCEDURE:
INVERTING AMPLIFIER:
Ratio of the feedback resistance to the input resistance governs the gain of the amplifier.
Gain = -Rf / Rin = 10K ohms/1k ohms = -10
Make the circuit connection as shown in fig.05 with the help of patch cords. Apply 1-volt dc and note
that output will be -10 times of the input voltage. Output of the Op-Amp cannot go beyond -15 volts. So
do not feed input more than +1.5V, when the input goes beyond ±1.5V.When the input goes beyond
±1.5V, Op-Amp will go into saturation state.
Note that output will be inverted. Hence this circuit is called amplifier.
NON-INVERTING AMPLIFIER:
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In a non-inverting amplifier input is amplified to non-inverting input terminal and gain can be adjusted
by changing feedback resistance. Here this circuit is designed for 10 gains. Since component tolerance is
±1.5%, the result will be within ±1.5%. Make the circuit connections as shown in fig.06 with the help of
patch cords. Apply input (it should be less than 1.5V) and observe the output. Output will be noninverted and amplified by approximately 10 times.
OBSERVATION TABLE:
INVERTING AMPLIFIER:
S.no
Vin
Vout
Gain A=Vout / Vin
Vout
Gain A=Vout / Vin
1.
2.
3.
4.
5.
NON-INVERTING AMPLIFIER:
S.no
Vin
1.
2.
3.
4.
5.
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RESULT:
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EXPERIMENT NO.-9
Summing Amplifier and Subtractor Amplifier
OBJECT: - Design the amplifier in following modes using 741-IC.
1. Summing Amplifier Circuit
2. Subtractor Amplifier Circuit
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
27.
Operational Amplifier Trainer kit
OAD-14
01
28.
Dual Trace Cathode Ray Oscilloscope
30 MHz
01
29.
Function Generator
30 MHz
01
30.
BNC Cable
75 Ω
03
31.
Patch Chords
Banana Pin
08
THEORY:
SUMMING AMPLIFIER
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Figure 6
Fig.2 shows the inverting configurations with three input Va, Vb & Vc. Depending on the relationship
between the feedback Rf &the input resistors Ra,Rb &Rc the circuit functions can be verified by
examining the expression for output voltage V0, which is obtained from kircoff's current equation
written at node V2.
Ia + Ib + Ic = If +Ib
Since R1 & a of the op-amp are ideally infinity, Ib =0anp & V1 = V2 = 0volts
Therefore
Va/Ra +Vb/Rb +Vc/Rc = -Vo/Rf
V0 = -Rf(Va/Ra+Vb/Rb+Vc/Rc)
SUBTRACTOR AMPLIFIER
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Figure 7
A basic differential amplifier can be used as a subtract or as shown in fig.3 in this fig. input signal can be
sealed to the desired values for the external resistor, when this is don the circuit is referred to as scaling
amplifier. In fig.3 external resistors are equal in value so the gain of the amplifier is equal to 1.
For this fig. the O/P voltage of the differential amplifier with a gain of 10 is
Vo = -Rf/R(Va-Vb)
i.e
Vo = 10(Va-Vb)
Thus the output voltage Vo is equal to the voltage Vb applied to the non-inverting terminal, hence the
circuit is called a subtract or.
PROCEDURE
SUMMING AMPLIFIER
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Make circuit connection as shown in fig 2. The O/P will be the 10 times of the sum of the input. Don’t
give input that the op-amp goes in saturation.
SUBTRACTOR AMPLIFIER
Make circuit connection as shown in fig.3 give two different I/P and measure the O/P. It will be the 10
times of the difference of the inputs.
OVBSERVATION TABLE
SUMMING AMPLIFIER
S.No
Va
Vb
Vc
Vo(observed)
Vo(calculated)
Vc
Vo(observed)
Vo(calculated)
1.
2.
3.
4.
5.
SUBTRACTING AMPLIFIER
S.No
Va
Vb
1.
2.
3.
4.
5.
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RESULT:-
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Experiment No.-10
Object: -
To the study of operational amplifier as a integrator.
Apparatus Required:
S.No.
32.
33.
34.
35.
36.
Name of Instruments/Kit
Operational Amplifier Trainer kit
Dual Trace Cathode Ray Oscilloscope
Function Generator
BNC Cable
Patch Chords
Specifications
OAD-14
30 MHz
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
03
08
THEORY
The integrator
An integrator is shown in Fig. as input voltage, Ein is applied to Rin, thus developing current Iin. As
in the basic inverter, Es= 0, Is = 0, and If = Iin. The feedback element in the integrator is a capacitor, Cf.
Figure 8
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Therefore, the constant current, If. In Cf builds a linear voltage ramp across Cf. then output voltage is
thus an integral of the input current, which is forced to charge Cf by the feedback loop. The change in
voltage across Cf is
-δEo=Iin δ t/ Cf
Which makes the output change per unit to time.
δ Eo/δ t = -Ein/δ Rin
input impedance of this circuit will be Rin
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Experiment no.-11
Object
To the study of operational amplifier as a Differentiator.
Apparatus Required:
S.No.
37.
38.
39.
40.
41.
Name of Instruments/Kit
Operational Amplifier Trainer kit
Dual Trace Cathode Ray Oscilloscope
Function Generator
BNC Cable
Patch Chords
Specifications
OAD-14
30 MHz
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
03
08
THEORY
The Differentiator
Differentiator circuit is shown in Fig in this circuit, the positions of R and C are reversed from
those in the integrator, placing the capacitive element in the input network. Thus the input current is
made to be proportional to the rate of change of the input voltage.
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Figure 9
Iin= δ Ein Cin/δ t
Again,
If = Iin
And scince, - Eo = If Rf
Or
Eo = - If Rf
Eo = δ Ein Rf Cin / δ t
Es = 0
Is = 0
IR = 0
Eo = Ein
Gain = 1
Input impedance = ∞
A special modification of the non-inverting amplifier is the unit gain stage as shown in Fig in this
circuit, Rin has increased to infinity, Rf is zero, and the feedback is 100%. Eo is then exactly equal to Ein
since Es = 0. The circuit is known as a voltage fallower since the output is a unity gain, in phase replica of
the input voltage. The input impedance of this stage is also infinite.
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