Download Microcomputer Control Systems I

VŠB-Technical University of Ostrava
Faculty of Electrical Engineering and Computer Science
Department of Electronics
Microcomputer Control Systems I
Ing. Petr Hudeček
2011
CONTENT:
1
BASIC TERMS OF DIGITAL TECHNOLOGY ....................................................................................... 4
1.1
NUMBERS CONVERSION (DECIMAL, HEXADECIMAL, BINARY) ................................................................. 4
1.2
LOGICAL FUNCTION AND THEIR EXPRESSIONS .......................................................................................... 5
1.2.1
Definition of logical function .......................................................................................................... 5
1.2.2
Logical function expressions ........................................................................................................... 5
1.2.3
Minimalization of logical function .................................................................................................. 6
1.2.3.1
1.2.3.2
2
With Boolean algebra .................................................................................................................................. 6
With Karnaugh maps ................................................................................................................................... 7
LOGIC GATES ............................................................................................................................................. 9
2.1
NAND GATES........................................................................................................................................ 10
2.1.1
NAND structure ............................................................................................................................. 10
2.1.2
NAND sub-types ............................................................................................................................ 12
2.1.3
NAND summary ............................................................................................................................ 12
2.2
NOISE IMUNITY ...................................................................................................................................... 12
2.3
WORK PRINCIPLES WITH LOGICAL GATES ............................................................................................... 13
2.3.1
Unused inputs and outputs ............................................................................................................ 13
2.3.2
Input logic signals adjustments ..................................................................................................... 13
2.3.3
Holding circuits ............................................................................................................................. 14
2.3.4
Outputs of logic gates .................................................................................................................... 15
2.3.5
Logic levels distribution ................................................................................................................ 15
2.3.6
GND distribution ........................................................................................................................... 16
2.3.7
Long wires excitation .................................................................................................................... 16
3
MICROCONTROLLER AND MICROPROCESSOR BASIC TERMS ............................................... 18
3.1
MICROCONTROLLER .............................................................................................................................. 18
3.2
MICROPROCESSOR (CPU) ...................................................................................................................... 18
3.2.1
CPU basic parts ............................................................................................................................ 19
3.2.2
Microprocessors actions ............................................................................................................... 19
3.2.2.1
3.2.2.2
3.2.2.3
4
Microprocessor timing ............................................................................................................................... 19
Instruction set ............................................................................................................................................ 20
Interrupt ..................................................................................................................................................... 20
BUSES IN MICROCONTROLLERS ....................................................................................................... 20
4.1
DIVISION IN MICROPROCESSOR TECHNIQUE ........................................................................................... 20
4.2
BUS TRANSFER TYPES (BY HARDWARE REALISATION): .......................................................................... 21
4.2.1
Parallel transfer ............................................................................................................................ 21
4.2.2
Serial transfer................................................................................................................................ 21
4.2.2.1
4.2.2.2
4.3
5
TRANSFER ERRORS ................................................................................................................................. 21
ADDRESS DECODERS ............................................................................................................................. 22
5.1
5.2
5.3
6
Synchronous serial transfer........................................................................................................................ 21
Asynchronous serial transfer ..................................................................................................................... 21
FULL ADDRESS DECODERS ..................................................................................................................... 22
INCOMPLETE ADDRESS DECODERS ......................................................................................................... 22
THE ADDRESS DECODER WITH LINEAR ADDRESS ASSIGNMENT ............................................................... 23
MICROCONTROLLER AND COMMUNICATION WITH PERIPHERY ........................................ 24
6.1
PROGRAM CONTROL OF COMMUNICATION ............................................................................................. 24
6.2
7
CONTROL OF COMMUNICATION BY INTERRUPTS .................................................................................... 24
SERIAL INTERFACES ............................................................................................................................. 24
7.1
RS232 .................................................................................................................................................... 25
7.2
RS422 .................................................................................................................................................... 25
7.3
RS485 .................................................................................................................................................... 25
7.4
CURRENT LOOP ...................................................................................................................................... 26
7.5
USB ....................................................................................................................................................... 26
7.6
SPI INTERFACE....................................................................................................................................... 26
7.7
I2C INTERFACE ....................................................................................................................................... 27
7.7.1
I2C Communication ....................................................................................................................... 28
7.7.2
I2C Multi-master mode .................................................................................................................. 28
7.7.3
I2C Addressing............................................................................................................................... 28
7.7.4
Acknowledge ................................................................................................................................. 28
8
SEMICONDUCTOR MEMORY .............................................................................................................. 29
8.1
8.2
8.3
9
DIVISION ACCORDING TO MEMORY ACCESS ........................................................................................... 29
DIVISION ACCORDING TO READ/WRITE POSSIBILITY ............................................................................... 29
DIVISION ACCORDING TO ELEMENTARY MEMORY CELLS PRINCIPLE ...................................................... 29
MICROCONTROLLER AND ANALOG ENVIRONMENT................................................................. 30
9.1
METHODS OF CONNECTING THE MICROCONTROLLER TO ANALOG ENVIRONMENT – ANALOG INPUT ...... 30
9.2
ANALOG CONVERTER TYPES .................................................................................................................. 31
9.2.1
Parallel A/D converter .................................................................................................................. 31
9.2.2
Compensational A/D converter ..................................................................................................... 31
9.2.3
Integrating converter..................................................................................................................... 32
9.2.4
Specifications of A/D ..................................................................................................................... 33
9.3
ANALOG OUTPUT ................................................................................................................................... 33
9.4
D/A CONVERTER TYPES ......................................................................................................................... 33
9.4.1
D/A with resistor net ..................................................................................................................... 34
9.4.2
D/A with R-2R ............................................................................................................................... 34
9.4.3
Specification of D/A ...................................................................................................................... 34
9.5
CODES FOR A/D AND D/A CONVERTERS - UNSIGNED ............................................................................ 35
9.5.1
Non negative numbers (e.g. integer) (Unsigned) .......................................................................... 35
9.5.2
Non negative real number (e.g. fraction) ...................................................................................... 35
9.6
CODES FOR A/D AND D/A CONVERTERS - EXPRESSION OF MARK (+,-) (SIGNED) ................................... 35
9.6.1
Absolute values.............................................................................................................................. 35
9.6.2
One′s complement (1x)................................................................................................................... 35
9.6.3
Two′s complement (2x) .................................................................................................................. 36
9.6.4
One half of internal ....................................................................................................................... 36
10
CPU, MCU AND MCU SYSTEMS ........................................................................................................... 36
10.1 DIVIDING BY PARAMETERS .................................................................................................................... 36
10.2 DIVIDING BY INSTRUCTION SET .............................................................................................................. 37
10.2.1
CISC (Complex Instruction Set Computer) ................................................................................... 37
10.2.2
RISC (Reduce Instruction Set Computer) ...................................................................................... 37
10.3 DIVIDING BY ARCHITECTURE ................................................................................................................. 37
10.3.1
Von Neumann architecture............................................................................................................ 37
10.3.2
Harvard architecture..................................................................................................................... 37
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
1
BASIC TERMS OF DIGITAL TECHNOLOGY
1.1
NUMBERS CONVERSION (DECIMAL, HEXADECIMAL, BINARY)
•
Binary number N2 = 1 1011 1100 to:
N10 = 1 ⋅ 28 + 1 ⋅ 27 + 0 ⋅ 26 + 1 ⋅ 25 + 1 ⋅ 24 + 1 ⋅ 23 + 1 ⋅ 22 + 0 ⋅ 21 + 0 ⋅ 20 = 444
N16 = 1BC because 1 1011 1100
1 ⋅ 2 + 1 ⋅ 2 + 0 ⋅ 2 + 0 ⋅ 2 = 12 =
1 ⋅ 2 + 0 ⋅ 2 + 1 ⋅ 2 + 1 ⋅ 2 = 11 =
•
Hexadecimal number N16 = 3E7 to:
N = 3 ⋅ 16 + 14 ⋅ 16 + 7 ⋅ 16 = 999
N = 1111100111- In reverse order as above (in red boxes).
•
Decimal number N10 = 222 to:
a)
Method of gradual substract
2 to the power
7
2 = 128
6
2 = 64
25 = 32
24 = 16
23 = 8
22 = 4
21 = 2
20 = 1
Difference
Coefficient
222 - 1⋅128 = 94
1
94 - 1⋅64 = 30
30 - 0⋅32 = 30
30 - 1⋅16 = 14
14 - 1⋅8 = 6
6 - 1⋅4 = 2
2 - 1⋅2 = 0
1
0
1
1
1
1
0
0 - 0⋅1 => 0
N2 = 1101 1110
b) Method of gradual separation (division)
Difference
Coefficient
222 ÷ 2 = 111
0
111 ÷ 2 = 55
55 ÷ 2 = 27
27 ÷ 2 = 13
13 ÷ 2 = 6
6÷2=3
3÷2=1
1
1
1
1
0
1
1
1÷2=0
N2 = 1101 1110
Page 4
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Both methods of gradual substract and gradual separation aren’t only for conversions from decimal
number, but these methods are useful for conversions for example from decimal to octal or from octal to
hexadecimal and so on.
1.2
LOGICAL FUNCTION AND THEIR EXPRESSIONS
1.2.1
DEFINITION OF LOGICAL FUNCTION
Logical function describes behaviour of logical circuit with use of true/false variables. Some important
logical functions (for this subject) are:
f1 = a ⋅ b (AND), f2 = a + b (OR), f3 = ⋅ (NAND), f4 =
1.2.2
•
•
LOGICAL FUNCTION EXPRESSIONS
By truth table
Status
X3
X2
X1
Logical function y
0
0
0
0
1
1
0
0
1
1
2
0
1
0
0
3
0
1
1
0
4
1
0
0
1
5
1
0
1
1
6
1
1
0
0
7
1
1
1
1
Disjunction form – sum of products
=
•
+ (NOR)
⋅
⋅
+
⋅
⋅
+
⋅
⋅
+
+
+
⋅
⋅
+
⋅
⋅
Conjunction form – product of sums
=
+
+
⋅
⋅
+
+
Note that the logical ones in the truth table correspond to disjunction form, while logical zeros correspond
to conjunction form. Logical function we can write (by using state indexes) f(x1, x2, x3) = ∑ (0, 1, 4, 5, 7) for
disjunction form and f(x1, x2, x3) = ∏ (2, 3, 6) for conjunction form too.
Page 5
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
1.2.3
MINIMALIZATION OF LOGICAL FUNCTION
1.2.3.1
WITH BOOLEAN ALGEBRA
Is algebra which can be understood as algebra in set of two elements B = {0; 1} with three allowed
operations (logical product – disjunction (+), logical sum – conjunction (-) and inhibition – negation). With using
laws of Boolean algebra (Fig.1) we can simplify the logical functions.
Name
The Idempotent Laws
The Associative Laws
The Commutative Laws
The Distributive Laws
The Identity Laws
The Complement Laws
The Involution Law
De Morgan's Law
AND form
AA = A
(AB)C = A(BC)
AB = BA
A(B + C) = AB + AC
AF = F
AT = A
AA = F A + A = T
#=A
A
AB = A + B
OR form
A+A=A
(A + B) + C = A + (B + C)
A+B=B+A
A + BC = (A + B)(A + C)
A+F=A A+T=T
F=T
T=F
A+B=AB
Fig. 1: Some important identities of Boolean algebra.
Example:
a) Simplify C +
:
Expression
C + $%
Rule(s) Used
Original Expression
C + ($ + %)
De Morgan's Law.
(C + %) + $
Commutative, Associative Laws
T+$
T
Complement Law
Identity Law
b) Simplify AB(A + B)(B + B):
Expression
&$(& + B)($ + B)
&$(& + B)
(& + $)(& + B)
& + $B
&
Rule(s) Used
Original Expression
Complement law, Identity law
De Morgan's Law
Distributive law. This step uses the fact that or distributes over
and. It can look a bit strange since addition does not distribute
over multiplication.
Complement, Identity
Page 6
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
c) Simplify (A + C)(AD + AD) + AC + C:
Expression
(A + C)(AD + A() + AC + C
(A + C)A(D + () + AC + C
Rule(s) Used
Original Expression
Distributive
(A + C)A + AC + C
Complement, Identity
A((A + C) + C) + C
Commutative, Distributive
A(A + C) + C
Associative, Idempotent
AA + AC + C
Distributive
A + (A + T)C
Idempotent, Identity, Distributive
A+C
Identity, twice
You can also use distribution of or over and starting from A (A+C) +C to reach the same result
by another route.
d) Simplify A(A + B) + (B + AA)(A + B):
Expression
&(A + B) + (B + AA)(A + $)
&A + &B + (B + A)A + (B + A)$
&B + (B + A)A + (B + A)$
&B + BA + AA + B$ + A$
&B + BA + A + A$
&B + AB + AT + A$
&B + A(B + T + $)
Original Expression
Idempotent (AA to A), then Distributive, used twice
Complement, then Identity. (Strictly speaking, we
also used the Commutative Law for each of these
applications.)
Distributive, two places
Idempotent (for the A's), then Complement and
Identity to remove BB
Commutative, Identity. Setting up for the next step.
Distributive
&B + A
Identity, twice (depending how you count it)
A + &B
Commutative
(A + &)(A + B)
A+B
1.2.3.2
Rule(s) Used
Distributive
Complement, Identity
WITH KARNAUGH MAPS
Karnaugh map is set of squares. Number of squares is 2x, when x is number of input variables (3 variables
= > 23 = 8, 4 variables = > 24 = 16 etc.).
Page 7
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
X2
Input variables
X1
X2
0
1
2
3
X1
X3
0
1
3
2
4
5
7
6
State indexes
of variables
X5
X2
X2
X1
X1
0
1
3
2
4
5
7
6
X3
X4
12
13
15
X1
0
1
3
2
18
19
17
16
4
5
7
6
22
23
21
20
12
13
15
14
30
32
29
28
8
9
11
10
26
27
25
24
X3
14
X4
8
9
11
10
Fig. 2: Examples of Karnaugh maps for 2 to 5 variables.
Functional values of the logical function are entered in the Karnaugh map so that to the corresponding field
in the map, type 1 (if the function value is equal to 1) or 0 (if the functional value is undefined) for each
combination of input variables. Neighbouring fields can be linked into larger units called loops. It is necessary to
link all neighbouring logical ones to loop for finding minimal disjunctive form of logic function. Size of loops
has to be equal 2n. It means 1, 2, 4, 8, 16 and etc. fields of the Karnaugh map in the one loop. Examples are on
fig.3.
Fig. 3: Examples of loops in Karnaugh maps.
Loops can also include unspecified states marked by X. Neighbouring fields are also fields in the corners
map. For finding minimal conjunctive form loops includes zeros or unspecified states.
Example:
As an example we simplify the previous logic function f(x1, x2, x3) = ∑ (0, 1, 4, 5, 7). The Karnaugh map
with loops and the result for disjunction form is:
X2
X1
X3
1
1
0
0
1
1
1
0
y=) +) ⋅)
Page 8
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
The Karnaugh map with loops and the result for conjunctive form is:
X2
X1
X3
1
1
0
0
1
1
1
0
y= ) +)
2
⋅ )
)
LOGIC GATES
A logic gate is a device which has implemented Boolean functions.
functions. It means that logic gates performs a
logical operation on one or more logic inputs and produces a single logic output.
output Logic gates process signals
which represent true or false.. Normally the positive supply voltage represents true and 0V represents false. For
small-scale logic, designers
igners now use prefabricated logic gates from families of devices such as the TTL 7400
series by Texas Instruments and the CMOS 4000 series by RCA, and their more recent descendants. Basic types
of logic gates are:
Type
Distinctive shape
Rectangular shape
Boolean algebra
between A & B
AND
A⋅B
OR
A
B
NOT
A
NAND
A⋅B
NOR
A
XOR
A⨁B
XNOR
Truth table
+⊕
B
or + ⊙
Fig. 4: Basic types of logic gates.
Page 9
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
2.1
2.1.1
NAND GATES
NAND STRUCTURE
Because all
ll family of logic gates comes from NAND gates (outside the few exceptions) it’s good to know
the NAND inner structure for the next work.
work The NAND structure is on the fig.5.
Fig. 5: NAND structure.
NAND with the high output resistance
resista
consists of the two n-p-nn transistors V3 and V4, the "lifting" diode
V5 and the current-limiting resistor
tor R3. When V2 is "off", V4 is "off" as well and V3 operates in active region as
a voltage follower producing high output voltage (logical "1"). When V2 is "on", it activates V4, driving low
voltage (logical "0") to the output. V2 and V4 collector–emitter
collector emitter junctions connect V4 base–emitter
base
junction in
parallel to the series-connected
connected V3 base–emitter
base
and V5 anode–cathode
cathode junctions. V3 base current is deprived,
dep
the transistor turns "off" and it does not impact on the output. In the middle of the transition, the resistor R3
limits the current flowing directly through the series connected transistor V3, diode V5 and transistor V4 that are
all conducting. It also limits the output current in the case of output logical "1" and short connection to the
ground. The strength of the gate may be increased without proportionally affecting the power consumption by
removing the pull-up and pull-down
down resistors from the output
o
stage.
The main advantage of TTL which is shown at fig.5 is the low output resistance at output logical "1". It is
determined by the upper output transistor V3 operating in active region as a voltage follower. The resistor R3
does not increase the output
utput resistance since it is connected in the V3 collector and its influence is compensated
by the negative feedback. A disadvantage is the decreased voltage level (no more than 3.5 V) of the output
logical "1" (even, if the output is unloaded). The reasons of this reduction are the voltage drops across the V3
base–emitter and V5 anode–cathode
cathode junctions.
Page 10
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Fig. 6: Input NAND charakteristic.
Fig. 7: Output NAND charakteristics.
Fig. 8: Transient characteristic of NAND.
Fig. 9: Comsumption characteristics of NAND.
Page 11
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
2.1.2
NAND SUB-TYPES
Basic TTL family variations and their successors which have a 10ns typical gate propagation delay and a
10mW power dissipation per gate for a 100 pJ switching energy we can divide to:
•
•
•
•
•
•
Low-power TTL (L), which traded switching speed (33ns) for a reduction in power consumption (1
mW) (now essentially replaced by CMOS logic)
High-speed TTL (H), with faster switching than standard TTL (6ns) but significantly higher power
dissipation (22 mW)
Schottky TTL (S), introduced in 1969, which used Schottky diode clamps at gate inputs to prevent
charge storage and improve switching time. These gates operated more quickly (3ns) but had higher
power dissipation (19 mW)
Low-power Schottky TTL (LS) – used the higher resistance values of low-power TTL and the
Schottky diodes to provide a good combination of speed (9.5ns) and reduced power consumption (2
mW), and PDP of about 20 pJ. Probably the most common type of TTL, these were used as glue logic
in microcomputers, essentially replacing the former H, L, and S sub-families.
Fast (F) and Advanced-Schottky (AS) variants of LS from Fairchild and TI, respectively, circa 1985,
with "Miller-killer" circuits to speed up the low-to-high transition. These families achieved PDPs of 10
pJ and 4 pJ, respectively, the lowest of all the TTL families.
Low-voltage TTL (LVTTL) for 3.3-volt power supplies and memory interfacing.
Most manufacturers offer commercial and extended temperature ranges: e.g. Texas Instruments 7400 series
parts are rated from 0 to 70°C and 5400 series devices over the military-specification temperature range of −55
to +125°C. Although manufacturers distribute various product lines as TTL in the LS family, some of new
circuits could rather be considered as DTL.
2.1.3
NAND SUMMARY
Power supply Logical gain Gate delay Max. frequency Gate power
Voltage [V]
[-]
[ns]
[MHz]
[nW]
CMOS 4000
3 to 15
50
40 to 20
8 to 16
10
CMOS 74C
3 to 15
50
50 to 30
3 to 8
10 to 30
CMOS 74SC
3 to 7
50
36
30
10
CMOS 74HC
2 to 6
10
6
60
10
CMOS 74HCT
5
10
6
60
103
CMOS 74HCU
2 to 6
10
6
60
103
10
10
35
107
TTL 74
5±5%
TTL 74L
10
33
3
106
5±5%
TTL 74S
10
3
125
1,9*107
5±5%
TTL 74LS
20
10
45
2*106
5±5%
TTL 74AS
20
1,5
200
2,2*107
5±5%
TTL 74ALS
20
4
50
106
5±5%
Type of logic
Fig. 10: NAND summary.
2.2
NOISE IMUNITY
It is a voltage level that can still break into the connections between integrated circuits, without response to
this parasitic signal. At the gates is important of guaranteeing the following TTL logic voltage levels:
Page 12
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
LOG 0
LOG 1
INPUT
0÷
÷0,8
2÷
÷UCC
OUTPUT
0÷
÷0,4
2,4÷
÷UCC
Fig. 11: Conditions for connection of two TTL gates.
2.3
2.3.1
Fig. 12: Values of TTL logic level gate.
WORK PRINCIPLES WITH LOGICAL GATES
UNUSED INPUTS AND OUTPUTS
Unused inputs - TTL devices have normally the logic one as default value if the input is allowed to float.
However (depending on many factors), TTL inputs can act as an antenna, different noise increases and it can
cause mischief to the circuit. The worst case is that the device will act as an uncontrolled intermittent oscillator.
Therefore, all unused inputs of TTL logic devices must be connected to a logic one or logic zero. If is more logic
gates in one package, it is better connect inputs of unused logic gates to zero for better current consumption.
Certain devices as is 74XX or earlier 74LSXX need a 1k resistor on Vcc or on ground (zero). This resistor is
unnecessary for all other logic devices.
In the case of CMOS devices, there is no default value on input. Value of CMOS input impedance is in
thousands of mega ohms and can cause extreme failures if would be allowed to float. It means. If you put your
finger or a scope probe near an un-terminated CMOS input, it can cause a logic change! In addition if CMOS
input is allowed to float, some devices can oscillate so fast that can destroy them because it exceeds theirs power
rating.
Unused Outputs - tri-state and open collector devices etc. do not require any attention. In the case of the
tri-state control pin, it should be treated as an input.
2.3.2
INPUT LOGIC SIGNALS ADJUSTMENTS
Fig. 13: Decrease of the input voltage in H state.
Page 13
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Fig. 14: Universal converter for ± 100V input signals.
Fig. 15: TTL to CMOS and CMOS to TTL connection.
2.3.3
HOLDING CIRCUITS
A
B
C
A
B
C
Fig. 16: Shaping the signal by gates.
2k2
22
A
B
C
Fig. 17: Shaping the signal by gates with positive feedback.
Page 14
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
For shaping of signals with longer edges we can use the Schmitt flip-flops (e.g. 74132 or analog). Another
possibility of signal forming is by D flip-flop circuits (Fig.18). Disadvantage of this possibility is use of a clock
pulses generator.
Fig. 18: Shaping the signal by D flip-flop circuit.
2.3.4
OUTPUTS OF LOGIC GATES
The most commonly used output element is a relay or power transistor. For the relay we must use the
transistor amplifier connected to the gate. It should be noted that the base current is limited only by the internal
resistance. Choosing of transistor type depends on this. If the gate output is connected directly into the transistor
base it can no longer use this output to drive the next gate input. One of the possible output connections is shown
in Figure 19.
Fig. 19: Logic gate with transistor on output.
Fig. 20: Logic gate with transistor on output active on zero state.
2.3.5
LOGIC LEVELS DISTRIBUTION
For correct logic gates operation must be provided the quality power supply. There are two requirements:
•
•
small active resistance of wires and power supply – capacitor connected near to the package
small impedance of wire and high frequency signal supply – each power parts must be in small
loops. If we need smaller loops we must connect capacitors, which do the high voltage short circuit
Page 15
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
For connections between gates we have several ways. The default connection is by PCB (Printed Circuit Board).
Outside the board may use wires, coaxial cables, printed circuits, etc. We must always thought with the fact that
each line can occur following states:
•
•
•
•
signal is delayed in wire
the wire leads to reflections
the wire is charged and discharged
wires can react between us
A logic hazard is the situation where, when one input variable changes, the output changes momentarily before
stabilizing to the correct value. There are two types of static hazards:
•
•
2.3.6
Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to
0 before settling on 1
Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily changes to
1 before settling on 0
GND DISTRIBUTION
Common wire must be implemented (wire or copper foil on the PCB) to have the least resistance and with
negligible inductance. Wires with these requirements must have large cross-section. When designing a PCB
therefore always try to design the maximum widest possible distribution of GND. If device have beside the logic
gates other types of circuits such as linear integrated circuits or power relays etc. each of these circuits must be
connected separately to GND. It means processors, logic devices and etc. to one ground (mostly called digital
ground), power relays, operational amplifiers and etc. to another ground (mostly called analog ground) and these
ground groups are concentrated to the one point, near to the ground terminal of most critical operational
amplifier (which handles the smallest signal level) or near to a power supply. When is GND common wire
designed it must be checked the maximum current that can flow through it.
2.3.7
LONG WIRES EXCITATION
Signal wire for fast TTL circuits which is longer than 25 cm is considered as long wire. If we transfer the
data by standard PCB (Printed Circuit Board), we risk the problems as are shown on figure 22.
Fig. 21: Transfer principle scheme by a long wire.
Page 16
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
4
4
2
2
A
0
-2
-2
4
4
2
2
B
0
-2
4
U [V]
U [V]
A
0
3
0
B
-2
4
2
4
2
0
C
-2
4
2
0
-2
C
1
4
2
2
D
0
-2
D
0
-2
0
40
80
120 160
0
t [ns]
40
80
120 160
t [ns]
Fig. 22: Situation on the wire around 20cm (left) and 2m (right) long.
Fig. 23: Adapting of a long wire.
A wire which is ended by TTL input is not due to its high impedance adapted. Adapting schemes are shown
in Fig. 23. The most suitable for long wires transmission is a coaxial cable (high resistance to interference, cross
talk) to three meters can be used the twist wire, wire and PCB to 30cm.
Page 17
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
3
MICROCONTROLLERS AND MICROPROCESSORS BASIC TERMS
3.1
MICROCONTROLLER
Microcomputer is a computer with a microprocessor as its central processing unit. They are physically small.
Many microcomputers (when equipped with a keyboard and screen for input and output) are also personal
computers. Microcomputers could be compared to Microcontrollers.
Microcontrollers work with 8b, 16b, or 32b data words. Basic parts of MCU:
a)
Clock generator
•
•
Usually oscillator with crystal resonator
Generate clock cycle (synchronise all parts of MCU)
b) Microprocessor
•
•
•
c)
Basic element of MCU
Controls all activities of MCU, provide execute of instructions
Controls data flow at inputs/outputs peripherals
Flash program memory
•
•
ROM types were used before
Contains program in form of instruction and operation parameters
d) RAM memory – for data storage
e)
I/O parts
f)
Peripherals
Fig. 24: Microcontroller block scheme
3.2
MICROPROCESSOR (CPU)
Integrated circuit with high integration density and computing power. Block scheme of unspecified type of
microprocessor can be seen on Fig. 25.
Page 18
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Fig. 25: Block scheme of microprocessor
3.2.1
a)
CPU BASIC PARTS
Controller
•
•
Controls all action of CPU
Instruction Registry (IR) and Instruction Decoder (DI)
b) PC (Program Counter)
•
c)
Contains address of each instructions, IR
SP (Stack Pointer)
•
•
LIFO type memory
Return address are saved here
d) ALU
•
•
•
•
Ensures of arithmetical and logical operations (adding, subtraction) on better
Types of CPUs can ensures division and multiply
Uses accumulator (registry for saving operand)
Contain Flag register – inform us about attributes of results
e)
Set of registers - memory part of CPU
f)
Direct memory addressing (very fast access in chip memory) - divides to register banks
3.2.2
MICROPROCESSORS ACTIONS
3.2.2.1
MICROPROCESSOR TIMING
Timing is derived from clock signal. Basic time unit is one clock cycle. Instruction cycle could be divided
into machine cycles:
•
•
•
Operand fetch
Instruction decode
Execute
Page 19
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
3.2.2.2
INSTRUCTION SET
• Expression of instruction by language of symbolical addresses
• Every microprocessor has define set of instructions
• Instruction consists from OPCOD (Operation code) and data word (or address)
Instruction types:
•
•
•
•
•
•
•
•
Transfer type instructions
Arithmetical type inst.
Logical type inst.
Moving and Rotating type inst.
Jump inst.
Call type inst.
Return from subroutine inst.
Control type inst. Data addressing modes (direct, indirect, relative, page)
3.2.2.3
INTERRUPT
• Ensures quick response of microprocessor or microcontroller to some stimulus from environment (input
signal, timer, error)
• Hardware interrupts are contained in CPU and then in MCU are expanded by interrupt system
• We only works with interrupts which are important → this ensures mask interrupt unit, there are interrupt
levels priority
4
BUSES IN MICROCONTROLLERS
All blocks in microcontroller are connected via bus. Buses ensure information change between
microprocessor and other parts of microcontroller (all blocks are connected through set of wires). Transfer rate is
determined by Bd (Bauds). It is number of bit per second.
4.1
DIVISION IN MICROPROCESSOR TECHNIQUE
a)
Data bus
•
•
•
Ensures data transfer between two blocks
Width of data bus is very important ⇒ from this transfer speed is derived
Communication at bus has to be controlled to avoid collision or data lose
b) Address bus
•
c)
Identification of memory space to read or write → Address 8bit bus could address 256 ═ 28
addresses (16b ═ 65536 addresses)
Control bus
•
Set of individual signals difference significances (Reset, MR, MW, Ready, IOW/IOR)
Another bus division:
•
•
•
Inner bus of CPU
Inner bus of MCU
Outer bus of microcomputer (ISA, PCI, AGP, USB)
Page 20
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
4.2
BUS TRANSFER TYPES (BY
(
HARDWARE REALISATION):
1) By timing
•
•
Asynchronous – Speed is same like slowest device
Synchronous – Speed is derived from CLK signal in definite time through the communication.
2) By line width
•
•
4.2.1
Parallel
Serial transfer
PARALLEL TRANSFER
FER
•
•
•
4.2.2
The highest transfer power but the most expensive for realization
Suitable mostly for short distances
Is used for bus in microcontroller or microcomputer
SERIAL TRANSFER
•
•
•
4.2.2.1
Slower data transfer rate than parallel but for longer distance
Cheaper realization then parallel
Low possibility of signals interference
SYNCHRONOUS SERIAL TRANSFER
T
•
•
•
•
4.2.2.2
High transfer power
Synchronization is common for transceiver and receiver
Character aren’t separated by synchronisation envelope
It can be secured by parity bits
ASYNCHRONOUS SERIAL TRANSFER
•
•
Synchronization is sent at start of each carried character
Characters aren’t carried regularly
Fig. 26: Asynchronous serial transfer
4.3
TRANSFER ERRORS
Creation of errors is random process but we can
can reduce effect of interferences to data transfer with:
•
•
Realization of transfer wiring
Choosing of security code
a) Detect type codes (Parity, CRC)
b) Self repair type codes (Reed-Solomon,
(Reed
Forward error correction)
Page 21
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
5
ADDRESS DECODERS
CSROM
Adresový
dekodér
Address decoder
A12÷A15
CSRAM
RAM
WE
OE
Addresssběrnice
bus
Adresová
CPU
TMS
320C50
OE
A0÷A12
A0÷A12
Data bus
Datová
sběrnice
R/W
ROM
D0÷D15
Control
bus
Řídicí sběrnice
RD
WR
D0÷D15
Fig. 27: The address decoder using example.
5.1
FULL ADDRESS DECODERS
When we have full decoding, the ADRAi address has assigned only one signal of the DEADRi and vice
versa. Fig. 28 shows connection of the full address decoder for address ADR = 11101111. Fig. 29 is an example
of the full address decoder based on the 74138 circuit. For this decoder, the following assignments:
DEADR0 = 0F8h, DEADR1 = 0F9h ... DEADR7 = 0Ffh
74 LS138
A0
A1
A2
A3
A4
A5
A6
A7
&
D EADR\
A0
A1
A2
A3
A4
A5
A6
A7
1
5.2
1
2
3
4
&
6,11,12
5V
Fig. 28: Full address decoding.
1
A
2 B
3 C
0
1
2
3
4
5
6
7
15
DEADR0\
7
DEADR7 \
6
G1
4
/G2
5
/G3
74LS30
Fig. 29: Full address decoding with 74138.
INCOMPLETE ADDRESS DECODERS
If we have incomplete decoding, some values of the system addresses aren’t considered because to signal
DEADRi belongs address space ADRk, where k = 1, 2, 3... This address decoder is cheaper, but requires careful
address assignment. Two completely different addresses in the program may in fact address the same circuit.
Page 22
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
A0
A1
A2
A3
A4
A5
A6
A7
74LS138
A0
A1
A2
A3
A4
A5
A6
A7
1 A
2 B
3
C
5V
0
1
2
3
4
5
6
7
15
7
DEADR0\
DEADR7\
74LS138
1 A
2
B
3
C
6
G1
4
/G2
5
/G3
5V
0
1
2
3
4
5
6
7
15 /CS0
14 /CS1
13 /CS2
6
4 G1
/G2
5
/G3
Fig. 31: Incomplete address decoding.
Fig. 30: Incomplete address decoding.
On figure 30, DEADR0 output signal is generated for each address having AB0 to AB2 = 0. For example
addresses 00h, 08h, 10h, etc. addresses are equivalent and belong to the same address space. It is not important
which one we use in the program. The result will be a selection of the same circuit. Another variant of
incomplete addressing decoder is shown on figure 31. The selection signals define the address space of the
following areas CS 0 = 00h ÷ 1Fh, CS1 = 20h ÷ 2Fh CS 2 = 30h ÷ 3Fh. These decoders are very often used for
allocating memory spaces for different types of memory (RAM EPROM., FLASH, etc.) or for additional
peripherals in microcomputer system.
5.3
THE ADDRESS DECODER WITH LINEAR ADDRESS ASSIGNMENT
The decoder principle is that to the selection signal on the output are assigned addresses in individual
(chronicle) orders. It means that DEADRi = ADRAi. One of the frequently used linear decoder with address
assignment is shown in figure 32. The 15-bit address is used to split 64kB address space into two halves. This is
not a linear assignment for both of these areas but only for space from 0h to 7FFFh. Decoding the second half
requires a 74LS04 inverter. Memory can be e.g. type 27C256 or 62256.
A1÷A14
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
1
A1÷A14
RAM
D1÷D8
/OE
/WE
/CE
EPROM
D1÷D8
/OE
/CE
Fig. 32: Address decoding with linear address assignment.
Page 23
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
6
MICROCONTROLLER AND COMMUNICATION WITH PERIPHERY
Periphery is all devices connected to microcontroller outside sometimes inside and provides
communication between microcontroller and environment. It means A/D and D/A converters, buttons, displays,
amplifiers, counters and etc... Communication control we can divide as:
•
•
Program initiates communication – program need data from environment
Periphery initiates communication – periphery need to send data to microcomputer
If move request for communication will come, it’s good to know which periphery can or can′t communicate
at the moment.
6.1
PROGRAM CONTROL OF COMMUNICATION
Communication is controlled by program with status bit or pin. As example is acquire data from keyboard.
It is used for less frequently (0.1 – 0.5 s) situations.
6.2
CONTROL OF COMMUNICATION BY INTERRUPTS
If periphery need communicate it actives interrupt signal incoming into processor. If processor detects
interrupt request it does an interrupt routine. After routine it continues with previous program. Today
microcontrollers use interrupt controller (IC):
a) IC provides receiving of interrupts
b) IC assign a priority levels to each interrupt
c) IC masks interrupts (mask defines interrupts which are currently active)
Fig. 33: Interrupt controller.
7
SERIAL INTERFACES
Are used for two basic purposes:
•
•
Communication between microcomputer systems, length 1 m to several 100 m (RS232, RS485, CAN)
Communication between integrated circuit or microcomputers on short distances (about several metres)
(SPI, I2C )
Page 24
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
7.1
RS232
•
•
Two signals: RxD (Receive data), TxD (Transmit data)
Two levels: log. 1 (H) – marking state,
state log. 0 (L) – space state
Fig. 34: RS232 logical levels.
•
•
Max cable length is 15 m or cable with 2500 pF capacity (with quality cable 50 m) all with 19 200 Bd.
For using TTL or CMOS circuit we have to use adaptation circuit to RS232 (MAX 232).
232
MAX232:
The MAX232 is an integrated circuit that converts signals from an RS-232
RS 232 serial port to signals suitable for
use in TTL compatible digital logic circuits. The MAX232 is a dual driver/receiver and typically converts the
RX, TX, CTS and RTS signals.
The drivers provide RS-232
232 voltage level outputs (approx. ± 7.5 V) from a single + 5 V supply via on-chip
charge pumps and external capacitors. This makes it useful for implementing RS-232
RS 232 in devices that otherwise
do not need any voltages outside the 0 V to + 5 V range, as power supply design does not need to be made more
complicated just for driving the RS-232
232 in this case.
7.2
RS422
•
•
•
It can be used for extend RS232 up to 1600 m
Branch-able
Voltage difference is carried on TP(Twisted
TP
pair)
Fig. 35: Connection scheme of RS422
7.3
RS485
•
•
Only one TP for two-ways
ways transfer (trigger of direction)
Up to 128 devices
Fig. 36: Connection scheme of RS485
Page 25
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
7.4
CURRENT LOOP
•
•
•
7.5
For the longest distances
Current loop 0/20 mA, highly resist to interference
Hundreds of meters, can be used for RS232
USB
•
•
•
•
•
Low speed – 1.5Mbit/s, Full speed 12Mbit/s, High speed 480Mbit/s
Uses +5V, GND, D+, D- (differential transfer type) (on D+, D- are differential signals)
Up to 127 devices
Connector types – A-type, B-type, mini USB, micro USB
Max power take-off is 500mA, normal is 100mA
Fig. 37: USB connector types and transfer speed
7.6
SPI INTERFACE
This interface is used for external memory connection, A/D or communication between microcomputers (2
or more). Circuits/microcomputers are connected through 4 signals:
•
•
•
•
MOSI (Master Out, Slave In) – Master’s MOSI data output is connected to slave’s MOSI input
MISO (Master In, Slave Out) – Master’s MISO data input is connected to slave’s MISO output
SCK (serial clock) – Master’s SCK output is connected to SCK input of all slaves
SS (slave select) – Each circuit has an input Slave SS (Slave Select) to select the circuit. If the SS in an
inactive level, the SPI interface circuit is disabled and its output MISO is high-impedance condition.
Inputs SS of individual circuits are separate wires connected to the master circuit. If the master circuit is
microcontroller, the wires are connected to one of its ports. So you can easily select circuit, which is
connected at the time of communication.
Page 26
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
SPI conception:
Fig. 38: SPI conception.
Fig. 39:: Read from Memory with using SPI.
SPI
Fig. 40: Write into Memory with using SPI
I 2 C INTERFACE
7.7
The mostly used to connection between integrated circuits. I2C makes bi-directional
directional commutation with using
2 wires.
•
•
•
•
•
Only one station can transfer data at one time
2 signals - SDA – Serial data,
data SCL – Serial clock
Max clock frequency is 100 kHz, in new types 400kHz or 1MHz
Multi-master interface
Max wire capacity 400pF
Fig. 41: SPI conception
Page 27
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
7.7.1
I 2 C COMMUNICATION
In idle state are H on SDA and SCL, data are changed only if SCL is in H). Start condition if SDA is
changed from H to L. Stop condition if SDA is changed from L to H if SCL is in H.
Fig. 42: Slave data write.
Fig. 43: Read from slave.
7.7.2
I 2 C MULTI-MASTER MODE
More than one master is used so communication needs to be arbitrated (Collision detection method is used).
Every master monitors the bus for start and stop conditions, and does not start a transmitting if another master is
communicating. If two masters start transmission in the same time arbitration occurs.
Fig. 44: Arbitration on I2C
7.7.3
I 2 C ADDRESSING
Every station in the system has own unique 7 bits address. After detect the starting condition all circuits
compare their address with an address which is on the bus. If any of the stations identify own address, data
belong to it and the station has to confirm the address with ACK bit. Then it can send/transmit more data.
7.7.4
ACKNOWLEDGE
Acknowledging each transmitted byte (including address) is followed by sending one ACK bit. If the g
station doesn’t receive confirmation, then ends transition with STOP condition.
Page 28
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
8
SEMICONDUCTOR MEMORY
Semiconductor memory is an electronic data storage device implemented on a semiconductor-based
integrated circuit. Examples of semiconductor memory include non-volatile memory such as Read-only memory
(ROM), magneto resistive random access memory (MRAM), and flash memory. It also includes volatile memory
such as static random access memory (SRAM), which relies on several transistors forming a digital flip-flop to
store each bit, and dynamic random access memory (DRAM), which uses one capacitor and one transistor to
store each bit. Shift registers, processor registers, data buffers and other small digital registers that have no
memory address decoding mechanism are not considered as memory.
8.1
DIVISION ACCORDING TO MEMORY ACCESS
•
•
•
RAM – Random Access Memory
SAM – Serial Access Memory
Memories with special ways of accessing:
a)
b)
c)
d)
e)
8.2
Two or more gateway memories
Associative memory respectively CAM memory – Content Addressed Memory
Memory type of stack also called Cell memory, Stack or LIFO (Last In - First Out)
Memory type front known as FIFO (First In - First Out)
Memory with combined control which allows random access. In principle belongs to the RAM
but the switch circuits enable the automatic increment/decrement address. Then allow the
delivery address only to realize fast sequential access to the entire sequence of adjacent
memory locations (transmission data block).
DIVISION ACCORDING TO READ/WRITE POSSIBILITY
•
•
8.3
RWM – Read Write Memory
ROM – Read Only Memory
a) ROM – Data are written in production.
b) PROM – Programmable ROM. Data can be recorded for the first time by the user.
c) EPROM – Erasable PROM. User can erase and again write data to memory. Memory can be
deleted by ultraviolet radiation throw small window on the package.
d) EEPROM – Electric Erasable PROM. User can erase and again write data to memory.
Memory can be deleted by electric voltage.
DIVISION ACCORDING TO ELEMENTARY MEMORY CELLS PRINCIPLE
•
•
SRAM – Static Random Access Memory. SRAM store data all the time when is connected to a source
of electrical power. SRAM memory cell is implemented as a bistable flip-flop. It means a circuit that is
always in one of two possible states, which determine stored value, 1 or 0.
DRAM – Dynamic Random Access Memory. In DRAM, information is stored using electric charge on
the capacitor. This charge has a tendency to discharge even when the memory is connected to an
electrical supply. To avoid this charge and thus the loss of stored information, it is necessary to
periodically perform the refresh, i.e. reviving the memory cell. This function performs any of the
circuit’s chipset.
Page 29
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
9
MICROCONTROLLER AND ANALOG ENVIRONMENT
9.1
METHODS OF CONNECTING THE MICROCONTROLLER TO ANALOG
ENVIRONMENT – ANALOG INPUT
For connection of microcontroller to analogue environment it is needed:
•
•
•
•
•
Amplifying signal
Converting signal to other type (Current to Voltage)
Sampling of signal
Choosing the channel – multiplexing
Signal to noise ration suppression
Fig. 45: Decentralized analogue inputs of microcontroller.
Fig. 46: Centralized analogue inputs of microcontroller
Page 30
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
9.2
ANALOG CONVERTER TYPES
Digital to analog converter is a circuit which generates an output digital number derived from the input
analog signal in respect of the analog reference quantity. The output number can be presented in a parallel or
serial form.
9.2.1
PARALLEL A/D CONVERTER
This type of D/A converter is the fastest converter but the most expensive. There is created so many voltage
references accordingly how many levels we want to recognize.
Fig. 47: Parallel A/D converter
Number of resistors is 2n, number of comparators is (2n – 1) and there are 2n voltage levels. Voltage
reference is divided by voltage divider which is consisted from resistors of same values and this creates 2n
voltage levels. Conversion time is about nanoseconds.
9.2.2
COMPENSATIONAL A/D CONVERTER
These types of converters consist of D/A converter, whose output is compared in the comparator transferred
to the input signal. Input of the D/A converter is attached to a control element whose function is to create a
number. This number converted to analogue value with D/A converter has to be equal to the value of the input
signal. There are several approaches how to create the control element and this strategy.
Fig. 48: Control el. makes number which after D/A converter is equal as VIN.
Page 31
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Division of the compensational A/D converter by control element strategy:
a)
Incremental count method – control element is up-counting counter. This counter starts every counting
from zero and count-up until the number (after D/A conversion) is equal to input value then conversion
stops. Time of conversion depends on size of VIN.
b) Keep track method (Two-way counter) – Up-down counter is used and it increases or decreases its
value according with input signal.
c)
Method of gradual approximation (Register of gradual approximation) – Method comes from method of
halving range. At beginning RGA sets 1 to most significant bit only (rest of bits are set to zero) so we
have half of maximum voltage range if it is lower than VIN RGA change 1 to 0 then RGA continues by
setting second bit. Time of conversion is conversion time of one bit multiply with bit count.
Fig. 49: Control element strategy
9.2.3
INTEGRATING CONVERTER
These converters are characteristic by very long convert time (1 to 10 ms) but are very resistant to noise
signals and are very accurate (most used in measurement applications).
Fig. 50: Principle of Integrating A/D converter
Converter is based on integrator I, which integrates the measured signal VIN for constant amount of time
when is n-bit counters filled up with clock pulse of frequency f. The output voltage value of the integrator is
proportional to the mean value of measured voltage VIN. After filling the counter, the switch connects integrator
to the input reference voltage -VREF (reverse polarity) and counters counting the time for which the integrator
output reaches the zero. Then the counting stops and the contents of counter is essentially resulting number N.
This value is proportional to the mean value of input voltage.
Page 32
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
9.2.4
SPECIFICATIONS OF A/D
A
•
•
•
9.3
Resolution (Depends on number of levels, Resolution = 1/2n )
Conversion time
Linearity
ANALOG OUTPUT
Realisation of output channels is possible to do with:
•
•
Parallel placing of more the D/A converters
Central D/A converter with demultiplexed
demultiplex outputs with analog memory
Fig. 51:: Analog outputs with separate D/A
converters
9.4
Fig. 52:: Analog outputs using sampling amplifiers
D/A CONVERTER TYPES
In the implementation of the D/A converter it has to be assigned 2n values of analog variables to n-bit
n
number. It is used the fact that an integer number can be divided into individual bits, with their weight and the
number is expressed as the sum of:
Fig. 53:: Principle of D/A converter
Replacing the numerical weight of each bit by corresponding quantum, such as el.. current makes possible
to add switches to power supplies which are controlled by relevant bit of the converted numbers. Last operation
is adding which create the resulting current and then current to voltage conversion.
Page 33
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
9.4.1
D/A WITH RESISTOR NET
Fig. 54: D / A converter with resistive weight networks
Practical implementation of the converter is a little different. Current sources are replaced by a single
reference voltage and resistors switched by individual bits which are connected to input operational amplifier.
Disadvantage is using of many different resistor values. Converter output voltage corresponds to the value of the
transferred number:
9.4.2
D/A WITH R-2R
Only two values of resistor are used. On the next switch is always half current.
Fig. 55: Resistors with values R and 2R
9.4.3
•
•
•
•
SPECIFICATION OF D/A
Resolution (8 bits converter => 100/256 = 0,4%)
Accuracy
Convert time (Number of converted word per second)
Range (Maximum voltage amplitude)
Page 34
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
9.5
9.5.1
•
•
•
•
•
CODES FOR A/D
D AND D/A
D
CONVERTERS - UNSIGNED
NON NEGATIVE
EGATIVE NUMBERS (E.G.
(E.G INTEGER) (UNSIGNED)
Every bit has exact weigh express as power of two ao has weigh 2o, a6 – 26, etc.
The smallest number – 0
The greatest number – 2n – 1
Difference of two closest numbers is 1
Count of all numbers - 2n
Fig. 56: Non negative number
9.5.2
•
•
•
•
•
•
9.6
9.6.1
•
•
•
NON NEGATIVE REAL NUMBER
NU
(E.G. FRACTION)
We use 2-m instead of 20
Negative power of 2 → fraction number
numb 1/2, 1/4 etc.
The smallest number 0
The greatest number 2-m (2n – 1)
Difference of two closest numbers is 2-m
Count of all numbers 2n
CODES FOR A/D
D AND D/A
D
CONVERTERS - EXPRESSION OF MARK (+,-)
(SIGNED)
ABSOLUTE VALUES
The highest bit is sign (0 mean +, 1 mean -)
Other bits represent absolute value of number
But express two types of zeroes
Fig. 57: Absolute signed values
9.6.2
•
•
•
ONE′S
S COMPLEMENT ( 1 X)
Used
sed to represent negative numbers
The highest bit is sign (0...+, 1...-)
1...
There is positive and negative zero
Page 35
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
Fig. 58: One′s complement (1x)
9.6.3
•
•
•
TWO′S
S COMPLEMENT ( 2 X)
The highest bit is sign (0...+, 1...-)
1...
Only one representation of zero
The most used
Fig. 59: Two′s complement (2x)
9.6.4
•
•
ONE HALF OF INTERNAL
The highest bit is sign (0...-,, 1...+)
One zero
Fig. 60: One half of interval
10 CPU, MCU AND MCU SYSTEMS
10.1 DIVIDING BY
Y PARAMETERS
1) CPU
• Its
ts open for system (has no peripheries)
• High price but high computing power
• High power consumption
2) MCU
• Low
ow prices, low power consumption
• Small dimension
• Low possibility of extend
3) DSP
• Like CPU + MCU
• High speed computing operation in fixed or floating point
• Price depend on peripheries
Page 36
VŠB-TU OSTRAVA
Department of Electronics (430)
Microcomputer Control Systems I
10.2 DIVIDING BY INSTRUCTION SET
10.2.1 CISC (COMPLEX INSTRUCTION SET COMPUTER)
•
•
•
Processor with complete instruction set
Various instructions for various operations
Variable instruction length
10.2.2 RISC (REDUCE INSTRUCTION SET COMPUTER)
•
•
•
High computing power with small count of instruction
It is hard to make complex operation with so simple instruct
Fixed length of instruction
10.3 DIVIDING BY ARCHITECTURE
10.3.1 VON NEUMANN ARCHITECTURE
•
•
•
Only one bus for all operation
Only one memory for PROGRAM and
DATA (we can rewrite DATA with Program)
•
•
Every periphery has own bus
Parallel transfer of data and instr. ⇒ higher speed
Fig. 61: Von Neumann architecture
10.3.2 HARVARD ARCHITECTURE
Fig. 62: Harvard architecture
Page 37