Download Hardware Architecture Modeling for Massively Parallel Real

Hardware Architecture Modeling for
Massively Parallel Real-time System Scheduling
PhD proposal (under CIFRE contract)
Zhen Zhang, Arnaud Lallouet, Chong Li
Huawei Technologies – France Research Center
2012 Labs / Central Software Institute / DAL
20 quai du Point du Jour, 92100 Boulogne-Billancourt
Dumitru Potop-Butucaru
INRIA, team AOSTE
2 Rue Simone IFF, 75012 Paris, France
Context
Huawei is a leading global ICT solutions provider.
Through our dedication to customer-centric innovation and strong partnerships, we have established
end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud
computing fields. We are committed to creating maximum value for telecom carriers, enterprises
and consumers by providing competitive ICT solutions and services. Our products and solutions
ranging from processors, servers to mobile phones have been deployed in over 170 countries, serving
more than one third of the world’s population. Huawei has launched in 2014 the French Research
Center (FRC), focusing on mathematics and algorithmic science, with more than 80 researchers. The
Distributed Algorithms Lab (DAL) develops algorithms and programming tools to support massively
parallel big-data applications, high performance machine learning, computer vision and real-time
embedded technologies.
Established in 1967, INRIA is the only French public research body fully dedicated to computational
sciences. Combining computer sciences with mathematics, INRIAs 3,500 researchers strive to invent
the digital technologies of the future. Educated at leading international universities, they creatively
integrate basic research with applied research and dedicate themselves to solving real problems, collaborating with the main players in public and private research in France and abroad and transferring
the fruits of their work to innovative companies. The researchers at Inria published over 4,450 articles in 2012. They are behind over 250 active patents and 112 startups. The 180 project teams
are distributed in eight research centers located throughout France. The AOSTE research team
(http://www.inria.fr/en/teams/aoste) promotes the use of synchronous formalisms for the high-level
modeling, the full formal design, and the distributed real-time implementation of embedded software.
The team builds upon prior work by its members on the SyncCharts, Esterel, and SynDEx formalisms,
which included extensive algorithmic studies on dedicated modeling, compilation, analysis, and optimization techniques. Our main expertise is in the fields of formal semantics of synchronous reactive
systems, and optimized mapping (i.e. distribution and scheduling) between application algorithms
and physical architectures descriptions.
Project
Facing forthcoming Artificial Intelligence needs, future embedded real-time systems will become
massively parallel both on the hardware and the software part. Some new large-scale intelligent
applications will have hard real-time constraints on components such as control, image processing,
object recognition, machine learning, deep learning, multiple-sensor information fusion and on-line
AI decision. It will be very hard to implement such applications on a massively parallel hardware, for
example a many-core system, while meeting all critical constraints. Therefore early stage scheduling
of functional tasks, communications relying on non-functional constraints on an abstract hardware
architecture model will be an efficient solution at all steps of system design, implementation, verification, validation and test.
In this project, we will study concurrent functional specification models, such as dataflow synchronous
[5], bridging parallel models such as BSP [7], Multi-BSP [8, 6] or PRAM, and state-of-the-art scheduling algorithms (based on both constraint solving engines or dedicated heuristics [2]) on top of such
models. Our goals are to:
• Define a general model for massively parallel execution platforms
• Define efficient scheduling algorithms.
Constraint Programming has already been used, by numerous research groups, to model and solve
scheduling problems under incresingly complex non-functional requirements (real-time, allocation,
etc.). However, recent work by our teams [3, 4] and others [1] has shown that existing modeling
approaches and solvers do not scale beyond certain limits, and put into evidence factors that influence
these limits – the problem size, its complexity, or the system load. In particular, our work has
shown that the allocation and scheduling of parallelized real-time applications onto massively parallel
hardware under high system load is untractable in practice.
This thesis proposal aims at better understanding the limitations of constraint solving techniques
and the factors influencing the empyric complexity of scheduling problems. Based on this better
understanding, our objective is to extend the reach of such approaches by means of improved encoding
of the scheduling problems and by improvements to constraint solving techniques/engines. We also
aim at developing efficient dedicated heuristics for solving the considered problems.
Student
We are seeking for a Master’s degree graduate in Computer Science from a top-level university/engineer
school. The candidate shall have a strong background in more than one of the following fields:
real-time systems, artificial intelligence, computer vision, parallel algorithms, machine learning, deep
learning, graph algorithms, constraint programming, image processing, etc. In addiction, the right
person should love the practice as well as the theory: having a good coding skill is essential to transfer
beautiful algorithms to perfect programs.
Please send by email to the contacts hereafter an archive containing a CV, a motivation letter, at
least two recommendation letters, all undergraduate and graduate marks and a detailed description
of the courses followed. Reports of scholar or personal projects, as well as any achievement, prize or
distinction will be appreciated.
Work environment
The work will take place in the offices of Huawei FRC (located in Boulogne-Billancourt) and Inria
Paris (located in Paris). Supervision will be done by Dr. Zhen Zhang, Prof. Arnaud Lallouet
and Dr.-Ing. Chong Li from the Huawei part and by Dr. (HDR) Dumitru Potop-Butucaru from the
INRIA part. Huawei FRC provides a challenging scientific environment, cutting-edge parallel hardware
and software, digital library, travel funds, company restaurant and a salary competitive with similar
positions in French industry. The successful candidate will receive a job offer in 2016, and the actual
doctoral work will begin as soon as possible thereafter.
Contact
Zhen Zhang, Huawei Technologies, [email protected]
Arnaud Lallouet, Huawei Technologies, [email protected]
Chong Li, Huawei Technologies, [email protected]
Dumitru Potop Butucaru, INRIA, [email protected]
References
[1] Alessio Bonfietti, Michele Lombardi, Michela Milano, and Luca Benini. Maximum-throughput
mapping of sdfgs on multi-core soc platforms. J. Parallel Distrib. Comput., 73(10):1337–1350,
2013.
[2] Thomas Carle, Manel Djemal, Dumitru Potop-Butucaru, and Robert De Simone. Static mapping
of real-time applications onto massively parallel processor arrays. In 14th International Conference
on Application of Concurrency to System Design, Proceedings ACSD 2014, June 2014.
[3] R. Gorcitz, E. Kofman, T. Carle, D. Potop-Butucaru, and R. de Simone. On the scalability of
constraint solving for static/off-line real-time scheduling. In Proceedings of FORMATS 2015,
Madrid, Spain, September 2-4, 2015, 2015.
[4] Sylvain Jubertie, Emmanuel Melin, Jérémie Vautard, and Arnaud Lallouet. Mapping heterogeneous distributed applications on clusters. In Emilio Luque, Tomàs Margalef, and Domingo
Benitez, editors, Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference,
Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings, volume 5168 of Lecture
Notes in Computer Science, pages 192–201. Springer, 2008.
[5] Edward A. Lee and David G. Messerschmitt. Synchronous data flow. Proceedings of the IEEE,
75(9):pp. 1235–1245, September 1987.
[6] Chong Li and Gaétan Hains. SGL: Towards a bridging model for heterogeneous hierarchical
platforms. Int. J. High Perform. Comput. Netw., 7(2):139–151, April 2012.
[7] Leslie G. Valiant. A bridging model for parallel computation. Commun. ACM, 33(8):103–111,
August 1990.
[8] Leslie G. Valiant. A bridging model for multi-core computing. J. Comput. Syst. Sci., 77(1):154–
166, January 2011.