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Budapest University of Technology and Economics Faculty of Mechanical Engineering Department of Automation and Applied Informatics INVESTIGATION OF A POWER FACTOR CORRECTION CONVERTER FED BLDC MOTOR DRIVE TDK Conference 2015/16. Author: Supervisor: Levente Zsolt Pap Péter Pál Stumpf, Phd. 2 Investigation of a Power Factor Correction Fed BLDC Motor Drive TABLE OF CONTENTS Table of Contents ..................................................................................................................... 2 1 Introduction ........................................................................................................................... 4 2 Theoretical Background of Power Factor Correction ....................................................... 6 2.1 Power Factor ..................................................................................................................... 6 2.2 PFC ................................................................................................................................. 12 2.3 General Classification of PFC ........................................................................................ 12 2.4 Boost Converter as PFC ................................................................................................. 13 2.5 Buck-Boost Converter as PFC ........................................................................................ 16 3 PFC Bridgeless Buck-Boost Converter ............................................................................. 20 3.1 Operation During Positive and Negative Half Cycles .................................................... 20 3.2 Operation During a Complete Switching Cycle ............................................................. 21 3.3 Design of PFC Bridgeless Buck-Boost Converter ......................................................... 23 3.3.1 Design of Input inductors ........................................................................................ 23 3.3.2 Design of DC Link Capacitor .................................................................................. 24 3.3.3 Design of Input Filter .............................................................................................. 25 3.4 Control of PFC Bridgeless Buck-Boost Converter......................................................... 26 4 PMBLDC Motor .................................................................................................................. 28 4.1 Electronic Commutation ................................................................................................. 29 4.2 Modelling a BLDC Motor .............................................................................................. 31 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive ................................... 33 5.1 Performance simulation using Matlab/Simulink ............................................................ 34 5.1.1 BLDC Motor parameters ......................................................................................... 34 5.1.2 Power Factor Measurement in Simulink ................................................................. 35 5.1.3 Steady-State Performance ....................................................................................... 36 5.1.4 Dynamic Performance of the Drive ........................................................................ 39 5.1.5 Performance under Supply Voltage Variation ........................................................ 43 Table of Contents 5.1.6 Comparative Analysis of DBR Drive ...................................................................... 43 6 Conclusion ............................................................................................................................ 45 Literature ................................................................................................................................ 47 3 4 Investigation of a Power Factor Correction Fed BLDC Motor Drive 1 INTRODUCTION Nowadays efficiency and cost are the major concerns in designing and developing low-power applications, such as fans, air conditioners, blowers, mixers and other household devices. Due the several advantages of brushless direct current motors (BLDC) operating under these circumstances, a continuous growth in the number of applications has been noticed during the past years. These features are high efficiency, high flux density per unit volume, low electromagnetic interference, silent operation and low maintenance requirements. However, the use of BLDC motors is not limited to domsestic applications only. They provide suitable solutions also for medical equipment, motion control, transportation or many other industrial tools. As energy consumption gained such an importance all over the world in order to fulfill the enormous demand, strict regulations have been announced by worldwide organizations like International Electrotechnical Commission (IEC) regarding the power quality of applications. Therefore, more advanced and “supply friendly” applications need to be developed by manufacturers. As a consequence of this requirement, different kind of power quality correction techniques are available today for applications using BLDC motor drives, but the most common is the Power Factor Correction (PFC) converter. PFC improves the power quality at ac mains as it reduces the total harmonic distortion (THD) in the supply current. The aim of my TDK project is to investigate a bridgeless PFC converter topology suitable for low-power BLDC motor applications. The proposed converter reduces the switching losses compared to other PFC topologies by minimizing the conducting elements during a cycle, therefore improving the efficiency. The bridgeless PFC transfers energy from the ac mains to the voltage source inverter (VSI), which controls the electronic commutation of the BLDC motor. The speed control of the motor is achieved by controlling the input direct voltage of the VSI, thus there is no need to control the transistors of the VSI by Pulse Width Modulation. It greatly decreases the switching loss as the required switching frequency of the converter equals to the electrical frequency of the BLDC. In the second chapter the theoretical background of the power factor and its correction is introduced. It is followed by introducing two most commonly used PFC topology, the boost 1 Introduction and the buck/boost with diode bridge rectifier. The third chapter presents the bridgeless PFC converter. The chapter shows the main design steps for selecting the passive elements. The fourth chapter deals with the theoretical background of BLDC motors. The fifth chapter presents the complete simulation model and the results of the simulation study. The results are compared with a conventional diode bridge rectifier fed version of drive with the same motor to illustrate the differences between the two power converters. The conclusions can be found at the end of the paper. 5 6 Investigation of a Power Factor Correction Fed BLDC Motor Drive 2 THEORETICAL BACKGROUND OF POWER FACTOR CORRECTION 2.1 POWER FACTOR The power of an electrical system consists of three components [1]: real power, P [W] reactive power, Q [var] apparent power, S [VA] The relation between these components is illustrated in Figure 2.1: Figure 2.1 Relation between the components of power P, or real power is what the system actually consumes as electric power. This is transformed into different form of powers used for heating, lighting or moving. Q is the reactive power, responsible for creating and maintaining the electromagnetic field, closely related to an inductive load. S, or apparent power consists of the two previous. It is the product of the rms values of voltage and current of the load. S V I [VA] (2.1) Apparent power should be considered when designing an electric device, as I current flows through the electric circuit, therefore the heat loss is I2R. To accomplish proper insulation in the device, the value of U is taken into account. Besides, U determines the magnitude of magnetic induction in the machine. The relation between S, P and Q with equations: P S cos (2.2) 2 Theoretical Background of Power Factor Correction Q S sin (2.3) S P2 Q2 (2.4) φ is the angle between the voltage and current vector. In case of sinusoidal voltage and current, cosφ is the power factor. The ratio of the apparent power and the real power is denoted by the power factor, as it can be seen in equation (2.2). An important role is associated with it regarding the production, transport and consumption of electrical energy. To achieve efficient electrical energy transport, the aim is to maximize average power while minimizing rms voltage and current in order to minimize losses. The power factor shows the efficiency of energy transport: 𝑝𝑜𝑤𝑒𝑟 𝑓𝑎𝑐𝑡𝑜𝑟 = 𝑎𝑣𝑎𝑟𝑎𝑔𝑒 𝑝𝑜𝑤𝑒𝑟 (𝑟𝑚𝑠 𝑐𝑢𝑟𝑟𝑒𝑛𝑡)(𝑟𝑚𝑠 𝑣𝑜𝑙𝑡𝑎𝑔𝑒) If the value of the quotient is lower than 1, phase delay or harmonic distortion or both describes the input side, as both of them decreases the power factor. Harmonic distortion occurs, when the current is not clearly sinusoidal. In this case, cosφ does not equal the power factor, as it only does when the distortion factor is 1. Harmonic distortion means that the current (and the voltage) curve is the superposition of the fundamental sinus component and its harmonics. The frequencies of these harmonics are the product of the fundamental frequency and positive integers. They are noticeable as a constant, continuous electrical noise in the system. Consequently, harmonics differ from electric line noises that are caused by huge power consumption and result in transient noises. Some sources of current harmonic distortion [3]: power electronics devices (rectifiers, uninterrupted power supplies, frequency adjustable drives, switching mode power supplies, etc.) inductive devices with saturation (generators, motors, transformers, etc.) Problems caused by harmonic currents: malfunction of the control system overheating of condensers, transformers, motors and other electric components noise effect in the electric devices nearby (for example computer) failure of sensitive electronic components 7 8 Investigation of a Power Factor Correction Fed BLDC Motor Drive In case of linear resistive load, the harmonics of current are in phase an directly proportional to the harmonics of voltage. The power factor is cosφ=1, as φ=0. The harmonics support the power transport. The rms values of current and voltage can be expressed with the amplitude of the harmonics by using Fourier series: Vn2 n 1 2 (2.5) I n2 V02 Vn2 1 2 Vrms 2 2 R R n 1 2 R (2.6) Vrms V02 I rms I 02 n 1 where: V0 is the direct voltage component Vn is the amplitude of the nth voltage harmonic I0 is the direct current component In is the amplitude of the nth current harmonic R is the resistive load The real power: Vn I n V I cos n V0 I 0 n n 2 2 n1 n1 P V0 I 0 (2.7) In case of nonlinear load, rms value of current is increased by the harmonics of the current, but real power is not, which leads to reduction of the power factor. P V1 I1 cos1 2 (2.8) where: U1 is the fundamental voltage harmonic I1 is the fundamental current harmonic φ1 is the displacement angle of the current and the voltage I1 P V1 I1 power factor cos1 2 cos1 Vrms I rms 2Vrms I rms I rms With the rms value of the current: (2.9) 2 Theoretical Background of Power Factor Correction power factor I1 2 I2 I n n 1 2 cos1 (distortion power factor) (displacement power factor) 2 0 (2.10) where: I1,rms I1 2 distortion power factor = I1 2 I n2 I n 1 2 2 0 displacement power factor = cosφ1 The distortion power factor is only defined for sinusoidal voltage and can be expressed with the total harmonic distortion (THD): I n2 2 THD n2 I1 (2.11) By rearranging the previous equation: distortion power factor 1 1 THD 2 (2.12) In conclusion, the power factor is the product of distortion power factor and displacement power factor, as the following equation shows: power factor cos 1 THD 2 (2.13) where: cosφ is the displacement power factor THD is the total harmonic distortion Let us consider an example.[2] A typical way of converting ac voltage to dc voltage is the single-phase full-wave rectifier (Figure 2.2). There are two common reasons for including the dc-side L-C filter: 9 10 Investigation of a Power Factor Correction Fed BLDC Motor Drive to obtain smooth dc output voltage (large C) and acceptable ac line current waveform (large L) the filter conducts the electromagnetic interference generated by dc load (small L and C) Input current flows, when the capacitor is charged, which occurs only, when the input voltage is greater than the capacitor’s voltage. With small L values, it results in impulse-like discontinuous current conduction at the ac side. (Figure 2.3) By increasing the value of L (L>∞), the input current shape tends to be a square wave, the current conduction is continuous. (Figure 2.4) Figure 2.2 Single-phase full-wave rectifier Figure 2.3 Input current and voltage with small L Figure 2.4 Input current and voltage with large L 2 Theoretical Background of Power Factor Correction In case of continuous current conduction (L->∞): distortion power factor I1, rms 4 90.0% I rms 2 2 1 1 48.3% THD distortion power factor In case of discontinuous current conduction, as the inductance is reduced, the THD rapidly increases, and the distortion power factor decreases. Typical distortion power factor of a fullwave rectifier with no inductor is in the range of 55% to 65%, and is governed by ac system inductance. The low value of distortion power factor brings up the idea of an electric circuit, which would improve the power factor: and here comes the idea of Power Factor Correction (PFC) circuits. 11 12 Investigation of a Power Factor Correction Fed BLDC Motor Drive 2.2 PFC The aim of using PFC stage in the first step of AC-DC converters is to improve the displacement and distortion power factor, therefore to minimize the used reactive power from the supply. The load should behave like a purely resistive load from the view of ac side in order to obtain sinusoidal input current in phase with the input voltage. The result is increased power quality and also higher resultant efficiency of the machine. Advantages of PFC: higher efficiency lower peak current possibility of filtering EMI noise lower transmission of EMI common input filter for parallel supplies But also, there are disadvantages of PFC: more complex design more elements are needed, which affects reliability on the one hand and on the other hand, it makes the electrical circuit more expensive the electromagnetic and radio frequency noises caused by PFC requires additional filtering that makes the input filter more complex and expensive How does it possible for the PFC to behave like a resistive load, despite the fact that it contains reactive passive elements like inductors and capacitors, and also active switch-mode elements like MOSFETs and IGBTs? The solution is quite simple: power factor correction is only a low-frequency demand, therefore the converter should seem resistive in the low frequency range. It follows that a filtering process is required to eliminate the high frequency ripples. 2.3 GENERAL CLASSIFICATION OF PFC There are two main categories of PFC circuits in general: active and passive PFC [3]. Passive PFC contains simple reactive elements like inductors and capacitors in order to compensate the displacement angle of line voltage and current. This process is called passive power factor correction. Active PFC uses switch-mode converters and controller circuits to increase the 2 Theoretical Background of Power Factor Correction power factor and reduce the total harmonic distortion. Both methods have their own pros and contras, but active PFC seems to be a more advanced technique. Active PFC is used to compensate the distortion of supply current, mostly switch-mode converters are accomplished in them. Although they are more complex than passive PFC circuits, the development of integrated circuits and semiconductors made active PFC an affordable choose. These power electric units are able to achieve power factor as great as 99% and THD lower than 5%. Both low- and high-frequency operation active PFC topologies exist. 2.4 BOOST CONVERTER AS PFC Among the several existing PFC topologies, the boost converter is commonly used with single-phase full-wave diode bridge rectifier to improve power quality. It is a high-frequency active PFC method and often chosen because boost converter exhibits lower transistor stresses than other dc-dc converters like Buck-boost, Cuk, SEPIC, etc. Figure 2.5[4] Boost (step-up) converter As the name implies, boost or step-up converter produces higher V0 output dc voltage than VD input voltage. In steady-state assuming that the output capacitor C is sufficient large, the output voltage is almost constant. v0 (t ) V0 (2.14) The operation of the converter [4] has two main stages depending on the state of the S switch (the elements are treated as being ideal): during the interval when the switch is closed (voi=0), current flows through the inductor, as the diode is reverse biased, thus isolating the output stage. The input supplies energy to the inductor. As the switch opens (voi=VD), the diode becomes forward biased, therefore the input supplies energy, as well as the inductor, to the output stage. Depending on the value of L, there might be 3 modes of current conduction. Discontinuous (DICM), continuous (CCM) and critical current conduction (CrCM) can occur. 13 14 Investigation of a Power Factor Correction Fed BLDC Motor Drive In case of critical conduction mode, the inductor current reaches zero exactly at the end of the switching period. Figure 2.6 [4] shows the corresponding voltage and current waveforms during CCM and DICM: Figure 2.6[4] CCM and DICM waveforms In case of CCM from Figure 2.6: Vd ton (Vd Vo )toff (2.15) As: D ton ton toff (2.16) where D is the duty ratio, it follows from (2.15) and (2.16), that: V 0 1 Vd 1 D (2.17) At the boundary between DICM and CCM (presented by dotted line on the left side of Figure 2.6), the average inductor current ILB is: VT 1 1 Vd I LB iL , peak ton 0 s D(1 D) 2 2 L 2L (2.18) 2 Theoretical Background of Power Factor Correction Figure 2.7 [2] PFC with full-wave single-phase rectifier and boost converter Figure 2.7 [2] shows a typical topology of a PFC using boost converter. The aim of this approach is to achieve sinusoidal iac(t) input current in phase with vac(t) input voltage. The desired waveforms can be seen on Figure 2.8 [2]. Figure 2.8 [2] Desired waveforms of PFC Re is called emulated resistance. M(t) is the quotient of the output voltage v(t) and vg(t). M(t) can be varied with duty cycle d(t), as it describes the relation between the output and the input voltage. vac (t ) VM sin(t ) (2.19) 15 16 Investigation of a Power Factor Correction Fed BLDC Motor Drive v g (t ) VM sin(t ) M (d (t )) v(t ) V vg (t ) VM sin(t ) (2.20) (2.21) The expression above (2.21) neglects converter dynamics. To avoid distortion near line voltage zero crossing, the converter should be capable of producing M(d(t)) approaching infinity. Boost converter satisfies this requirement in CCM operation [2]: M (d (t )) v(t ) vout (t ) 1 vg (t ) vin (t ) 1 d (t ) (2.22) Since M(d(t))≥1 in the boost converter, it is required that V≥VM. The duty ratio from (2.22): d (t ) 1 vg (t ) V (2.23) The controller varies this duty cycle as necessary to make ig(t) proportional to vg(t), hence to reduce harmonics and achieve unity power factor. One drawback of the converter in BLDC motor drive application is that, the DC output voltage is higher than the amplitude of the input voltage. In single phase 220V system it is more than 310V. As the DC voltage cannot be reduced below a certain value, the BLDC drive cannot operated at lower speeds with DC bus voltage control. Furthermore BLDC motors, which have lower rated voltage cannot be used at all. The BLDC motor can be operated at lower speed (e.g. during starting) or low voltage BLDC motors can be applied only if the high DC bus voltage is chopped by controlling the transistor of the VSI of the BLDC drive. Naturally it increases the switching loss and reduce the efficiency of the drive system. 2.5 BUCK-BOOST CONVERTER AS PFC As the name implies, buck-boost converter is able to produce lower or higher output voltage than the input voltage. It can be obtained as a cascade connection of a buck and a boost converter. Therefore, in steady-state, assuming CCM operation, the voltage transfer ratio (output-to-input) is the product of the transfer ratios of the cascade connected buck and boost converters. Assuming, that these have a common duty ratio D: 2 Theoretical Background of Power Factor Correction V0 D 1 Vd 1 D (2.24) Figure 2.9 [4] Buck-boost converter When the switch is closed, input provides energy to the inductor and the diode is reverse biased. After the switch is opened, the energy stored in the inductor is transferred to the output. During this period, if the inductor current reaches zero, discontinuous current conduction appears. The resulting waveforms during CCM and DICM can be seen on Figure 2.10 [4]. Figure 2.10 [4] Buck-boost waveforms during CCM (left) and DICM (right) 17 18 Investigation of a Power Factor Correction Fed BLDC Motor Drive Assuming DICM, the voltage transfer ratio: Vd DTs (V0 )1Ts V0 D Vd 1 (2.25) (2.26) For PFC operation, buck-boost converter is commonly used with a diode bridge rectifier as it can be seen on Figure 2.11. Figure 2.11 Buck-boost converter for PFC Figure 2.12 Input current waveform The average input current according to Figure 2.12 [6]: iac ,avg (t ) D 2Ts vac (t ) 2L (2.27) 2 Theoretical Background of Power Factor Correction Equation 2.27 gives a linear relationship between average input current and input voltage, which proves, that buck-boost converter has excellent self-PFC property. The explanation is that the input current of the converter is not related to the discharging period (when the switch is in OFF state). The input characteristic of the converter also shows this useful self-PFC property on Figure 2.13. Figure 2.13 Input V-I characteristic of buck-boost converter The output voltage of the buck-boost converter can be either larger or smaller than the input voltage. Furthermore, contrary to boost topology, buck-boost converter can be used to control DC voltage and realize low speed operation of BLDC motor drive. Unfortunately, this topology has two limitations: the polarity of the output voltage is reversed, therefore the input and output voltage does not have common ground, which makes the design more complex. the power switch needs a floating drive 19 20 Investigation of a Power Factor Correction Fed BLDC Motor Drive 3 PFC BRIDGELESS BUCK-BOOST CONVERTER Buck-boost converter can be designed for PFC with bridgeless topology as well. By eliminating the diode bridge rectifier, losses associated with it also disappear, however, the circuit becomes more complex. The bridgeless buck-boost converter can be seen on Figure 3.1. Figure 3.1 PFC Bridgeless Buck-Boost converter with input filter The operation of the converter can be classified into two parts: operation during the positive and negative half cycles of supply current and operation during a complete switching cycle. 3.1 OPERATION DURING POSITIVE AND NEGATIVE HALF CYCLES The proposed bridgeless converter is a combination of two buck-boost converters. Each of them operates for the positive or the negative half cycle. Switches Sw1 and Sw2 are used for the positive and negative half cycles of supply current, respectively. During the positive half cycle switch Sw1, inductor Li1 and diodes D1, Dn are conducting. Switch Sw2, inductor Li2 and diodes D2, Dp are used for the negative half cycle similarly. The inductor currents during two Figure 3.2 [5] Inductor currents during negative and positive half cycle of supply voltage 3 PFC Bridgeless Buck-Boost Converter periods of the supply voltage are illustrated in Figure 3.1 [5]. 3.2 OPERATION DURING A COMPLETE SWITCHING CYCLE The converter is operated in DICM, therefore there are 3 stages within a complete switching cycle. The operation is discussed now for the positive half cycle of supply voltage, but also true respectively for the negative half cycle. I. In this mode, switch Sw1 conducts to charge inductor Li1. Diode D1 is reverse biased, therefore capacitor Cd is discharged by the load. Diode Dp completes the circuity, as it can be seen on Figure 3.3. Figure 3.3 Operation in stage I. II. When switch Sw1 is opened, diode D1 becomes forward biased therefore the energy stored in the inductor is transferred to the capacitor Cd. Current iLi1 is decreasing, at the end of the stage it is dropped to zero. Figure 3.4 Operation in stage II. Figure 3.4 shows the circuity during this stage. III. As there is no more energy in the inductor Li1, discontinuous it enters conduction the mode. Current iLi1 is zero, and none of the elements except Cd conducts. Capacitor Cd supplies energy to the Figure 3.5 Operation in stage III. load, therefore voltage Vdc starts decreasing until the end of the switching period. (See Figure 3.5) When switch Sw1 is closed again, the process starts over from stage I., periodically. 21 22 Investigation of a Power Factor Correction Fed BLDC Motor Drive For the negative half cycle, operation during a complete switching cycle is the same, but with inductor Li2, switch Sw2, diode D2 and Dp. The operation from stage I to stage III. is illustrated in Figure 3.6-8. Figure 3.6 Operation during negative half cycle, stage I. Figure 3.7 Operation during negative half cycle, stage II. Figure 3.8 Operation during negative half cycle, stage III. 3 PFC Bridgeless Buck-Boost Converter Figure 3.9[5] Waveforms during a complete switching cycle 3.3 DESIGN OF PFC BRIDGELESS BUCK-BOOST CONVERTER In this subsection the main design steps of a bridgeless Buck-boost converter with rated power P0 = 400 W are shown. The converter is designed to operate in discontinuous current conduction mode, consequently current in inductors Li1 and Li2 becomes discontinuous in a switching period. The rms value of supply voltage is 220 V, therefore the average voltage appearing at input side is given as [5]: Vin 2 2Vs ,rms 2 2 220 198 V (3.1) The duty ratio in case of a buck-boost converter is: D Vdc Vdc Vin (3.2) The converter is designed for dc link voltage control from 50 V (Vdc,min) to 220 V (Vdc,max), with a nominal value of 150 V (Vdc, nom). Therefore the minimum and the maximum duty ratio (Dmin and Dmax) corresponding to Vdc,min and Vdc,max are calculated as 0.2016 and 0.5263. (See (3.2) 3.3.1 DESIGN OF INPUT INDUCTORS 23 24 Investigation of a Power Factor Correction Fed BLDC Motor Drive At the boundary of CCM and DICM, critical current conduction occurs. Inductor current reaches zero exactly at the end of the switching cycle. At this point, the value of the inductor [5]: R1 D Lic1 2 fs 2 (3.3) where R is the equivalent load resistance, fs is the switching frequency (fs=40 kHz). The value of Lic1 is calculated at the worst duty ratio (Dmin), so the converter operates in DICM even at very low duty ratio. At minimum duty ratio, Vdc,min is 50 V, and the power is given [5] as 90 W (Pmin). Vdc. min (1 Dmin ) 2 50 2 (1 0.2016) 2 221.33 H Pmin 2 fs 90 2 40000 2 Lic min (3.4) To ensure a deep DICM condition, the values of Li1 and Li2 are taken less than 1/10 of Licmin. Figure 4.0 [5] shows the effect of the value of Li1 and Li2 (taken as Licmin, Licmin/2, Licmin/5, Licmin/10) on the supply current. At the higher values of the inductors, the supply current is highly distorted due to inability of operating in DCIM at the peak values of supply voltage. Hence, the values of Li1 and Li2 are selected as 18 μH. This choice Figure 4.0[5] Effect of input inductors on supply current also reduces the cost of the converter. 3.3.2 DESIGN OF DC LINK CAPACITOR The dc link capacitor Cd is responsible to supply voltage to the load. The design of Cd is governed by the second order harmonic current flowing through it. Because of the PFC operation the supply current is proportional to the supply voltage, they are in phase. Therefore, the input power is given as [5]: Pin 2VS sin t 2 I S sin t VS I S (1 cos 2t ) (3.5) 3 PFC Bridgeless Buck-Boost Converter where the term consisting cos2ωt corresponds to the second order harmonic component, which is reflected in the dc link capacitor as: ic (t ) VS I S cos 2t Vdc (3.6) The dc link voltage ripple corresponding to this current: Vdc I 1 ic (t )dt d sin 2t Cd 2Cd (3.7) For the maximum value of voltage ripple, the value of sin2ωt is taken as 1. Therefore, by rearranging equation (3.6): Cd Id 2Cd Vdc (3.8) The value of the capacitor is calculated for Vdc,nom and the allowed ripple in the dc link voltage is 3%: P0 400 Vdc,nom Id 150 Cd 943.6 F 2Cd Vdc 2Cd Vdc 2 314 0.03 150 (3.8) The capacitor is selected as 1200 μF. 3.3.3 DESIGN OF INPUT FILTER A second-order low-pass L-C filter is used at the input side with values of Lf and Cf to absorb the higher order harmonics of supply current. The maximum value of filter capacitor is calculated as [5]: C f max I peak LV peak tan( ) 400 1 tan(1) 324 nF 220 314 220 2 Where: Ipeak is the peak value of supply current Vpeak is the peak value of supply voltage ωL is the line frequency (3.9) 25 26 Investigation of a Power Factor Correction Fed BLDC Motor Drive θ is the displacement angle between supply current and supply voltage The value of Cf is taken as 330 nF. Lf consists of two parts: the source impedance (Ls) and the required additional inductor (Lreq) [5]. The value of source impedance is considered as 4%-5% of the base impedance, hence: L f Lreq Ls 1 Vs 2 1 L 0 . 04 req 2 4 2 f c C f L P0 Lreq 2 1 1 220 3.78 mH 0 . 04 4 2 20002 330 10 9 314 400 (4.0) (4.1) (4.2) fc is the cut-off frequency of the filter, which is selected as [5]: f L f c f sw (4.3) Where: fL is the line frequency fsw is the switching frequeny As the switching frequency of the PFC selected to be 40 kHz, from equation (4.3), the values of fc is selected as fsw/20, therefore fc is 2 kHz. Finally, the input filter is designed with values of Lf=3.9 mH and Cf=330 nF. 3.4 CONTROL OF PFC BRIDGELESS BUCK-BOOST CONVERTER The control unit generates PWM signals for the power switches Sw1 and Sw2 to obtain dc link voltage control. A simple voltage control loop (voltage follower approach) is utilized with digital (discrete) proportional-integral (PI) controller. First, the error signal is generated from reference voltage (Vdc*) and dc link voltage (Vdc): Ve [k ] Vdc [k ] Vdc [k ] (4.4) k represents the kth sampling instant. This error signal is given to the PI controller to calculate a controlled output voltage (Vcc) as: 3 PFC Bridgeless Buck-Boost Converter Vcc [k ] Vcc [k 1] k p (Ve [k ] Ve [k 1]) kiVe [k ] (4.5) Where kp and ki are the proportional and the integral gains of the controller. This Vcc controlled output voltage is compared with a high frequency sawtooth signal (md) to generate PWM signals for the switches: For vs>0: if md< Vcc then Sw1= ON if md≥ Vcc then Sw1= OFF For vs<0: if md< Vcc then Sw2= ON if md≥ Vcc then Sw2= OFF 27 28 Investigation of a Power Factor Correction Fed BLDC Motor Drive 4 PMBLDC MOTOR A permanent magnet brushless direct current motor is a synchronous permanent magnet machine with trapezoidal back electromotive force (EMF). The rotor of the machine is made of permanent magnet. The main benefits from this are reduced energy losses, as no energy needed for electromagnetic excitation, higher power or torque density than in case of electromagnetic excitation, higher flux density in the air gap results in better dynamic performance and the simplification of construction and maintenance also has to be noted. On the other hand, higher cost and large weight of special magnetic materials are significant drawbacks. The stator consists of three windings equally placed in 120° around the rotor and connected in star. Each of the winding are constructed with several coils that are placed in the slots to form a winding. The interconnection of the coils in the stator windings results in trapezoidal EMF. (Figure 4.1 [7]) The windings are distributed along the inner perimeter of the stator to form an even numbers of poles. Number of pole pairs defines the relation between the mechanical and the electrical rotation, as: e (t ) p m (t ) (4.1) Where: φe is the electrical rotor position angle φm is the mechanical rotor position angle p is the number of pole pairs As the angular velocities are: e (t ) d e (t ) dt (4.2) m (t ) d m (t ) dt (4.3) The relation between the electrical and mechanical angular velocities is also defined by the number of pole pairs: e (t ) p e (t ) (4.4) 4 PMBLDC Motor The electronic torque is the result of the interference of the rotor’s magnetic field and the stator’s current. However, to rotate the rotor, a proper switching of phase voltages is required. Figure 4.1[7] Back EMF in stator windings durin an electronic rotation 4.1 ELECTRONIC COMMUTATION The voltage source inverter (VSI) deals with the electronic commutation of the three phases. The position of the rotor is also essential to be known for commutation. Hall-effect sensors are placed in the motor (exactly three) that are able to sense to rotor’s position on a span of 60°. When a magnetic pole passes the sensor, a high or a low signal is generated based on the polarity of the pole. This distributes one electrical rotation into six segments. (Figure 4.2 [7]) Based on the information form these sensors, VSI connects dc link voltage over two phases, Figure 4.2 [7] Hall sensor signals 29 30 Investigation of a Power Factor Correction Fed BLDC Motor Drive therefore, dc current is drawn from the input side for 120° at the center of each phase symmetrically. On Figure 4.3 [5], VSI connects Vdc input voltage over phases “a’ and “b”. Figure 4.3 [5] Circuity when switch S1 and S4 are closed The line current iab is drawn from the capacitor Cd. The magnitude of iab depends on the applied dc link voltage Vdc, back electromotive forces (ean and ebn), resistances (Ra and Rb) and self-inductance and mutual inductance (La ,Lb and M) of the stator windings. The switching states of the switches S1-S6 are determined by hall signals Ha-Hc. Table I.[5] shows the connection between the hall-signals and the switching states for one electrical rotation (360°). Table I.[5] Switching states of VSI switches according to hall signals 4 PMBLDC Motor 4.2 MODELLING A BLDC MOTOR The model of a BLDC motor is quite similar to that of a DC motor. Always to out of the three stator windings are energized: one of them is connected to the positive, the other to the negative voltage. Therefore, the equivalent circuit consists of the line-to-line values of resistance, inductance and induced voltage. Figure 4.4 [7] shows the stator windings and the equivalent circuit. Figure 4.4 [7] Stator windings and equivalent circuit of a BLDC motor The differential equation describing the line-to-line equivalent circuit: Vdc RL Li LL L di e dt (4.5) where Vdc is the applied DC voltage RL-L is the stator line-to-line resistance LL-L is the stator line-to-line inductance e is the line-to-line induced voltage or back EMF Electromagnetic torque occurs because of the interference of the flux of the permanent magnet and the stator current: Te K t i (4.6) where Kt is the torque constant of the motor, Te is the electromagnetic torque. The electromotive force appears due to the rotating permanent magnet’s flux crossing the armature windings: 31 32 Investigation of a Power Factor Correction Fed BLDC Motor Drive e K em (4.7) where Ke is the voltage constant of the motor. The torque balance of the machine: Te J m dm Bmm Tload dt (4.8) where Jm is the inertia of the motor plus the load Bm is the viscous friction coefficient Tload is the load torque The mechanical and electrical time constant can be calculated as: te tm LL L RL L LL L RL L Kt Ke (4.9) (4.10) where te is the electrical time constant, tm is the mechanical time constant. From the equations above and by substituting the time constant into the obtained transfer function, the transfer function of the BLDC motor is: YmVdc m (s) 1 1 Vdc ( s) K e 1 sTm TmTe s 2 (4.11) The block diagram of the BLDC motor: Figure 4.5 [7] Block diagram of BLDC motor This transfer function could be used in my simulation to obtain the parameters of the speed controller, however due to lack of time, the process was neglected. 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive 5 PFC BRIDGELESS BUCK-BOOST CONVERTER-FED BLDC MOTOR DRIVE Now that the theoretical background and design of the application is discussed, a special use of a bridgeless buck-boost converter [5] will be evaluated. The converter is utilized to supply an electrically commutated permanent magnet brushless direct current (PMBLDC) motor. Energy is transported by the converter from ac mains to the input direct voltage link of the voltage source inverter (VSI), which is responsible for the electronic commutation of the motor. Figure 5.1 [5] BLDC motor drive with front-end bridgeless buck-boost converter Figure 5.1 shows the proposed BLDC motor drive. The parameters of the PFC based bridgeless buck-boost converter are designed such, that it operates in DICM to achieve inherent power factor correction at ac mains. Speed control of the BLDC motor is achieved by varying the dc link voltage Vdc of VSI, thus it operates at fundamental switching frequency, which reduces the switching losses. Reference voltage is calculated from reference speed, as it is directly proportional to the applied dc link voltage at a given load. Electronic commutation is based on the signals of position sensing hall sensors placed in the motor. An input low-pass L-C filter is needed to absorb the higher order harmonics of input current. 33 34 Investigation of a Power Factor Correction Fed BLDC Motor Drive 5.1 PERFORMANCE SIMULATION USING MATLAB/SIMULINK The performance of the proposed drive is simulated in Matlab/Simulink environment. The values calculated at PFC design are being used with a BLDC motor defined previously. Figure 5.2 Simulink model of the drive The Simulink model consists of AC voltage source, input filter, PFC bridgeless buck-boost converter, three-phase voltage source inverter, BLDC motor and control unit. The blocks titled “Decoder” and “Gates” are calculating the control signals for VSI gates from the hall sensor signals. The voltage PI controller is realized with a Matlab Embedded Function, which is called every time, when the “Trigger” block generates an impulse. This happens at a frequency of 1000 Hz (fcontroller). Inputs of the controller are the following: Ts time-step (Ts=1/ fcontroller), ωref reference speed of the rotor, Vdc dc link voltage, kp proportional gain of the controller (kp=0.002) and ki integral gain of the controller (ki=0.5). The reference voltage Vdc* is calculated by the controller from ωref and kv voltage constant: Vdc kv ref (5.2) The output of the controller is the duty ratio D, which is the input of the PWM signal generator block. This block creates the pulses for switches Sw1 and Sw2 as described previously. 5.1.1 BLDC MOTOR PARAMETERS The BLDC motor used in the simulation has the following rating: 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive Prated (rated power) 251.32 W Vrated (rated dc link voltage) 220 V Trated (rated torque) 1.2 Nm Ke (back EMF constant, or kv) 102 V/kr/min Rph (phase resistance) 14.56 Ω Lph (phase inductance) 25.71 mH J (moment of inertia) 5*10-4 kgm2 Table II BLDC Motor datasheet 5.1.2 POWER FACTOR MEASUREMENT IN SIMULINK Two components of power factor need to be measured: distortion power factor and displacement power factor. The first one is captured with the Simulink built in THD measuring block, as there is a well defined relation between THD and distortion power factor (See Equation 2.11). The displacement power factor is measured with an own Simulink subsystem illustrated in Figure 5.3. Figure 5.3 Measuring displacement power factor in Simulink Basically, the displacement angle is being measured between voltage and current. The integrators are cleared by the zero crossing of voltage and current curves, hence subtracting the output signals of the integrators gives the displacement angle in per unit. By multiplying with 2π, the displacement angle in radian is obtained. The cosine of this angle gives the displacement power factor. (Equation 2.9 and 2.10) 35 36 Investigation of a Power Factor Correction Fed BLDC Motor Drive 5.1.3 STEADY -STATE PERFORMANCE The simulation is carried out using rated conditions: Trated torque is 1.2 Nm, DC link voltage Vdc is set to be 220 V, input voltage at ac mains Vs (amplitude of vs as vs Vs sin t , where ω=50 Hz) is 311 V. Figure 5.4-5.10 shows the results for 3 periods of supply voltage. Figure 5.4 Supply voltage waveform Figure 5.5 Supply current waveform Figure 5.6 Rotor speed 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive Figure 5.7 Electromagnetic torque of the motor Figure 5.8 Current in stator phase “a” Figure 5.9 Current in inductor Li1 Figure 5.10 Current in inductor Li2 37 38 Investigation of a Power Factor Correction Fed BLDC Motor Drive Figure 5.11 shows the total harmonic spectra of supply current is, and its THD at rated conditions (Vdc=220 V). As it can be seen from this figure, PFC operation is satisfying. There are no significant harmonics represented in the current, only third order harmonic component appears. Figure 5.11 Total harmonic spectra of supply current The performance of the drive at speed control is tabulated in Table Vdc [V] N [rpm] DPF [-] THD [% of Is] PF [-] Is [A] 50 120 0.998208 12.36% 0.99067 0.52 II. DC link voltage Vdc varies from 70 303 0.999998 9.83% 0.99520 0.71 50 V to 220 V. Displacement power 90 486 0.999998 8.33% 0.99655 0.85 factor harmonic 110 670 0.999999 7.21% 0.99741 1.03 distortion (THD), speed of the rotor 130 852 0.999999 6.59% 0.99783 1.22 150 1033 0.999999 7.09% 0.99749 1.45 170 1215 0.999999 6.17% 0.99810 1.57 190 1395 0.999999 5.84% 0.99830 1.79 210 1576 0.999999 5.87% 0.99828 1.97 220 1670 0.999999 5.55% 0.99846 2.07 (DPF), total and peak value of supply voltage (Is) are also shown in Table II. Power factor at low power is larger than 0.99 which indicates good PFC behavior. By increasing the DC link Table II. Simulation results of Vdc variation from 50 V to 220 V voltage improvement in THD can be noticed. At rated Vdc (220 V), THD is as low as 5.55% and power factor nearly reaches 0.999. Figure 5.11 and 5.12 shows the total harmonic spectra at Vdc =50 V and Vdc=220 V. 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive Figure 5.12 Total harmonic spectra of supply current with V dc=50 V 5.1.4 DYNAMIC PERFORMANCE OF THE DRIVE The performance of the drive is evaluated also in dynamic conditions. First, smooth start of the motor is simulated. Due to the fact that when the motor starts to speed up, the back electromotive forces in the stator windings are built up together with the speed, a smooth starting method is required to avoid high peak current in the windings. Figure 5.13-5.14 show the results of smooth start from 0 to 50 V dc link voltage. The drive is started with no load, but when the desired dc link voltage is reached, rated load torque is applied on the motor (at 0.7 s on Figures 5.13- 5.14). Figure 5.13. Input voltage and current during start 39 40 Investigation of a Power Factor Correction Fed BLDC Motor Drive Figure 5.14. DC link voltage (Vdc), speed (N), stator current in phase a (Ia) and electromagnetic torque (Te) during start. Rated load is applied at t=0.7 s As it can be seen from Figure 5.13, with this soft-start method, high peak current is avoided. 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive 41 Figure 5.15.Supply voltage (Vs) input current (Is) DC link voltage (Vdc), speed (N), and electromagnetic torque (Te) in case of step-change in Vdc from 150 V to 200 V Figure 5.15 describes the behavior of the drive when a sudden step change occurs in reference 42 Investigation of a Power Factor Correction Fed BLDC Motor Drive Vdc*. The actual value of Vdc follows this change with an overshoot, but within the acceptable limits. As the speed of the motor is proportional to the dc link voltage, a higher speed is achieved, the speed transition is quite smooth and satisfactory. Figure 5.16 Supply voltage (Vs) input current (Is) DC link voltage (Vdc),and speed (N) in case pf supply varying the supply voltage from peak value 311 V to 160 V 5 PFC Bridgeless Buck-Boost Converter-Fed BLDC Motor Drive Figure 5.16 shows the response of the drive to a sudden change in the amplitude of the supply voltage. The voltage controller compensates the lower input voltage with higher duty ratio, therefore Vdc is kept constant with a little ripple in it. 5.1.5 PERFORMANCE UNDER SUPPLY VOLTAGE VARIATION The behavior of the drive is also simulated in practical supply conditions, ac input voltage varies from 90 V to 310 V. The important power quality values are tabulated in Table IV for different values of supply voltage. The THD values are all below the limits set up by IEC 61000-3-2 [8], hence the operation is efficient and the PFC converter is well Vs,peak [V] 90 110 130 150 170 190 210 230 250 270 290 310 DPF [-] 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 0,999999 THD [% of Is] 2.47% 2.50% 2.54% 2.67% 3.05% 3.41% 3.53% 3.93% 4.55% 4.91% 5.20% 5.55% PF [-] Is [A] 0.99969 0.99969 0.99968 0.99964 0.99953 0.99942 0.99938 0.99923 0.99897 0.99880 0.99865 0.99846 6.23 5.62 4.79 4.26 3.61 3.18 2.95 2.62 2.49 2.31 2.12 2.07 Table IV Simulation results of supply voltage variation from 90 V to designed. 310 V (Vs,peak) 5.1.6 COMPARATIVE ANALYSIS OF DBR DRIVE To demonstrate the effect of the PFC converter, a comparative analysis is carried out. The same BLDC motor is fed with a diode bridge rectifier charged capacitor, same value (1200 μF) as in case of the PFC. Also the input filter is applied to system with values Lf and Cf. The Simulink model of the drive can be seen on Figure 5.17. Figure 5.17 Diode bridge rectifier fed BLDC motor drive 43 44 Investigation of a Power Factor Correction Fed BLDC Motor Drive DC link voltage is set to be around 220 V. Figure 5.18 Input current Is , DC link voltage Vdc and speed in case of DBR Simulation results show that the input current waveform is highly distorted. This is because the capacitor can only be charged when the input voltage is greater than the capacitor voltage. Hence, the DC link voltage ripple also larger than in case of PFC (see Figure 5.16). Figure 5.19 illustrates the total harmonic spectra of input current. THD rapidly increased compared to the PFC drive (Figure 5.20), which points out the main benefit of PFC. 6 Conclusion Figure 5.19 Total harmonic spectra and THD of DBR drive input current Figure 5.20 Total harmonic spectra and THD of PFC drive input current 6 CONCLUSION Nowadays, as power quality problems have gained such an importance, a modern electric drive should fulfill all the regulations regarding their energy consumption. In addition, the cost and the performance of the drive are also significant features of it. During my TDK project I could dig myself into the topic of power factor correction that provided me deep understanding of PFC circuits and widened my knowledge of power electronics. As an electric motor drive is an interdisciplinary science field, I benefited from more fields of studies. The control of the drive requires sufficient knowledge of control theory, as well as digital electronics and signal processing. By using Matlab software for simulation I gained useful skills that could help my further research in this field. First, the theoretical background of power factor correction was described including the basics of power consumption and indicating quantities. As the demand of improving power factor was derived from the example of diode bridge rectifier, PFC circuits was introduced. Three 45 46 Investigation of a Power Factor Correction Fed BLDC Motor Drive different topologies were discussed: boost converter, buck-boost converter and bridgeless buck-boost converter. Considering the fact that a low-power BLDC motor drive was needed for particular applications like fans, coolers or other domestic machines, a bridgeless buck-boost topology was selected for design and simulation. However, the PFC converter was not built, the elements were designed keeping in mind that only standard elements could be used and within the acceptable cost limits. A brief summary of operation of BLDC motors was presented highlighting the electronic commutation. Dynamic motor equations were evaluated and the transfer function of the motor was given, however, it was not used for controller tuning. Simulation results proved the importance of PFC circuits, as the chosen topology radically reduced the total harmonic distortion of supply current, therefore did not reflected harmonics back to the ac mains. Comparative analysis revealed the power quality improvement in numbers: the proposed drive decreased the THD to nearly 5%, and the power factor was increased to 0.999. Not only the power quality features were improved, a new method of speed control reduced the switching losses in the voltage source inverter, as the dc link voltage was regulated by a PI voltage controller. Although, the simulation results were satisfactory further development would be essential to continue the research in the topic of my TDK project. First, a closed loop speed control would improve the performance of the drive which result in capability of PFC BLDC drives in different applications. Second, the designed converter could be built, and validate the results of simulation. Furthermore, other PFC topologies could be studied in order to demonstrate the advantages and disadvantages of them and find the most suitable application. I strongly believe that this TDK project presents an optimal and efficient solution for power quality problems of low-power applications of BLDC motors, and that my work on this project is the beginning of my professional development in the field of power electronics. Literature LITERATURE [1] BME-AAIT Budapest University of Technology and Economics. Department of Automation and Applied Informatics: Basics of Electrotechnics Lecture Notes [2] ECEN 5807: Modelling and Control of Power Electronics Systems. Supplementary Notes and Materials. Chapter 16. Harmonics in Power Systems http://ecee.colorado.edu/~ecen5807/notes.html [3] A.Emadi . A. Khaligh . Z. Nie. and Y. Joo Lee: Integrated Power Electronic Converters and Digital Control. Chapter 3: Power Factor Correction CRC Press 2009. ISBN: 978-1-43980069-0 [4] BME-AAIT Budapest University of Technology and Economics. Department of Automation and Applied Informatics: Power Electronics. Laboratory Test Nr. 2.. 8th September 2014 [5] Vashist Bist. Bhim Singh: An adjustable-Speed PFC Bridgless Buck-Boost Converter-Fed BLDC Motor Drive. IEEE Transactions on Industrial Electronics. vol. 61. no. 6. pp. 26652677. June 2014 [6] Huai Wei. Issa Batarseh: Comparison of Basic Converter Topologies for Power Factor Correction. Southeastcon '98. Proceedings. IEEE. pp. 348-353. April 1998. ISBN: 0-78034391-3 [7] András Lőrincz: Master Thesis, BLDC and PMSM Motor Speed Control in Practice, Budapest University of Technology and Economics. Department of Automation and Applied Informatics, 2013 [8] Limits fir Harmonic Current Emissions (Equipment Input Current ≤16 A Per Phase), Int. Std. IEC 61000-3-2, 2000 47