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Short Sheet RAJ240500 R01AN2519EJ0100 Rev.1.00 2015.07.15 Introduction RAJ240500 is Renesas Battery Management IC which incorporates battery fuel gauge and battery charger features. RAJ240500 offers a variety of advantages to integrate battery fuel gauge and battery charger in a single system. This document describes a brief summary of RAJ240500 product features. RAJ240500 Overview RAJ240500 product consists of MCU block and AFE block as shown in Fig.1. Power supply voltage from AC adapter is applied at Adapter input (+) and Adapter input (-) terminal. Built-in DCDC controller regulates power to system output and to the battery. Fuel gauge and charger control firmware is stored in embedded flash memory and controls embedded analog and digital hardware circuits to offer optimum battery management operation. System output + Adapter input (+) FET control circuit SCL SDA DCDC PWM controller DCDC output current sense Input over voltage detector Input over current detector Voltage regulator (5V) CL control DAC (7bit) DCDC Input-Output difference detector DCDC output over voltage detector CC control DAC (7bit) CV control DAC (10bit) Overcurrent detection circuit Fuse control circuit AFE timer Series regulator (1.8V/3.3V) Simple temperature sensor AFE On-chip oscillator Current integrating circuit (18 bits×1 channel) Reset circuit Serial input/output interface MCU runaway Detection circuit A/D converter (15 bits×7 channels) Flash memory Communication Input current sense CSI21 (Clock synchronous communication) FET control circuit PWM (8 bits×1) Battery Input power supply voltage detector Battery voltage Detection circuit Conditioning circuit RAM Timer RD (16 bits×1) DataFlash 12 bits Interval timer I2C-BUS Timer array unit (16 bits×4) Watchdog timer (17 bits) Adapter input (-) + Key Features Low power consumption 16-bit CPU Built-in flash memory High speed on-chip oscillator ROM : 128KB, RAM : 5.5KB, Data flash : 4KB Built-in on-chip debug circuit 15 bits ΔΣA/D converter 18 bits ΔΣA/D current integrating circuit Serial interface : CSI, UART, I2C Overcurrent detection circuit Rev.1.00 2015.07.15 Built-in charger DCDC converter control N-ch FET driver for discharge and charge FETs Precharge support (0V battery charge) Conditioning circuit for battery cell balancing Fuse blow circuit MCU runaway detection circuit Narrow VDC support JAITA charging control support Turbo boost support Page 1 of 34 Short Sheet Table of Contents 1. Overview .......................................................................................................................... 3 1.1 Features................................................................................................................................... 3 1.2 Pin Description ......................................................................................................................... 4 1.2.1 Pin connection diagram(Top View)................................................................................. 4 1.2.2 External pins ...................................................................................................................... 5 1.2.3 Internal pins between AFE and MCU .................................................................................. 6 1.3 Block diagram .......................................................................................................................... 7 1.3.1 System block diagram ........................................................................................................ 7 1.3.2 AFE block diagram ............................................................................................................. 7 1.3.3 MCU block diagram ............................................................................................................ 8 1.4 Product Overview ..................................................................................................................... 9 2. Feature Description ........................................................................................................ 11 2.1 Measurement ......................................................................................................................... 11 2.1.1 ADC Circuit ...................................................................................................................... 11 2.1.2 Current Integrating Circuit................................................................................................. 13 2.1.3 Current Integration Circuit in Impedance Measurement Mode ........................................... 14 2.2 Protection............................................................................................................................... 15 2.2.1 Overcurrent Detection Circuit............................................................................................ 15 2.2.2 Charge / Discharge FET Control Circuit ............................................................................ 16 2.3 Charge Control Circuit ............................................................................................................ 17 2.3.1 2.3.2 Input voltage detection ..................................................................................................... 18 ACDRV charge pump ....................................................................................................... 19 2.3.3 DC-DC converter control .................................................................................................. 20 2.4 Power Supply ......................................................................................................................... 24 2.4.1 2.4.2 REGC .............................................................................................................................. 25 VCC_FG,VCC_CHG, VBAT, GND0, PGND ...................................................................... 25 2.4.3 2.4.4 CREG2 ............................................................................................................................ 25 ACDRVIN......................................................................................................................... 26 2.5 2.6 Series Regulator .................................................................................................................... 26 Reset Circuit .......................................................................................................................... 27 2.7 Serial Communication Interface .............................................................................................. 28 2.7.1 3 wire serial I/O (CSI11, CSI21) ........................................................................................ 28 2.7.2 UART (UART0) ................................................................................................................ 28 2.7.3 Simplified I2C (IIC11) ........................................................................................................ 29 2.8 Conditioning circuit ................................................................................................................. 29 2.9 Fuse control circuit ................................................................................................................. 30 2.10 MCU runaway detection Circuit .............................................................................................. 31 3. Package Dimension ....................................................................................................... 33 Rev.1.00 2015.07.15 Page 2 of 34 Short Sheet 1. 1.1 Overview Features Selectable minimum instruction execution time from High speed (0.03125μs:High speed on-chip oscillator clock 32MHz operation) to ultralow speed. General-purpose register:8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM:128 KB,RAM:5.5KB,Dataflash:4 KB Built-in the high speed on-chip oscillator clock Can be selected the following clock 32 MHz (TYP.) / 24 MHz (TYP.) / 16 MHz (TYP.) / 12 MHz (TYP.) / 8 MHz (TYP.) / 4 MHz (TYP.) / 1 MHz (TYP.) Built-in flash memory of single power supply (with block erase/write protection function) Self-programming support (with boot swap/flash shield window function) Built-in on-chip debug circuit Built-in watchdog timer (can be operated the specified low speed on-chip oscillator clock) Multiplication and multiply-accumulate instruction support I/O port:9 (CMOS input/output:4, CMOS input:2, N-ch open drain:3) Timer ・16 bits timer:5 channels (TAU:4 channels,timer RD:1 channel) ・12 bits interval timer:1 channel Serial interface ・CSI ・UART ・I2C,simplified Stand-by function : HALT, STOP 15-bit ΔΣA/D converter(external 2 channels, internal 5 channels(include simple temperature sensor)) Current integrating circuit(18 bits ΔΣA/D) Overcurrent detection circuit (discharge short-circuit current (2 channels), charge/discharge overcurrent, wake-up current) AFE on-chip oscillator clock (4.194 MHz, AFE block control only) AFE timer (setting range:125 ms to 64 s) Series regulator (VREG2:3.3 V/1.8 V) Charge/Discharge FET control circuit (discharge FET,Charge FET) Adapter input voltage(Charge DC-DC input voltage) detection circuit Conditioning circuit Battery voltage detection circuit Adapter (Charge power source ) detection circuit Reset circuit (VREG2 monitoring) FUSE control circuit Serial input/output interface (AFE-MCU communication only) MCU runaway detection circuit Turbo boost support Built in Charge DC-DC converter control circuit Narrow VDC support JEITA charge control support Charge DC-DC converter input current monitor Constant current Precharge function (0V battery charge support) Charge input current limit 7bits setting Charge output current limit 7bits setting Charge output voltage 10bits setting Charge block detection circuit (Input power supply, over voltage/over current detection ,Output over voltage/over current detection , Input-output voltage difference detection) Power supply voltage : VCC_FG = 2.0 to 25 V/VCC_CHG=4.5V to 25V. Operation ambient temperature : TA = -20 to +85 [degree] Rev.1.00 2015.07.15 Page 3 of 34 Short Sheet 1.2 Pin Description 1.2.1 Pin connection diagram(Top View) Figure 1-1 : Pin Assignment Diagram 26 25 ISENS0 P12/SO11/TRDIOB1/(INTP5)/ 「P16]/[INTP5]「RXD0」 27 ISENS1 P11/SI11/SDA11/TRDIOC1 28 AN0 P10/SCK11/SCL11/TRDIOD1 29 AN1 IMON 30 P17/TXD0/AN2 ISENSL1 ・40 pin plastic mold QFN(5.0 by 5.0) 24 23 22 21 ISENSL0 31 20 VIN1 PGND 32 19 VIN2 LODRV 33 18 VIN3 34 17 VBAT 16 CFOUT LX HIDRV BTST 35 RAJ240500 36 15 FUSEOUT 40 11 DFOUT 1 2 3 4 5 6 7 8 9 10 VCC_FG ISENSH0 CREG2 RESETN GND0 12 REGC 39 P122 ISENSH1 P137/INTP0 SCL TOOL0 13 DETOUTN VCC_CHG 38 ACDRVIN 37 ACDRV VREGN 14 SDA ・RAJ240500 Type name and package Part R A J 24 050 0 XXX D NP Package type: NP: QFN ROM number(Omitted with blank products) Management number of Renesas Function type Battery management controller IC A:1 chip product Custom IC Renesas semiconductor product Rev.1.00 2015.07.15 Page 4 of 34 Short Sheet 1.2.2 External pins External pins are listed in Table 1-1. Refer to RAJ240500 User's Manual: Hardware CHAPTER 22 ELECTRICAL SPECIFICATIONS for electrical specifications. Table 1-1 : External pins description Category Pin name I/O Function Power supply VCC_FG, - VCC_CHG, Apply power supply voltage to VCC_FG pin from external power supply (Adapter/USB etc.) or battery. Apply external power supply voltage to VBAT VCC_CHG pin through ACFET. GND0, PGND Connect the negative input terminal of lithium-ion battery 1 to the GND0. Connect the Ground (System ground) to the PGND. CREG2 - REGC Note 1 - The regulator output (2.1 V) stability capacitor connect pin for internal operation connects to GND0 through capacitor (0.47 μF to 1 μF) ACDRVIN Input Supply voltage terminal for charge pump circuit of the input control FET. Reset RESETN Input Reset input of MCU TOOL0 input TOOL0 Input Connects to CREG2 through resistor. A/D converter AN0, AN1, AN2 Input Analog input of A/D converter. Current integrating circuit ISENS0, SENS1 Input Analog input of current integrating circuit and overcurrent detection circuit. ISENSH0, Input Analog inputs for Charge DC-DC controller. IC internal power supply of 1.8V/3.3V.connects to 2.2 μF capacitor. Connects to power supply of MCU(VDD, EVDD0) in the package. Overcurrent detection circuit Charge current detection ISENSH1, "ISENSL1" terminal is also the function of DC-DC feedback input and the ISENSL0, power supply input for the discharge FET charge pump. ISENSL1 I/O port P10 to P12, P17 I/O I/O port of CMOS. To select Input or output, it has a direction register, It can select an input port or an output port each one terminal. P10,P11,P17 can change Nch Open Drain format. Battery voltage detection circuit P122, P137 Input Input port of CMOS DETOUTN Output Nch Open Drain output terminal. (Current,Voltage detection output) VIN3 Input The positive input terminal of lithium-ion battery 3. VIN2 Input The negative input terminal of lithium-ion battery 3 and the positive input VIN1 Input The negative input terminal of lithium-ion battery 2 and the positive input terminal of lithium-ion battery 2. terminal of lithium-ion battery 1. DFOUT Output ON/OFF signal output pin for discharge FET. CFOUT Output ON/OFF signal output pin for charge FET. Fuse control output FUSEOUT Output ON/OFF signal output pin for fuse. I2C -BUS interface SCL I/O I2C -BUS interface clock I/O pin. FET control output (IICA0) It connects to P60/SCLA0 of MCU. Nch Open Drain output. SDA I/O INTP0, INTP3 to INTP5, INTP8 to Input I2C -BUS interface data I/O pin. It connects to P61/SDAA0 of MCU. Nch Open Drain output. INT interrupt input INTP3, INTP4 and INTP8 to INTP11 connects interrupt request signal of AFE INTP11 Serial interface(CSI11, CSI21) SCK11, CK21 INT interrupt input. in the package and do not connect to any pin. I/O Transmission clock output of CSI11, CSI21 (clock synchronous serial I/O ). SCK21 connects directly to the CLK of serial I/O interface and do not connect to any pin. SI11, SI21 Input Serial data input of CSI11, CSI21 (clock synchronous serial I/O). SI21 connects directly to the DO of serial I/O interface and do not connect to any pin. SO11, SO21 Output Serial data output of CSI11, CSI21 (clock synchronous serial I/O). SO21 connects directly to the DI of serial I/O interface (AFE) and does not connect to any pin. Rev.1.00 2015.07.15 Page 5 of 34 Short Sheet Category Pin name I/O Serial interface (UART0) RxD0 TxD0 Input Serial data input of UART Output Serial data output of UART. P73 I/O Serial I/O interface Function It uses as chip select signal of serial I/O interface(AFE) by setting output port P73 connects directly to the CS of serial I/O interface (AFE) and does not connect to any pin. MCU runaway detection circuit P76 Output Analog output IMON Output DC-DC FET control LODRV,HIDRV Output DC-DC output FET control terminal. ACDRV Output AC FET control terminal. LX Input DC-DC Hiside FET Source voltage input terminal. BTST Input DC-DC Hiside FET Bootstrap capacitor connect terminal. It uses as counter refresh signal of MCU runaway detection circuit by setting output port.P76 connects directly to the WDTIN of AFE and do not connect to any pin. Analog monitor output terminal for Adapter input current and Battery discharge current. Bootstrap control VREGN Output DC-DC Hiside FET Bootstrap reference voltage output terminal. Note1 : REGC is not external power supply pin. Do not draw any current from REGC externally. 1.2.3 Internal pins between AFE and MCU Internal pins between AFE and MCU are listed in Table 1-1. These signals are connected within the package and not accessible with any external pins. Table 1-2 : Internal Pin Description I/O as seen from AFE MCU pin AFE pin Function P30/INTP3 INT_AFE_CHG Output External interrupt output of SYSIN pin P05/INTP10 INT_AFE_TM Output Underflow interrupt output of AFE timer P06/INTP11 INT_AFE_ANL Output Abnormal interrupt output (Abnormal interrupt are the logical add of 4 factors (CD interrupt, WU interrupt, MCU runaway detection interrupt, external interrupt of FUSEOUT pin)). P70/SCK21 CLK Input Clock input of communication between MCU and AFE. P71/SI21 DO Output Data output of communication between MCU and AFE. P72/SO21 DI Input Data input of communication between MCU and AFE. P73 CS Input Chip select input of communication between MCU and AFE. P74/INTP8 INT_AFE_AD Output A/D interrupt output P75/INTP9 INT_AFE_CC Output Current integrating interrupt output P76 WDTIN Input Refresh signal input of MCU runaway detection circuit. Output SCL/SDA pin interrupt output ― Connection of P61/SDAA0 and SDA pin. P31/INTP4 INT_AFE_ P61/SDAA0 SDA_IN I2C (With pull-down resistor and external interrupt function in the AFE.) P60/SCLA0 SCL_IN ― Connection of P60/SCLA0 and SCL pin. (With pull-down resistor and external interrupt function in the AFE.) P17/AN2 Rev.1.00 2015.07.15 AN2 Input A/D converter analog input. Page 6 of 34 Short Sheet 1.3 Block diagram 1.3.1 System block diagram Figure 1-2 : System Block Diagram AFE FET control circuit Input current sense FET control circuit Input over voltage detector Input over current detector Voltage regulator (5V) CL control DAC (7bit) DCDC Input-Output difference detector DCDC output over voltage detector CC control DAC (7bit) CV control DAC (10bit) Overcurrent detection circuit Fuse control circuit Series regulator (1.8V/3.3V) Simple temperature sensor AFE On-chip oscillator Current integrating circuit (18 bits×1 channel) Reset circuit Serial input/output interface MCU runaway Detection circuit A/D converter (15 bits×7 channels) IMON DETOUT MCU PWM (8 bits×1) Input power supply voltage detector AFE timer Battery voltage Detection circuit Conditioning circuit CSI21 Flash memory 1.3.2 DCDC output current sense DCDC PWM controller RAM (Clock synchronous communication) Timer RD (16 bits×1) DataFlash 12 bits Interval timer I2C-BUS Timer array unit (16 bits×4) Watchdog timer (17 bits) AFE block diagram VCC_FG VBAT CFOUT DFOUT ISENSL1 ISENSL0 LODRV PGND LX HIDRV BTST VREGN ISENSH1 ISENSH0 VCC_CHG ACDRV ACDRVIN Figure 1-3 : AFE Block Diagram VCC_CHG ACDRV Charge Pump CHG/DSG FET Drv. FET DRV REGN 5V VIN3 VIN2 ISENSL0 ACDRVIN ACDET/ UVLO/ OVP Charge Control IMON VCCVOUT Det Battery voltage det. Conditioning Driver LOGIC VIN1 GND0 CL DAC DCDC control CC DAC CV DAC ISENSE0 Over current det IMON OSC (4MHz) DETOUT CHG cont. FUSEOUT FG cont. Interruption cont. DETOUTN 18 bits ADC Coulomb counter Register Serial IF 15 bits ADC MCU cont. Simple Temp sensor MUX CREG2 PWM gen. LOGIC Reset gen. AFE ISENSE1 VCC_FG Voltage reference VREG1 VCC_FG VREG2 3.3V/ 1.8V CREG2 SCL ROM SDA CPU Rev.1.00 2015.07.15 AN0 AN1 P17/AN2 P12 P11 P10 RESETN P137 P122 TOOL0 REGC MCU Page 7 of 34 Short Sheet 1.3.3 MCU block diagram Figure 1-4 : MCU Block Diagram TIMER ARRAY UNIT (4ch) PORT 0 2 P05, P06 (Note1) ch0 PORT 1 5 P10 to P12, P16, P17 PORT 3 2 P30, P31 (Note1) PORT 6 2 P60, P61 (Note2) PORT 7 7 P70 to P76 (Note1) ch1 INTERVAL TIMER ch2 ch3 RL78 CPU CORE TIMER RD (1ch) TRDIOB1/P12, TRDIOC1/P11, TRDIOD1/P10 3 ch1 MULTIPLIER, DIVIDER & MULTIPLYACCUMULATOR RxD0/P16 (Note3) TxD0/P17 (Note3) P122 DATA FLASH MEMORY PORT 13 P137 POR/LVD CONTROL RAM RESET CONTROL SERIAL ARRAY UNIT0 (4ch) ON-CHIP DEBUG TOOL0 UART0 SYSTEM CONTROL RESET SERIAL ARRAY UNIT1 (2ch) SCK21/P70 (Note1) SI21/P71 (Note1) PORT 12 POWER ON RESET/ VOLTAGE DETECTOR WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR CODE FLASH MEMORY CSI21 HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR REGC SO21/P72 (Note1) SDAA/P61 (Note2) SCLA/P60 (Note2) Rev.1.00 2015.07.15 SERIAL INTERFACE IICA INTERRUPT CONTROL 2 INTP0/P137 INTP5/P16 INTP3/P30 INTP4/P31 2 INTP8/P74 INTP9/P75 2 INTP10/P05 (Note3) INTP11/P06 (Note3) Page 8 of 34 Short Sheet 1.4 Product Overview Major RAJ240500 design specifications are listed in Table 1-3. Note that following description assumes peripheral I/O re-direction register 0 (PIOR0) set to "02H". Table 1-3 : Design Specification Item Description Code flash memory 128 KB Data Flash memory 4 KB RAM 5.5 KB Main system clock High speed on-chip Low speed operation:1 to 8 MHz (VREG2 =1.8 to 3.45 V) Oscillator clock (fIH) Low speed on-chip oscillator clock 15 kHz (TYP.) : VREG2 =1.8 to 3.45 V General purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) minimum instruction execution time 0.03125 μs(Internal high speed oscillation clock:fIH = 32 MHz) Instruction set ・Data transmission (8/16 bits) ・Addition and subtraction/logical operations (8/16 bits) ・Multiplication (8×8 bits,16×16 bits),Division (16÷16 bits,32÷32 bits) ・Product Sum operation(16×16+32 bits) ・Rotate, barrel shift, bit manipulation (set, reset, test, Boolean operation) etc I/O Port Timer CMOS input/output 4 CMOS input 2 I2C bus input/output 2 FUSE control FUSEOUT(High voltage input/output port) 16 bits timer 5 channels Watchdog timer 1 channel 12 bits interval timer 1 channel (TAU:4 channels, Timer RD:1 channel) ・UART:1 channel Serial interface ・I2C:1 channel/simple I2 C:1 channel ・CSI:1 channel 2 Vectoru interrupt source I C bus 1 channel Internal 10 External 8 (6 sources is connected to AFE in the chip) ・Reset by RESET pin (reset circuit output of AFE,connect to RESETOUT) ・Internal reset by watchdog timer Reset ・Internal reset by illegal instruction execution Note 1 ・Internal reset by RAM parity error ・Internal reset by illegal memory access On-chip debug function Supported Note 1 : Internal reset occurs when an instruction code of “FFH” is executed. Internal reset due to illegal instruction execution does not occur in the emulation mode with an on-chip debug emulator. Rev.1.00 2015.07.15 Page 9 of 34 Short Sheet Item Description PWM 8 bits×1 A/D converter 15 bits resolution (ΔΣ method) ×2 channels + internal 5 channels Current integrating circuit 1 channel:18 bits resolution Current integrating circuit for 1 channel:11 bits resolution impedance measurement Simple temperature sensor Overcurrent detection circuit Charge block detection circuit 1 channel Discharge short-circuit current detection 1, discharge short-circuit current detection 2 , Discharge overcurrent detection1 , discharge overcurrent detection 2,charge overcurrent detection, Wake-up current detection (discharge),turbo boost current detection Adapter input : UVLO,over voltage/over current detection Charge output : over voltage/over current detection Input-output voltage difference detection Charge/Discharge FET control circuit NchFET driver for charge control Charge block power supply FET control circuit NchFET driver for charge block power supply Charge output FET control circuit Nch FET driver for Charge output control(DC-DC converter) Built in BootStrap power supply(VREGN) NchFET driver for discharge control Input current limit(7bits),Output current control(7bit),Output voltage control(10bits) Battery voltage detection circuit Battery voltage gain:1 Adapter input voltage detection circuit Adapter input voltage detection Adapter input current detection circuit Adapter input current detection DC-DC output voltage detection circuit DC-DC output voltage detection Fuse control circuit Fuse control function Series regulator VREG2:power supply for MCU (1.8V/3.3 V) High precise reference voltage source Built-in voltage reference voltage(1.2V) for A/D converter , current integration circuit Reset circuit Series regulator output monitoring (VREG2) Conditioning circuit 3 cell support (On-resistor:500Ω) MCU runaway detection circuit 20 bits×1(2 / 4 /8 [s] to be selected) On-chip oscillator 4.194 MHz (TYP.) AFE timer 2 channels AFE timer A(setting range:125 ms to 64 s) AFE timer B(setting range:30.52 us to 125 ms) Serial input/output interface Communication between AFE and MCU (4-wire) Power supply voltage VCC_FG=2.0 to 25V / VCC_CHG=4.0 to 25 V Operation ambient temperature -20 to 85 [degree] Package 40 pin QFN Rev.1.00 2015.07.15 Page 10 of 34 Short Sheet 2. Feature Description 2.1 Measurement 2.1.1 ADC Circuit 15-bit delta-sigma ADC is implemented to measure instantaneous analog signal levels, such as voltage, current, temperature and etc. The multiplexer selects one of 18 channels to measure each signal as shown in Figure 2-1. Selectable ADC multiplexer channels are listed in Table 2-2. Appropriate channel of the multiplexer must be selected to measure desirable analog signal. ADC conversion results are stored in A/D data registers after the conversion. ADC circuit block has a feature to execute multiple ADC conversions automatically. The multiplexer selects designated channel and ADC conversions are executed as specified in ADC automatic mode control register. An interrupt is asserted upon ADC conversion and the conversion result is stored in A/D data registers periodically. Impedance measurement mode for Turbo-boost is an optional feature to measure voltage and current simultaneously. This optional feature was designed to measure battery impedance upon Turbo-boost operation and to calculate available maximum power. See 12.2 Register of AFE in RAJ240500 User’s Manual: Hardware for ADC registers. See 22.6.1 A/D converter characteristics in RAJ240500 User’s Manual: Hardware for ADC electric characteristics. Figure 2-1 : A/D Converter fOCO divided by 4 ISENSL1 VIN3 VIN2 VIN1 AN2 AN1 AN0 Simple temperature sensor VREG1 VREGpull GND0 System voltage Input voltage Input current Discharge current Charge current PGND Clock/Interrupt control circuit AD interrupt AD data register H AD data register L Data bus Multiplexcer Δ∑convertor AD control register ADSEL[4:0] Table 2-1 : A/D converter specification Item Performance A/D conversion method ΔΣ conversion Analog input voltage range 0 V to (TBD) Operating clock φAD fOCO divided by 4: 1.048576 MHz (fOCO=AFE on-chip oscillator) Resolution 15 bits Conversion accuracy Integral non-linearity error : ±16 LSB Rev.1.00 2015.07.15 Page 11 of 34 Short Sheet Analog input channel Multiplexer output A/D conversion start condition Software trigger Conversion rate per pin 1024 ΦAD cycles: 1 ms mode Note 2048 ΦAD cycles: 2 ms mode Note 4096 ΦAD cycles: 4 ms mode Note 8192 ΦAD cycles: 8 ms mode Note Note : One of the modes should be selected with the bits ADTIME0 to ADTIME1 in the ADCON1 register. Table 2-2 : ADC Multiplexer Channels Measurement Item Input Signal Ground Level 1 Offset voltage GND0 GND0 2 Cell1 voltage VIN1 GND0 3 Cell2 voltage VIN2 VIN2 4 Cell3 voltage VIN3 VIN3 5 Total cell voltage VIN3*0.2 GND0 6 Charge voltage ISENSL1×0.2 GND0 7 AN0 AN0 GND0 8 AN1 AN1 GND0 9 AN2 AN2 GND0 10 Simple temperature sensor Simple temperature sensor GND0 11 VREGpull VREGpull GND0 12 A/D reference voltage (VREG1) VREG1 GND0 13 Input voltage ACDRVIN×0.0819 PGND Note1 14 Input current PGND Note1 15 System voltage PGND Note2 16 Charge current (ISENSL0-ISENSL1)×20+0.4 PGND Note1 17 Discharge current (ISENSL1-ISENSL0)×10+0.4 PGND Note1 18 Charge GND offset (ISENSH0-ISENSH1)×20+0.4 ISENSL0×0.2 PGND Note Thermistor pull up voltage GND0 Note1 : Do not select these channels when charge block is not powered on. Internal amplifiers are not functional without power source. Note2 : System voltage channel should be selected only when ISENSL0 voltage is 4.0V or higher. Otherwise, the precision of system voltage measurement will degrade. Rev.1.00 2015.07.15 Page 12 of 34 Short Sheet Figure 2-2 ADC Multiplexer Diagram 1 0 ISENSL1 ISENSL0 ISENSH ISENSH ISENSL1 ACDRVIN - + - + X20 X20 Input voltage X10 System voltage Input current Charge PGN ull AN * AN Simple temperature sensor * GND GND VIN2 VIN1 MUX GND A/D 0 Converter ADSEL<4:0> 0 0 2.1.2 PGN D VREGp VREGp ull VIN3 VIN3 VIN2 VI Discharge current AN2 N1 AN A1 GND0 N0 Simple temperature sensor VREGpull VREG Input voltage1 Input current System voltage Discharge curren Charge currentt PGND current D - + Current Integrating Circuit The current integrating circuit is used to measure current flowing across a sense resistor and converts the differential voltage between ISENS1 and ISENS0 pins to accumulated digital value. Current integration result per cycle is stored in the CCRH, CCRM and CCRL registers. The values of these registers are undefined after a reset. Read the current integration result before the next current integration cycle is completed because the CCRH, CCRM and CCRL registers are overwritten upon completion of the next current integration cycle. See 12.2 Register of AFE in RAJ240500 User’s Manual: Hardware for current integrating circuit registers. See 22.6.2 Current integrating circuit characteristics in RAJ240500 User’s Manual: Hardware for current integrating circuit electric characteristics. Figure 2-3 Current integrating circuit block diagram CC ISENS1 ISENS0 Clock/interrupt control circuit Current integration interrupt Current integration data register H Current integration data register M Current integration data register L Data bus A/D converter Current integration control register Table 2-3 Current integrating circuit specification Item Conversion method Rev.1.00 2015.07.15 Performance ΔΣ conversion Page 13 of 34 Short Sheet Analog input voltage range -0.1 V to 0.1 V Operating clock φCC fOCO divided by 32: 131.072 kHz (fOCO=AFE on-chip oscillator) Resolution 18bit Conversion accuracy Integral non-linearity error: ±0.02 %FSR Analog input pin Potential difference between ISENS1 and ISENS0 pins Conversion time per cycle 250 ms (32,768φCC cycle) 2.1.3 Current Integration Circuit in Impedance Measurement Mode The current integrating circuit in impedance measurement mode executes its current integration in synchronized with ADC conversion. It measures current flowing across the sense resister and converts differential voltage between ISENS1 and ISENS0 pins to accumulated digital value when ADC is converting voltage simultaneously. This optional feature is designed to measure battery impedance and to calculate available maximum power of the battery. Current integration circuit conversion time is shorter and its resolution is lower than normal current integration as described in Table 2-4. See 12.2 Register of AFE in RAJ240500 User’s Manual: Hardware for current integrating circuit registers. See 22.6.2 Current integrating circuit characteristics in RAJ240500 User’s Manual: Hardware for current integrating circuit electric characteristics. Table 2-4 Current integrating Circuit for impedance Measurement Performance Item Performance Conversion method ΔΣ conversion Analog input voltage -0.1 V to 0.1 V Operating clock φCC fOCO divided by 32: 131.072 kHz (fOCO=AFE os-chip oscillator) Resolution Conversion time 1 ms(note 1): 7 bits Conversion time 2 ms(note 1): 8 bits Conversion time 4 ms(note 1): 9 bits Conversion time 8 ms(note 1): 10 bits Analog input pin Conversion time per cycle (note 1) Potential difference between ISENS1 and ISENS0 pins Note 1 ms, 2 ms, 4 ms, 8 ms Note The conversion time varies with the settting of the ADTIME1 bit and the ADTIME0 bit in the ADCON1 register. Rev.1.00 2015.07.15 Page 14 of 34 Short Sheet Figure 2-4 Current integrating circuit for impedance measurement block diagram φCC (fOCO divided by 32) Clock/interrupt control circuit Current integration for impedance measurement interrupt ISENS1 Δ∑ converter Current Integrating Circuit for Impedance Measurement Data Register H Current Integrating Circuit for Impedance Measurement Data Register L Data bus ISENS0 AD control register AD control register 2 2.2 Protection 2.2.1 Overcurrent Detection Circuit The overcurrent detection circuit detects overcurrent events such as short-circuit, charge/discharge overcurrent and turns off battery pack charge/discharge control FETs to stop charging/discharging. The overcurrent detection circuit incorporates discharge short-circuit current circuit 1, discharge short-circuit current circuit 2, discharge overcurrent circuit, discharge overcurrent circuit 2, and charge overcurrent circuit. The detection voltage and the detection time can be set in hardware registers individually. The overcurrent detection circuit also incorporates a wakeup current detection circuit which generates an interrupt upon current of 200 mA to 1 A across the sense resistor in power-down mode, where the current integrating circuit is disabled. Additionally, it incorporates large discharge current (1C to 4C) detection which generates an interrupt upon Turbo Boost event, measure cell voltage and turns on charge FET automatically. See 12.2 Register of AFE in RAJ240500 User’s Manual: Hardware for overcurrent detecting circuit registers. See 22.6.3 Overcurrent detecting circuit characteristics in RAJ240500 User’s Manual: Hardware for overcurrent detecting circuit electric characteristics. Table 2-5 Overcurrent Detection Circuit Specification Item Performance Analog input pin ISENS1 Operating clock f32K (AFE on-chip oscillator divided by 128) Detection voltage Setting range Discharge short-circuit current1 Discharge short-circuit current 2 (setting interval) 0.1 V to 0.8 V (0.1 V) 25 mV to 100 mV (12.5 mV) 100 mV to 250 mV (25 mV) Discharge overcurrent 25 mV to 50 mV (2.5 mV) 50 mV to 100 mV (5 mV) Discharge overcurrent 2 -10 mV to 75 mV (1.25 mV) 75 mV to 110 mV (2.5 mV) Charge overcurrent -25 mV to -100 mV (12.5 mV) -100 mV to -250 mV (25 mV) Rev.1.00 2015.07.15 Page 15 of 34 Short Sheet Detection time Wakeup current -120 mV to 170 mV (1.25 mV) Turbo boost current -120 mV to 170 mV (1.25 mV) Discharge short-circuit current1 0 μs to 427 μs (61 μs) Setting range Discharge short-circuit current 2 0 μs to 915 μs (61 μs) (setting interval) Discharge overcurrent 0.916 ms to 30.212 ms (1.95 ms) Discharge overcurrent 2 0.916 ms to 30.212 ms (1.95 ms) Charge overcurrent 0 μs to 915 μs (61 μs) Wakeup current 62.5 ms ※244 μs during calibration Turbo boost current 488 μs Detection voltage offset error Wakeup current detection circuit Input scaling factor 2.2.2 Discharge short-circuit current1 ±50 mV Discharge short-circuit current 2 ±10 mV ( setting range 1) /±25 mv (setting range 2) Discharge, charge overcurrent ±10 mV (setting range 1) /±25 mv (setting range 2) Discharge overcurrent 2 ±10 mV Wakeup current ±20 % Turbo boost current ±20 % 20 times, 10 times, 5 times, 2 times Charge / Discharge FET Control Circuit The FET control circuit has two on-chip voltage step-up circuits and drives N-ch FETs as switches to control charging and discharging current. FET ON/OFF control Charge FET and discharge FET can be turned on/off by setting the FETC bit, FETD bit in the FCON register, to 1/0. Forced FET OFF Function The FET control circuit can be configured to turn off charge FET or discharge FET automatically when an short-circuit overcurrent, overcharge, or overdischarge state is detected. Forced OFF Function of discharge FET is set with BCFETEN bit in BCDCON register or SCFETEN bit in SCDCON register or DOCFETEN bit in DOCDCON register to 1. Forced OFF function of charge FET is set with COCFETEN bit in COCDCON register to 1. The state of forced FET OFF function is judged by reading the AFECON3 register. In discharge FET control, read the DFCNTMON bit in the AFECON3 register, in charge FET control, read the CDCNTMON bit in the AFECON3 register respectively. When the DFCNTMON bit is “1”, the DFOUT pin becomes ISENSL1 level. When the CFCNTMON bit is “1”, the CFOUT pin becomes VBAT level When the forced FET OFF function is enabled (forced OFF), FETC bit and FETD bit in FCON register values are invalid. Forced FET OFF function control is always enabled in this case. Table 2-6 shows the relationship of FCON register value, FET forced OFF function and DFOUT/CFOUT pin control. Table 2-6 Initialize register by reset factor except for power-on reset and other DFOUT control Rev.1.00 2015.07.15 CFOUT control Page 16 of 34 Short Sheet DFCNT MON bit FETD bit DFOUT pin CFCNT MON bit FETC bit CFOUT pin 0 0 OFF 0 0 OFF 0 1 1 1 0 1 ON ISENSL1 level 0 1 1 1 0 1 ON VBAT level Charge FET ON function when turbo boost current is detected It is possible to force charge FET ON when turbo boost current is detected. Charge FET ON function is enabled by setting the TBCFETEN bit in the WUDCON2 register to 1 when turbo boost current detection is enabled. See 12.2 Register of AFE in RAJ240500 User’s Manual: Hardware for charge/discharge FET control circuit registers. See 22.6.6 Charge/discharge FET control circuit characteristics in RAJ240500 User’s Manual: Hardware for charge/discharge FET control circuit electric characteristics. 2.3 Charge Control Circuit This block generates power supply voltage to system and battery by DC-DC converter from AC-adapter. This block has 3 functions as follows. 1. Input voltage detection 2. ACDRV charge pump 3. DC-DC converter control Table 2-7 Charger Control Specifications Input voltage detection Adapter voltage detection. ACDRV charge pump Nch input FET gate driver. Current detection It detect input current by external 10m ohm detection resistor.(for DC-DC converter output Input current voltage control) Charge current DC-DC PWM (CC,CV charge) Rev.1.00 2015.07.15 It detect charge current by external 10m ohm detection resistor.(for DC-DC converter output voltage control) CC,CV control Constant voltage control (CV) : 10bits(16mV/step) Constant current control(CC) : 7bits(64mA/step) Input current control Precharge CFET control charge current when DC-DC output constant voltage. (The case of battery voltage is under the value.) Charge ON/OFF control It can ON/OFF control by register. Page 17 of 34 Short Sheet Figure 2-5 Charge Control Circuit 2.3.1 Input voltage detection Charge control block detect the state of each terminal, such as ACDRVIN,VCC_CHG,ISENSL1. These signals control start and stop operation of charge block. ACDRV AMP ISENSL1 ISENSL0 REGN ISENSH1 ISENSH0 VCC_CHG ACDRV ACDRVIN Figure 2-6 Charge Control Block Diagram REGN DCDC CP ACDET DCDC VCC BAT Control REGNPOR UVLO INOCP PWM OUTOVP OUTPOK INOVP Control Logic (1) AC adapter input voltage detection (ACDET) This circuit detects AC adapter connection. It detect input when ACDRVIN input voltage > VACOK_RISE (TYP. 4.5V) and set "1" to ACDET register. ACDET register clear to "0" when it detect ACDRVIN input voltage < VACOK_FALL (TYP. 4.2V) Rev.1.00 2015.07.15 Page 18 of 34 Short Sheet ACDET detection occur interrupt to MCU, and from this, MCU controls charge block start sequence, such as "charge control enable" "ACFET ON" "DC-DC enable". And also it start Fuel Gauge block. (2) UVLO detection This circuit detect removing AC adapter. After charge block start , it detect when ACDRVIN input voltage < UVLO(TYP. 3.15V) and set "1" to UVLODET register. It clear CHGBLKON bit to "0". (3) Input overvoltage detection (INOVP) This circuit detect when ACDRVIN input voltage is over VOV_AC, and set "1" to INOVPDET register. It clears ACFETEN register and DCDCEN register. Then ACDRV chargepump and DC-DC converter stop. INOVP detection level is controled by INVOPT1 and INOVPT0 Bits. It can avoid from applying higher voltage than assumed to adapter. Set INOVPT1 and INOVPT0 Bits during ACDET start to DCDC enable. (4) Charge control block enable Charge control block(DC-DC control circuit , DETOUT circuit ,IMON circuit) enabled by setting CHGBLKON ="1". CHGBLKON register can set "1" only when ACDET="1". ACDET is a internal signal display register that display "1" when it detect input voltage from adapter. It clears to "0" by UVLO detection. 2.3.2 ACDRV charge pump Built in ACDRV charge pump drives input ACFET. It supports Nch MOSFET. ACDRV charge pump and FET driver operate when input voltage is applied to ACDRVIN terminal. If there is no voltage, ACDRV charge pump stop and FET driver cut off ACFET current. (1) ACFET Enable ACDRV charge pump start and ACDRV terminal outputs ACDRVIN terminal level + 5.5V, when ACFETEN register is set to "1". ACFETEN register can set "1" only when CHGBLKON="1" and REGNPORDET="1". It clears to "0" when VCCBAT1DET or INOVPDET are set to "1". (2) ACFETNUEN ACFETNUEN register : ACFET use choice 0 : Use 1 : No Use Set this register "1" for no ACFET application. (3) ACDRVGOEN ACDRVGOEN register : It forced pull down ACDRV terminal to GND level. (0 : Disable, 1 : Enable) This setting is forced to cut off ACFET at the case when DC-DC converter external FET driver is broken. Rev.1.00 2015.07.15 Page 19 of 34 Short Sheet Don't use this register in normal operation, because this setting has possibility of exceeding ACFET maximum rating of applied voltage. 2.3.3 DC-DC converter control Built-in DCDC converter controls switching mode regulator and drives external FET gates. Both of high side and low side drivers for synchronous rectification are N-channel FETs and utilize boot strap circuit to boost gate drive voltage. DC-DC converter has 3 feedback signals to regulate PWM switching signal as listed below. Battery voltage, System voltage (DC-DC converter output) (CV) Input current (CL) Output current (CC) DCDC converter circuit has six control states as listed in Table 2-8. Table 2-8 DCDC Converter Control States Each Amplifier operation No. State Control CV CL CC PRECHG 1 No Adapter No × × × × 2 Constant Current CC ○ ○(×) ◎ × 3 Constant Voltage CV ◎ ○(×) ○ × 4 No Charge CV ◎ ○(×) × × 5 Current Limit CL ○ ◎ ○ × 6 Pre-charge CV & PRECHG ◎ ○(×) × ◎ (◎:Main, ○:Sub, ×:Stop) Pre-charge : DC-DC converter output constant voltage in CV control mode and CFET output constant precharge current to battery. CFET gate is controlled by linear signal. At "○(×)" cell in the upper table, CL control mode stop if CLEN register set to "0". However, note that it stops current limit function. Set CHGEN register "1" at CC control mode or Pre-charge control mode. Because output current sense circuit become power down at CHGEN ="0". Set CHGEN register "0" when current control circuit isn't used. <Charge current control application> System power supply output from before the current sense resistor. (ISENSL0 terminal) It is suitable for battery charge that the charge current is controlled to purely constant current. <Load current control application> System power supply output from after the current sense resistor. (ISENSL1 terminal) DC-DC converter controls by sum value of charge current and system load current at CC control mode. At this mode, charge current is equal to CC mode setting value minus system load current. Rev.1.00 2015.07.15 Page 20 of 34 Short Sheet This application save battery power dissipation that discharge current doesn't pass the output sense resistor. (1) DCDC start sequence DC-DC converter starts operation by setting DCDCEN register to be "1". DCDCEN register can set "1" only when CHGBLKON="1" and VCCBAT2DET="1". DCDCEN register clear to "0" when VCCBAT1DET=1 or INOVPDET=1 or OUTOVPDET=1 or OUTPOKDET=1. DC-DC converter control frequency is set by FREQSEL[1:0] register. At DC-DC converter starts, softstart sequence is need by changing CHICHG register and CHVCV register. (2) Input current limit Input current is detected by sense resistor between ISENSEH0 and ISENSEH1 terminal. Input current is limited by this detected current. The limit value is set by CHICL register, as following table. It is recommended that the sense resistor value is 10mohm. Input current is controlled as lower than setting value. Shortage current is supplied from battery. CHICL register: Input current limit setting (sense resistor value is 10mΩ) (3) MIN MAX 1LSB DAC 64mA 8128mA 64mA 7bit Description Output current control Output current is detected by sense resistor between ISENSEL0 and ISENSEL1 terminal. Output current is controlled constantly by this detected current. The current value is set by CHICHG register, as following table. It is recommended that the sense resistor value is 10mohm. The case system power supply from before sense resistor, it is controlled as battery charge current is setting value. The case system power supply from after sense resistor, system current plus charge current is controlled as setting value. CHICHG register:Output constant current setting (sense resistor value is 10mΩ) (4) MIN MAX 1LSB DAC 64mA 8128mA 64mA 7bit Description Constant voltage control DC-DC converter controls ISENSL1 terminal voltage as setting value. Control voltage is set to CHVCV1 register and CHVCV2 register. During stopping battery charge or controlling system voltage in pre-charge , the operation is same. Rev.1.00 2015.07.15 Page 21 of 34 Short Sheet CHVCV1, CHVCV2 register : Constant voltage setting MIN MAX 1LSB DAC 2.048V 15.04V 16mV 10bit Description DC-DC converter is only for step-down. (5) Pre-charge Pre-charge operation is available by setting PRECCHGEN register to "1" when battery voltage is low. In Pre-charge operation, DC-DC converter controls system voltage to be setting value and CFET is controlled to output constant current at same time. Pre-charge current is set by CHICHG register.(Pre-charge setting register is double use for constant current setting.) At starting Pre-charge mode or finishing Pre-charge mode, once change to No_charge mode and move to the next mode. (To avoid mode change response.) FETC (FCON register bit2) is invalid when PRECHGEN register is set to "1". Set CHGEN register "1" at CC control mode or Pre-charge control mode. Because output current sense circuit become power down at CHGEN ="0". During Pre-charge, CFET generate heat as follow calculation. (CFET drop voltage) x Pre-charge current Caution : Don't exceed FET maximum power dissipation specification. Precharge current max value is 1024mA. If it is set exceed the value, output is clamped to 1024mA. Pre-charge current setting (10mΩ sense resistor) CHICHG register : Double use of output current control setting (6) MIN MAX 1LSB DAC 64mA 1024mA 64mA 7bit Description Input overcurrent detection(INOCP) This circuit monitors DC-DC converter input current by ISENSEH0-ISENSEH1 terminal voltage difference. It detects that input current exceed IOC_AC, then DC-DC converter High Side Driver is off. IOC_AC is 300% of CL setting value. This detection and release are operated every DC-DC control clock. This function is disabled by setting INOCPEN to "0". (7) Output overvoltage detection (OUTOVP) This circuit monitors DC-DC converter output voltage(ISENSL1 terminal voltage). It detects that output voltage exceed VOV_VSYS, then DC-DC converter High Side Driver is off. VOV_VSYS is 106% of CV setting value. The High Side driver control is released when output voltage fall and lower from VOV_VSYS_HYS(103% of CV setting value). If OUTOVP detection continues 250ms, OUTOVPDET register is set to "1" and DC-DC converter is stopped. In this case, DC-DC converter doesn't re-start only output voltage falling down. It needs DC-DC start sequence by MCU. Rev.1.00 2015.07.15 Page 22 of 34 Short Sheet During DC-DC converter start sequence(Soft start), this function is disabled. This function is disabled by setting OUTOVPEN to "0". (8) Input output level detection (VCCBAT) This circuit compare VCC_CHG (Adapter input voltage) and ISENSL0 terminal voltage and display result to VCCBAT1DET and VCCBAT2DET register. When ISENSL0 voltage is higher than VCC_CHG voltage, ACFET and DC-DC converter is stopped. VCCBAT1DET ="1" : VCC_CHG - ISENSL0 < 200mV VCCBAT2DET ="1" : VCC_CHG - ISENSL0 > 200mV This detection enable 2ms after setting ACFETEN=1 in the case of ACFETNUEN=0.In this case, VCCBAT1DET register clear to "0" at setting ACFETEN=1. When VCCBAT1DET is set to "1", ACFETEN register and DCDCEN register is cleared to "0". From this, ACFET and DC-DC converter is stopped. (9) Output POK detection(OUTPOK) During DC-DC converter operating, this circuit detects circuit short. It detects that DC-DC output (ISENSL1 voltage) is lower than VOPOK (typ1.5V) and this continue over 1ms. If it detects, OUTPOKDET register is set to "0". From this, DCDCEN register is cleared to "0" and DC-DC converter is stopped. This function is disabled by setting OUTPOKEN to "0". This detection is invalid until 0.576V or more are set to DACCV in soft start sequence. When DACCV register is set to over 0.576V, this function is enabled and detect threshold is 0.5V. At the end of softstart , OUPOKDET is set to "1" if DC-DC output voltage exceed 0.5V. And OUPOKDET is set to "0" when DCDCEN register set to "0". (10) Diode rectifier mode The DIMODE bit set to "1" then DC-DC converter turned into diode rectifier mode. The diode rectifier mode improve DC-DC converter's efficiency when the current load is light. To judging load situation, check the AD output of input current monitor. In the case of continuously using diode rectifier mode, set disable period 20us every 125ms typ (20ms~500ms). If not, HiSide-Driver MOS gate level cannot keep and DC-DC converter don't work properly. (11) REGN detection(REGNPOR) When VREGN terminal voltage exceed VREGN_R(TYP. 3.7V),REGNPORDET register is set to "1". From this, ACFETEN register can be set "1". After setting ACFETEN register, REGNPORDET value is ignored. (12) Inversion current protect (RCP) Rev.1.00 2015.07.15 Page 23 of 34 Short Sheet It detect DC-DC converter inversion current and protect it. This function is enabled by setting RCPEN register to "1". (13) Discharge control This circuit discharge ISENSL1 terminal. This is enabled by setting DISCHGEN register to "1". (14) DC-DC converter operation mode display EACCCOMP, EACVCOMP and EACLCOMP bits of CHREAD2 register indicate DC-DC converter operation mode by monitoring error amplifier. Normally only one of them indicates “0” , and it present the DCDC mode, when the DCDC circuit is in operation. They indicate two or more “0” in the same time when changing time or when DCDC circuit is not in normal operation. (15) DCDC-ERROR detection DCDCERDET bit of CHREAD2 register indicates that DC-DC converter is in abnormal operation (= DCDC-ERROR). It indicates “0” in normal operation. It become “1” when Bit2~Bit0 are all “1” and this situation continues 1ms. The DCDC circuit stops if this bit turns into “1”. DCDCERDET register is cleared when DC-DC converter starts. (16) Current amplifier filter short function In this function, DC-DC converter response become quick in changing DCDC operation mode. FILCNTEN bit of CHCON3 register controls this function. For example, in the case of sudden decrease of load current such as at the end of turbo boost, the large transient charge current is suppressed. And battery over current is reduced at the time that CFET is turned on(CV to CC) even if DACCC isn't set minimum value at the moment. If the transient waveform is not acceptable, set DACCC minimum level when the CFET is turned on. 2.4 Power Supply There are four external power supply pins and two internal power supply pins. Table 2-9 Power Supply Pins Pin name I/O Function VCC_FG, VCC_CHG, VBAT GND0, PGND - Apply power supply voltage to VCC_FG pin from external power supply (Adapter/USB etc.) or battery. Apply external power supply voltage to VCC_CHG pin through ACFET. Connect the negative input terminal of lithium-ion battery 1 to the GND0. Connect the Ground (System ground) to the PGND. CREG2 - IC internal power supply of 1.8V/3.3V.connects to 2.2 μF capacitor. Connects to power supply of MCU (VDD, EVDD0) in the package. Rev.1.00 2015.07.15 Page 24 of 34 Short Sheet I/O Function REGC Note 1 Pin name - IC internal power supply and a regulator output of 2.1V. A capacitor (0.47 μF to 1 μF) must be connected between REGC and GND. ACDRVIN Input 2.4.1 Supply voltage terminal for charge pump circuit of the input control FET. REGC This port is a regulator output stability capacitor connect pin for internal operation. It needs to connect to GND0 through a capacitor (0.47 to 1uF).Also uses good characteristics capacitor to stabilize an internal power supply. REGC GND0 Note Keep the wiring for the broken-line part in the above figure as short as possible. 2.4.2 VCC_FG,VCC_CHG, VBAT, GND0, PGND (1) VCC_FG, VCC_FG is a power supply pin for Fuel Gauge circuit. Apply power supply voltage to VCC_FG pin from external power supply (Adapter/USB etc) or battery(Diode OR). (2) VCC_CHG VCC_CHG is a power supply pin for Charger circuit. Apply power supply voltage to VCC_CHG pin from external power supply (Adapter/USB etc) through ACFET. (3) VBAT VBAT is the positive input terminal of lithium-ion battery 3. This is a reference voltage input pin of charge FET control circuit. Apply highest potential of all battery cells to VBAT. (4) GND0, PGND GND0, PGND are ground potential pin. GND0 connects to the negative input terminal of lithium-ion battery 1. PGND connects to the System Ground. 2.4.3 CREG2 This pin is a regulator output stability capacitor connect pin for internal operation. CREG2 connects to GND0 through a capacitor (2.2uF). Rev.1.00 2015.07.15 Page 25 of 34 Short Sheet Note: Keep the wiring for the broken-line part in the above figure as short as possible. 2.4.4 ACDRVIN Supply voltage terminal for charge pump circuit of the input control FET. 2.5 Series Regulator This IC incorporates a low-dropout VREG1 and VREG2 voltage source. VREG1 is used as the power source of A/D converter, current integrating circuit. VREG2 is used as 1.8V/3.3 V power supply. Figure 2-7 shows the Block Diagram of Series Regulator. Pch MOS transistors are used for output control. No external resistor or equivalent is required because output voltages are adjusted in the IC. Attach a 2.2 μF capacitor to the VREG2 to suppress input and load fluctuations. The settling time after input, output, and load fluctuations should be 10 ms as a standard value. Figure 2-7 Series Regulator Circuit VCC_FG Reference voltage source VREG2 (1.8/3.3V) + - CREG2 VREGpull (to AN0,AN1,AN2 pull up reference) VREG2 + - GND (Internal) VREG1 (1.2V) to A/D converter GND Rev.1.00 2015.07.15 Page 26 of 34 Short Sheet 2.6 Reset Circuit The reset circuit makes RESETOUT pin H level or L level by an output of power-on reset circuit or a reset request from MCU runaway detection circuit. The reset circuit monitors VREG2 output voltage of the regulator circuit. When the reset circuit detects voltage more than the reference value RESETOUT pin output becomes high level. When the reset circuit detects voltage lower than the reference value, the RESETOUT pin output signal becomes low level. The reset circuit comprises comparators, a reference voltage, a Delay circuit, bleeder resistors, and N-ch transistor. The reset circuit output is N-ch transistor, RESETOUT output is high or low level depend on pull-up resistor built-in RESETOUT pin. The reset circuit provides hysteresis for the detection voltage and the cancel voltage. RESETOUT pin connect to RESET pin internally. Figure 2-8 shows the Block Diagram of Reset circuit. Figure 2-8 Reset circuit VREG2 VREG2 RESETOUT Reset request from MCU runaway detection circuit RESETN OUTPUT Delay Power on reset AFE reset circuit RESETN input MCU RAJ240500 Rev.1.00 2015.07.15 Page 27 of 34 Short Sheet 2.7 Serial Communication Interface Each serial interface supported by this product has the following features. 2.7.1 3 wire serial I/O (CSI11, CSI21) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI). [Data transmission/reception] Data length of 7 or 8 bits Phase control of transmit/receive data MSB/LSB first selectable Level setting of transmit/receive data [Clock control] Master/slave selection Phase control of I/O clock Setting of transfer period by prescaler and internal counter of each channel Maximum transfer rate During master communication: Max. f CLK/4 Note During slave communication: Max. fMCK/6 Note [Interrupt function] Transfer end interrupt/buffer empty interrupt [Error detection flag] Overrun error It cannot be corresponding to SNOOZE mode in this product. Note Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics 2.7.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be implemented by using timer array unit with an external interrupt (INTP0). [Data transmission/reception] Data length of 7, 8, or 9 bits Select the MSB/LSB first Level setting of transmit/receive data and select of reverse Parity bit appending and parity check functions Stop bit appending [Interrupt function] Rev.1.00 2015.07.15 Transfer end interrupt/buffer empty interrupt Error interrupt in case of framing error, parity error, or overrun error Page 28 of 34 Short Sheet [Error detection flag] Framing error, parity error, or overrun error It cannot be corresponding to LIN-bus and SNOOZE mode in this product. Simplified I2C (IIC11) 2.7.3 This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I 2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master. Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop conditions are observed. [Data transmission/reception] Master transmission, master reception (only master function with a single master) ACK output functionNote and ACK detection function Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) Manual generation of start condition and stop condition [Interrupt function] Transfer end interrupt [Error detection flag] * Parity error (ACK error), or overrun error [Functions not supported by simplified I 2C] Slave transmission, slave reception Arbitration loss detection function Wait detection functions Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn bit (serial output enable register m (SOEm)) and serial communication data output is stopped. See the processing flow in 10.7.3 (2) for details. 2.8 Conditioning circuit The conditioning circuit is equipped with a function to internally discharge each cell of the battery connected. This function can decrease the voltage of an overcharged battery, which increases the safety of the battery pack. In addition, voltages between connected battery cells can be the same voltage, allowing full charge of all cells. This enables the battery pack to be used for a long period. The MCU selects a cell for self-discharge. Conditioning control is enabled by controlling the switches with the serial data from the MCU. The conditioning circuit comprises MOS switches and logic circuit. Any battery cell (Vcell1 to Vcell3) can be set for self-discharge by setting the CDRON0 to CDRON2 bit in the COND register. Figure 2-9 shows the Block Diagram of Conditioning Circuit. Figure 2-9 Block Diagram of Conditioning Circuit Rev.1.00 2015.07.15 Page 29 of 34 Short Sheet VIN3 CDRON2 bit CDRON1 bit CDRON0 bit Switch control circuit Vcell3 VIN2 Vcell2 VIN1 Vcell1 GND0 2.9 Fuse control circuit The fuse control circuit is used for a system controlling a fuse used for cutting charge/discharge path at the time of the abnormality. In addition, this fuse control circuit is able to read the failure mode identification register data from MCU after the fuse was cut off. It is possible to identify the failure mode. Figure 6 shows Example for the Fuse Control System. (1) Fuse control When abnormal state is detected by MCU write the FUSECUT0, FUSECUT1 bit in the AFECON2 register to 11b, FUSEOUT pin becomes High level, and turn on the fuse cutting FET. (2) The failure mode identification It can read a state of FUSEOUT pin by reading the FUSEMON bit in the AFECON3 register. The FUSEOUT pin becomes HiZ level when VCC level output can’t be controlled by fuse control function. Therefore it can detect a state that the fuse cutting FET is ON by the fuse cutting FET by reading the FUSEMON bit. Input of FUSEOUT pin connects to P06/INTP11 of MCU internally, when FUSEOUT pin becomes VCC level it can detect external interrupt of MCU. Rev.1.00 2015.07.15 Page 30 of 34 Short Sheet By INTP11 interrupt during fuse cut off, write the values of FUSECUT0, FUSECUT1, FUSEMON bit in the flash memory. To read that written data from flash memory after fuse was cut off, it is possible to identify the failure mode. The Interrupt request pin of FUSEOUT that connects to P06/INTP11 of MCU internally is the INT_AFE_ANL (abnormal interrupt). Note. INT_AFE_ANL is shared many AFE causes of interrupt. Therefore, confirm a cause of FUSEOUT pin by reading the FUSEIR bit in the INTIR register. Figure 2-10 Example for the Fuse Control System To Bat To FET/Pack+ 2nd protection IC NMOS-FET for Fuse control 600Ω max FUSEOUT VCC Other interrupt request Fuse interrupt FUSEMON bit FUSEMCU0 bit FUSEMCU1 bit AFECON3 register AFECON2 register AFE local bus 2.10 MCU runaway detection Circuit MCU runaway detection circuit detects MCU runaway event. It monitors CPU runaway condition independently in addition to MCU watchdog timer. MCU runaway detection circuit consists of pre-scaler to divide AFE on-chip oscillator clock and 16 bits counter. Counter overflow time is selectable from 2, 4 and 8 sec. Table 2-10 shows MCU runaway detection circuit specification. Rev.1.00 2015.07.15 Page 31 of 34 Short Sheet Table 2-10 MCU runaway detection circuit specification Item Specification Overflow time 2, 4, 8 sec. Count source AFE on-chip oscillator divided by 4 Counter bit length 19 bits Operation of the overflow (1)overflow for first time ・set the WDTIR bit to 1 (2)Overflow for second time when the MTRSEL bit is “0” ・clear the FETC bit and the FETD bit to 0 when the MTRSEL bit is “1” ・clear the FETC bit and the FETD bit to 0 ・MCU runaway detection reset is generated. Refresh conditions ・P76 of MCU is applied to H pulse to WDTIN pin Note . ・Power-on reset ・Overflow time change Note the P76 of MCU is connected to WDTIN inside package. Also the WDTIN incorporated the pull-down resistor. Rev.1.00 2015.07.15 Page 32 of 34 Short Sheet 3. Package Dimension 40-pin plastic mold QFN (5.0mm x 5.0mm) Note : The package information above is tentative and subject to change. Rev.1.00 2015.07.15 Page 33 of 34 Short Sheet Revision History Rev. 1.00 Rev.1.00 2015.07.15 Date 2015/07/15 Page All History Comment First official version Page 34 of 34