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Noise, Crosstalk, and Power Consumption Overview In this lesson we will Examine a high-level view of noise and noise sources in digital systems. Introduce problem of power supply and ground noise and some of the root causes. Examine methods for mitigating power supply and ground noise. Examine both board level attack and a distributed or local attack. Analyze crosstalk and inductive coupling. Briefly examine ground planes and power consumption. The Real World Again Ideal systems Switch in 0 time Noise free No prop delay Consume no power Etc. Real systems Have all these problems Need to be aware of such problems Need to have tools to deal with them Important to remember No two systems alike Variation in physical world attributes Means must understand root cause of problems Noise Noise in electrical circuits Unwanted signals arising from number of sources Signals often random in nature Potential sources External electrical sources Coupled in from Machinery Electric lights Radio and television Telecomm equipment Internally generated Clocks Switching Reflected in power distribution - 1 of 18 - Coupling between signals Capacitive Inductive Thermal Problem tends to worsen with Increasing frequency Decreasing signal edges or other electrical features Problem exacerbated as denominators decrease Partial solution: reduce di or dv di dv , dt dt Let's Look at several of these Examine some ways to help solve Keep in mind there is no perfect solution Power Supply and Ground Noise Common Path Noise When signal sent from source to destination Must return via ground path Common path noise is product of Returning signal current and ground impedance Consider the following circuit Graham and Johnson page 263 In distributed system Value of parasitic inductance increasing with module separation - 2 of 18 - In both circuits Return current goes through common ground path Either can cause noise to be generated via Ground inductance Fundamentally we’re dealing with Ohm’s law To ensure low common path noise Must have low impedance ground connections between gates Vcc Zp Vcc Zs Zg More generally the signal path has three components 1. The ground path 2. The power path 3. Path between power and ground Noise can arise from voltage drops in any of these segments Graham and Johnson 266 267 Such recognition gives rise to following three general rules for dealing with such problems 1. Zg - Use low impedance (key word here) ground connections between gates a ground plane works very well. 2. Zp - Impedance between power pins on any two gates should be as low as impedance between ground pins. 3. Zs - Must be a low impedance path between power and ground. We'll talk about ways of achieving each of these Power Distribution Wiring As we've seen power supply wiring has Resistive component Inductive component - 3 of 18 - Resistance Remote Sense Let’s look at the resistance of the Power supply wiring first Important to recognize Where power supply is What the wiring is Power Supply M ZL Resistance of wiring easy to calculate Expected operating current known If resistance is problem Get larger diameter wire Also pure resistance Not a function of frequency ZL Zmeter -> infinity Power supply may also be designed with remote sense Sense the level at far end of distribution Automagically adjust Inductance Graham and Johnson page 265 Effects of inductance harder problem to deal with Rapidly changing signals Acting across power distribution inductance Induce voltage shifts between Supply and logic it feeds Such shifts are more sudden and larger Than those arising from wiring resistance Noise given by basic relationship v L di dt As dt decreases → V increases Some array logics support control of output rise and fall times We have three potential approaches to deal with problem 1. Use low inductance wiring 2. Use logic immune to power supply noise 3. Reduce size of charging currents Do these help 1. L - Inductance is logarithmic function of wire diameter Almost impossible to solve problem Getting larger wire alone - 4 of 18 - V = L (di/dt) DC 2. Logic - Differential logic signals almost completely immune Power supply fluctuation Not cheap Not particularly practical in many cases Some vendors moving in this direction 3. Reduce di/dt - two ways to accomplish Increase denominator Reduce numerator Reducing magnitude of charging currents lower level signals Involves board level filtering Let's look at problem in following circuit Graham and Johnson page 271 Assume We are switching to a logic high must charge capacitor Rise time of 5 ns 50 pf load capacitor 5-7 unit loads L1 I C1 DC Compute max di/dt From iC dV dT Plus a little calculus we get max di 1.52V C 1.5 x107 A / sec 2 dt T rise Assuming typical TTL signal →ΔV = 4.5V Assume we have two parallel power distribution paths Power Ground plane - 5 of 18 - wire glass epoxy ground plane Based upon such a configuration Next compute the inductance of the power supply wiring L according to Lpsw 10.16 X ln L X H D 2H 164nH D Inductance Length of wire Assume 10 in Height above ground Assume 0.1 in Diameter of wire Assume 18 AWG - 0.04in We now compute peak noise voltage Note: we’ll see that below certain frequencies Impedance of PSW is sufficiently low We don’t need to do anything Since V Lpsw di dt Vnoise Lpsw di 1.5 x107 164 x10 9 2.5V dt max To solve problem Graham and Johnson page 272 Install board level bypass C2 as shown Assumes The power supply is not on the board C2 is installed on the board - generally at the card edge Kirchoff's Current Law holds here Only smoothed current flows in this part of wiring Path for charging current shortened L1A C1 A L1B C2 DC power supply board - 6 of 18 - If impedance of C2 lower than power supply wiring From KCL majority of charging current for C1will flow through it Rather than the system power supply wiring ips iC1 A XC1 Xps XC2 iC2 In addition original parasitic inductance Split into two pieces L1A piece must be smaller than the original L1 Therefore produce smaller noise voltage drop Computing Board Level Bypass Cap We compute board level bypass cap as follows 1. Estimate max step change in supply current - I due to gate switching This will flow through the psw Don't know when gates will switch Assume all N gates switch simultaneously at some known frequency Parasitic capacitors all in parallel Imax N C Imax N C Vsignal t Vsignal rise 2. Determine max power supply noise logic can handle - Vnoise 3. Max common path impedance is going to be X max Vnoise max Imax Remember - this is an impedance Typically we can allocate all of the impedance to one lumped value If not must split up as follows (a) Ground connection (b) Power connection (c) Path between power and ground - 7 of 18 - 4. Figure inductance in power supply wiring - LPSW Combine with Xmax to find frequency below which power supply wiring is adequate That is - a low enough impedance XL j L | X L | L X max Vnoise max Imax 2 F Lpsw Want to determine frequency we start to get into trouble Gives us a worst case number If all gates switch together at frequency F = Fpsw substituting 3 into 4 Fpsw VL 1 IL 2 Lpsw From 4 | XL | VL X max IL FPSW X max 2 LPSW Will get less noise than Vnoise and power supply wiring adequate Signal can travel through psw and noise will be below Vnoise max 5. Below FPSW power supply wiring is fine – don’t need board level bypass. Above FPSW must add bypass cap to take over - To lower the impedance. Compute value of cap that has impedance Xmax at FPSW as XC 1 j C X max ω = 2 F …let F = Fpws - 8 of 18 - Cbypass 1 2 FPSW X max Local Bypass Capacitors Every printed circuit board needs Relatively large bypass cap to counteract Inductance of power supply wiring Single perfect cap on each board Could completely solve distribution problem We can compute the max frequency at which such a cap is effective A good cap should be effective between Fpsw and Fbypass X max 2 LPSW X Fboard bypass max 2 LC 2 FPSW parasitic XLC2 Fboard bypass will be driven by LC2 C2 Unfortunately no cap perfect As we know every cap has some series inductance For the one we just added we have - LC2 Impedance of LC2 increases with frequency Cap also has parasitic resistor Denoted equivalent series resistance – ESR Approximately 0.1 – 1.1 Ω Full capacitor impedance given as: XC F ESR j 1 C L From which we compute magnitude of cap impedance 1/ 2 2 1 2 XC F ESR 2 FL 2 FC - 9 of 18 - LC2 ESR As we saw earlier Such inductance causes impedance to increase rather than decrease At high frequencies Extent of problem depends upon Value of Fknee 0.5 F knee rise Impedance which must be maintained Best way to guarantee low impedance above Fbypass Add another cap with lower series resistance Remember how resistors in parallel add Total will be less than smallest We accomplish this by Paralleling a lot of small capacitors Sprinkle parallel array around circuit card Remember impedances in parallel This becomes the third piece of our solution We now see that three factors dominate impedance between power and ground Low frequencies 0 to Fpsw Middle frequencies - impedance of card level bypass Fpsw to Fbypass High frequencies Fbypass to Fknee - inductance of power distribution wiring - impedance of distributed cap array We design cap array as follows 1. Want system to work up to Fknee. Calculate how much inductance can tolerate at high frequency X L L 2 FL Fknee Ltot 0.5 Tr X max X T max r 2 Fknee - 10 of 18 - 2. Look up or measure series inductance of bypass caps (C3). Typical value around 1 - 5nH. Surface mount - through hole Since Lequivalent for N parallel inductors is Lequivalent Li N we must put put N in parallel to get Ltotal Thus we have Ltot LC 3 N Which is what we want – configuration reduces total inductance Use this figure to compute number of bypass caps N LC 3 Ltot Total array capacitance must have impedance less than Xmax at frequencies down to Fbypass. Recall LC2 is board level bypass. from above Fbypass X max 2 LC 2 From, XC 1 j C with XC = Xmax and = 2 Fbypass Carray 1 2 Fbypass X max - 11 of 18 - 4. Calculate capacitance of each element of the array Celement Carray N Example Let's consider CMOS board of 100 gates. Assume 10 pF loads and 5ns rise times. Fknee 0.5 5 ns Let the series inductance of cap be 5 nH and assume we want Xmax = 0.1 Thus X T Ltot max r 0.159nH L 5 nH N C3 32 Ltot 0.159nH Fbypass Carray X max 0.1 3.18MHz 2 LC 2 2 5nH 1 0.5 F 2 FbypassX max Celement Carray 0.016 F N Power and Ground Planes Parallel power and ground planes provide 3rd level of bypass capacitance Power and ground planes have Zero lead inductance No ESR - equivalent series resistance Help to reduce power and ground noise at high frequencies - 12 of 18 - Compute capacitance as follows C power plane r A d - 0.225 r A d Relative electric permittivity of insulator Assume 4.5 for epoxy PCB FR4 material Area of shared power-ground plane in2 Separation between planes Crosstalk and Loops We know from Ampere's Law Current flowing in wire will produce magnetic field Faraday's and Lenz's work Circuit moving in magnetic field has induced current Work of Gauss and others Charge and potential difference between two conducting surfaces Related by quantity called capacitance From these we see Mother Nature is conspiring against us When we have adjacent conducting paths Capacitive and inductive physics Couples signals from one circuit into the other Any time we have two circuits We have mutual capacitance Voltages in one circuit create electric fields Such fields affect other circuit Any time we have two loops We have mutual inductance Current in one loop creates magnetic field Such fields affect other loop - 13 of 18 - Crosstalk Crosstalk arises from mutual capacitance and inductance between circuits Will examine each component separately Consider simple circuit Graham and Johnson page 26 Let's only look at capacitance We model circuit as follows Circuit A CM Circuit B Intuitively we see Since can't change voltage across cap instantaneously Signal on A must appear on B The mutual capacitance CM injects current IM into circuit B Proportional to rate of change of voltage in circuit A, VA Can write simplified approximation as IM CM dVA dt IM is the crosstalk current Valid under following assumptions Coupled current is much smaller than primary current and does not load circuit A Coupled signal voltage in B smaller than signal on A Capacitor is large impedance compared to circuit B ground impedance Directs where current flows Can estimate crosstalk as fraction of driving voltage VA given Known mutual capacitance CM Fixed circuit rise time Tr Known impedance in receiving circuit RB Using Thevenin model 1. Derive max change in voltage per unit time from change in Circuit A dVA VA dt Tr 2. Compute mutual capacitive current IM CM VA Tr - 14 of 18 - 3. Compute the crosstalk current in Circuit B as the impedance in circuit times the induced current Induced crosstalk voltage given as V crosstalk IM RB 4. Compute the crosstalk signal as the ratio between The induced voltage in B with respect to the change in A V crosstalk IM RB RBCM VA VA Tr RBCM Tr V crosstalk VA Preventing or Reducing Crosstalk To prevent such coupling we have several alternatives circuit A Guarding Ground trace routed so as to cut path Guard trace grounded at one end Capacitance still exists Cannot couple in Guard circuit B Twisted Pair By twisting conductors Net crosstalk from alternating plus and minus coupling Cancels Ground Plane or Ground Grid Provides return path directly under trace Lowest inductance Smallest loop area Minimizes magnetic field interacting with other traces Ground plane best grid provides good alternative I(t) Circuit A Loops Graham and Johnson page 28 LM Any electronic circuit contains loops It's the only way they work Again from our studies of electromagnetic physics Changing electromagnetic field passing through circuit - 15 of 18 - Circuit B + V(t) Coupled noise source voltage Induces current in circuit Such fields are everywhere Radio and television stations Electric lights Let's look at following simple circuit The mutual inductance LM injects voltage VM into loop B Proportional to rate of change of voltage in circuit A Can write simplified approximation as di VcrosstalkLM A dt The above expression is valid under following assumptions Induced voltage across LM smaller than primary signal voltage and attaching LM does not load circuit A Coupled signal current in circuit B smaller than current in circuit A Secondary impedance is small compared to impedance to ground of circuit B Can estimate crosstalk as fraction of driving voltage VA given Known mutual inductance LM Fixed circuit rise time Tr Known impedance in driving circuit RA 1. Derive max change in voltage per unit time dVA V dt Tr 2. Assume loop A resistively damped by RA and current and voltage proportional to each other Compute current in A dV A di RA A dt dt VA rise R A di A dt di A V A dt R A rise 3. Compute mutual inductive noise - induced voltage Vcrosstalk LM V A R ATr - 16 of 18 - 4. Compute the crosstalk signal as the ratio between The induced signal and the causal signal Vcrosstalk L Crosstalk M VA R ATr To prevent such coupling we have several alternatives When laying out circuit Keeps such loops as small as possible Non-existent if possible Circuit A is preferable to Circuit B 1 2 circuit A 3 4 Power Consumption Depends upon Logic family Implementation Frequency of operation Load on the device Supply voltage Comprised of two components Static - DC Dynamic - AC Compute as P CL Co V 2f idcV V idc CL Co f Supply Voltage DC current External capacitive load Internal output capacitance Frequency of operation - switching frequency Frequency dependent portion arises From totem pole output configuration Both devices on for short time When ON both conducting CMOS DC Top or bottom device OFF Very low power consumption With logic low Sink current coming from gate circuit of succeeding device - 17 of 18 - 1 2 circuit B 3 4 With logic high Source current going to gate circuit of succeeding device AC Both devices ON for short interval Sink current now through both devices to ground TTL DC Top or bottom device OFF Higher power consumption With logic low Sink current coming from emitter or diode circuit of succeeding device With logic high Source current going to emitter or diode circuit of succeeding device AC Both devices ON for short interval Sink current now through both devices to ground Summary In this lesson we Examined a high-level view of noise and noise sources in digital systems. Introduced problem of power supply and ground noise and some of the root causes. Examined methods for mitigating power supply and ground noise. Examined both board level attack and a distributed or local attack. Analyzed crosstalk and inductive coupling. Briefly examined ground planes and power consumption. - 18 of 18 -