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Brief Papers_______________________________________________________________________________
Highly Linear Receiver Front-End Adopting MOSFET Transconductance
Linearization by Multiple Gated Transistors
Tae Wook Kim, Bonkee Kim, and Kwyro Lee, Senior Member, IEEE
Abstract—Highly linear receiver RF front-end adopting
MOSFET transconductance linearization by linearly superposing
several common-source FET transistors in parallel (multiple gated
transistor, or MGTR), combined with some additional circuit
techniques are reported. In MGTR circuitry, linearity is improved
by using transconductance linearization which can be achieved
by canceling the negative peak value of
of the main transistor
with the positive one in the auxiliary transistor having a different
size and gate drive combined in parallel. This enhancement,
however, is limited by the distortion originated from the combined
and harmonic feedback, which can greatly be
influence of
reduced by the cascoding MGTR output for the amplifier and by
the tuned load for the mixer. Experimental results designed using
the above techniques show IIP3 improvements at given power
consumption by as much as 10 dB for CMOS low-noise amplifier
at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without
sacrificing other features such as gain and noise figure.
Fig. 1. Simplified schematic of common-source circuit.
Index Terms—CMOS amplifier, CMOS mixer, derivative
transconductance cancellation, third-order input intercept point
(IIP3 ), third-order nonlinearity.
I. INTRODUCTION
L
INEARITY plays an important role in RF systems
because nonlinearity causes many problems, such as
harmonic generation, gain compression, desensitization,
blocking, cross modulation and intermodulation, etc. [1],
[2]. For example, nonlinearity in transmitter circuits, such as
upconversion mixers and driver/power amplifiers, generates
adjacent channel signals, and nonlinearity in receiver circuits,
such as low-noise amplifiers (LNAs) and mixers, is directly
related to immunity to the various interferences. Among
various distortions, even-order distortion caused by even-order
nonlinearity can easily be reduced by adopting a differential
signal processing architecture [3]. However, it is difficult to
reduce odd-order distortion. Among odd-order distortions, the
third-order intermodulation distortion (IMD ) is the most dominant nonlinearity component. The performance measure for
this nonlinearity is usually expressed by the third-order input
intercept point (IIP ) per DC power consumption (IIP DC),
since the third-order intercept point (IP ) is usually proportional
Manuscript received January 6, 2003; revised September 25, 2003. This work
was supported in part by the MICROS Research Center, KAIST.
T. W. Kim and K. Lee are with the Department of Electrical Engineering
and Computer Sciences and the MICROS Research Center, Korea Advanced
Institute of Science and Technology, Daejon 305-701, Korea (e-mail: [email protected], [email protected]).
B. Kim is with Integrant Technologies, Inc., Kyunggi-do 463-760, Korea.
Digital Object Identifier 10.1109/JSSC.2003.820843
Fig. 2. g and g of a CS 360/0.35-m MOSFET. Threshold voltage is about
0.66 V for this particular device.
to DC power consumption. Therefore, it is a great challenge
to increase IP DC for extremely low-power systems such as
ZigBee [4].
Several circuit techniques have been proposed to improve
the IIP of RF amplifiers. Most of them are based on negative feedback circuits. One of the most famous ones is series
feedback using source degeneration by resistor or inductor [5].
Source degeneration using an inductor is very plausible because
it does not increase the noise figure [6]. Another good example
is parallel feedback, such as cascode parallel feedback [7]. Even
though these methods are effective to enhance IIP , they have
problems of gain reduction. Actually, the enhancement in linearity is the result of the gain reduction. Although IIP can be
improved by the differential circuit technique [3], IIP is ultimately limited by the MOSFET transconductance nonlinearity
itself. In this regard, there have been several attempts to reduce
third-order transistor transconductance nonlinearity.
One good example is the superposition of an auxiliary transistor operating in triode region [8]. Another one is the same in
saturation region, known as the derivative superposition method
0018-9200/04$20.00 © 2004 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 3. Schematic illustration of g
positive peak of ST.
Fig. 4.
cancellation using MGTR. The size and gate bias of ST is chosen such that the negative g
Analyzed CS equivalent circuit and qualitative explanation of combined effect of g
in the HEMT community [9], and the multiple gated transistor
method (MGTR) in CMOS community [10]. Note that the superposition in triode region concept is not suitable for receiver
front-end because of the large power consumption.
In the area of mixer circuits, the Gilbert cell is certainly one
of the best candidates suitable for monolithic integration [11]. It
is composed of an RF transconductance amplifier and switching
stage, and its linearity is mostly determined by that of transconductance [12]–[15].
Therefore, it is very important to linearize MOSFET
transconductance for both RF amplifiers and mixer circuits.
peak of MT is cancelled by the
and harmonic feedback to linearity.
We have shown that MGTR is an effective way to linearize the
common-source (CS) MOSFET without increasing DC power
consumption [10]. However, it was also shown that the obtained
IIP DC improvement is much smaller than that expected from
linearity improvement in transconductance, which was shown
to be due to various other harmonic mixing [16].
In this brief, we propose that the use of MGTR combined
with other circuit techniques can indeed improve IP DC by
an order of magnitude. First, adopting MGTR combined with
cascode configuration, we show the design and fabrication results for 900-MHz CMOS LNA with IP DC improvement as
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 5.
225
has a negative peak value in the gate
see in Fig. 2 that
drive voltage range of 0.1–0.45 V (gate-to-source voltage range
of 0.76–1.11 V in Fig. 2), which is the usual bias voltage for
high-gain, low-noise, and low-power applications. Thus, linearity degradation is quite severe. In the MGTR amplifier, howof the main transistor (MT) can
ever, this negative peak of the
be cancelled by the positive peak value of a properly sized secondary transistor (ST), whose transfer characteristic is shifted
to the right by changing either the gate bias or the threshold
voltage as shown in Fig. 3. Note that, because ST is biased in
subthreshold regime, this linearization method does not consume any extra power.
It was shown later, however, that the third-order distortion
and harmonic feedback becaused by the combination of
comes dominant in the highly linearized transconductance am[16]. Therefore, we have to conplifier having very small
sider the role of various harmonics to further reduce IMD .
The effect of out-of-band termination on intermodulation distortion was originally analyzed for a bipolar common-emitter
amplifier circuit [17], and repeated for a FET one as follows:
Simplified schematic of cascode MGTR LNA.
IIP
(2)
Fig. 6.
Simplified schematic of MGTR mixer with tuned load.
(3)
large as 10 dB. Second, we report 7-dB IP DC improvement at
2.4 GHz for the CMOS mixer adopting MGTR and second-harmonic reduction techniques without sacrificing other RF characteristics such as gain and noise figure. Section II starts by reviewing the MGTR concept, then discusses the combined efand harmonic feedback to the nonlinearity of the
fect of
third-order transconductance linearized amplifier using MGTR,
and proposes cascode configuration to remove these effects. In
Section III, based on the above analysis, the MGTR mixer with
a second-harmonic reduction technique is proposed and discussed. In Sections IV and V, design and measurement results
are demonstrated and bias circuitry for MGTR as well as the
desensitivity against the manufacturing and temperature variations are discussed, followed by the conclusion in Section VI.
II. CASCODE MGTR CMOS LNA
Nonlinearity of CS FET amplifier mostly comes from
transconductance ( ) nonlinearity in the driving MOSFET
transistor. Using Taylor series expansion, the drain current of a
CS FET as shown in Fig. 1 can be expressed as
(1)
Here,
is a small-signal gate-to-source voltage and
indicates
order transconductance with respect to
.
It is well known that the coefficient of
in (1) plays an
important role in determining the IMD of an RF amplifier [8],
could be minimized by lin[16]. In MGTR, these coefficient
early superposing several CS FET transistors with proper bias
and size in parallel [9], [10]. As was shown in [16], we can
where
(4)
Here,
indicates the source impedance, and
and
are the conductance functions to be defined at the suband the second harmonic frequency
harmonic frequency of
is related to equivalent IMD voltage
of , respectively.
to the IMD response of the drain current nonlinear term and
is the linear transfer function for the input voltage of
[17].
shows the relationship of how output current
works for IMD response. As graphically explained in Fig. 4,
comes from the third-order nonlinearity in the drain current
comes from the combined effect of the second-order
and
nonlinearity generating the second-order product, which is then
mixed with the fundamental tones, yielding the third-order products [17]. This self-interaction is due to the multiple feedbacks
in the circuit mainly by the gate–drain capacitance [16], [17].
Equations (2)–(4) implies that linearity (IP ) can indeed be improved first by reducing , but that, as can be seen in (3), when
becomes negligibly small,
becomes dominated
by
, which is proportional to the square of
[see (4)]. As
peak can effectively
can be inferred from Fig. 2, although
is still appreciable.
be cancelled using MGTR, the value of
. One of the
Therefore, we have to devise a way to decrease
best ways to achieve this is to increase both
and
.
was originally
In the CS FET circuit shown in Fig. 4,
defined in [17], which can be approximately given as
(5)
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Fig. 7. (a) Simplified schematic and plot of impedance versus frequency of conventional current source and LC resonating RF current source. The LC resonating
RF current source has maximum impedance at resonating frequency. Simplified schematic and simple explanation to common node (node A, B, C) characteristics
of: (b) conventional single balance mixer; (c) conventional folded cascode mixer; and (d) LC folded cascode mixer.
(a)
(b)
Fig. 8. (a) Photomicrograph of cascode MGTR LNA whose size is
400 m 500 m. (b) Photomicrograph of MGTR mixer with tuned load
whose size is 1200 m 800 m.
2
2
Fig. 10.
LNA.
IP comparison between conventional cascode and cascode MGTR
TABLE I
MEASUREMENT SUMMARY AND COMPARISON OF CASCODE MGTR
LNA AND CONVENTIONAL CASCODE LNA
Fig. 9.
IMD reduction vs ST gate drive voltage of cascode MGTR LNA.
Here,
and
are the impedance looking into the source
and into the load, respectively (see the analyzed CS equivalent
circuit in Fig. 4), and
is the unit current cutoff angular fre. Note that
is much
quency defined as
larger than
.
is on
In a typical CS FET amplifier, the magnitude of
. Thus, the second term in the numerator
the order of
,
of (5) is comparable to one. Furthermore, because
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 11.
load.
IP increase versus ST gate drive voltage for MGTR mixer with tuned
in the denominator is the most dominating factor.
to less than
Therefore, it is very important to reduce
one. In other words,
should be decreased as much as possible. In [17], the harmonic tuning is used to reduce . In this
paper, however, we first propose to use cascode configuration to
for RF amplifiers, as shown in Fig. 5. In the cascode
reduce
configuration,
is decreased to
. Although this is not as
good as the harmonic tuning, our approach is more plausible because it provides performance as good as the harmonic tuning
method and does not require large passive LC components as in
[17].
III. MGTR MIXER WITH TUNED LOAD
A highly linear mixer using MGTR in the transconductance
combined with tuned load, which reduces harmonics at output,
is proposed. Fig. 6 shows the circuit schematic diagram for this
circuit, which is composed of an LC folded cascode mixer [18]
and an MGTR transconductor operating at 2.4-GHz ISM band.
and
operate as switchs.
and
are load resistors
which also work as common-mode feedback circuits with
and .
and
reject the local oscillator (LO) signal at IF.
Fig. 7 explains why the LC folded cascode mixer is the
best configuration for the MGTR transconductor. As shown in
and
are resonant at , providing maximum
Fig. 7(a),
load for the signal, while small impedance at the second-harand
frequency as well as at
monic frequency of
. As was discussed for the
the subharmonic frequency of
amplifier case, it is well known that
,
components at
the CS node (node A, in Fig. 7) worsen the linearity in the
conventional single balanced mixer, which is greatly reduced
using LC resonating RF current source [see Fig. 7(a)] as shown
in Fig. 6. Also, the LC resonating RF current source removes
signal, which degrades linearity in conventional
the
single balanced mixer [19]. It should be noted here that
harmonic termination is adopted in [19], while the
tuned
load is used here, to reduce the
component at the output.
Moreover, linearization using MGTR is most effective when
the driver FET used for the transconductance amplifier is in
saturation region, i.e., at large V . The folded cascode circuit
in Fig. 7(d) helps us to have large voltage headroom for V ,
making the driver FET always in saturation region.
227
Fig. 12.
load.
IP comparison of conventional mixer and MGTR mixer with tuned
IV. DESIGN AND FABRICATION OF CASCODE MGTR LNA
AND MGTR MIXER WITH TUNED LOAD
A. 900-MHz Cascode MGTR LNA
The 900-MHz cascode MGTR LNA, whose schematic
is shown in Fig. 5, is designed and fabricated using only
CMOS in 0.35- m SiGe BiCMOS process. Fig. 8(a) shows a
photomicrograph of the cascode MGTR LNA whose die area
is 400 m 500 m. The size of the MT is 360/0.35 m and
that of ST is 440/0.35 m. The MT is typically biased at gate
drive (V
V
V , where V
V) of 0.24 V
of ST is negative, i.e., ST is in subthreshold regime
and V
when there is no input signal. Fig. 9 shows the measured IMD
reduction versus V
of ST, while V
of MT is fixed at
0.24 V. Note that maximum IMD reduction as large as 20 dB
is obtained. Fig. 10 shows the measured IP at maximum IMD
reduction and comparison of conventional cascode amplifier.
Note that IP improvement at least as large as 10 dB is obtained
from the proposed cascode MGTR over the 0.13-V window of
variation of ST, which is wide enough to cover process
V
variation. The OIP of the proposed amplifier is 25.6 dBm at
7.8-mA current consumption. Measurement performance and
comparison with conventional amplifier are summarized in
Table I. Although it has slightly higher noise figure because of
ST, it improves IP by an order of magnitude.
B. MGTR Mixer With Tuned Load
A 2.4-GHz harmonic tuned MGTR mixer with LC folded
cascode structure, shown in Fig. 6, is designed and fabricated using 0.18- m CMOS technology. Fig. 8(b) shows
a photomicrograph of the MGTR mixer whose die area is
1200 m 800 m. The MT is biased at a gate drive of 0.14 V
(V
V) and ST bias is below V . Input is terminated
with a 50- resistor. Fig. 11 shows measured IP increase
of ST where MT is fixed at V
of 0.14 V. Maxversus V
imum IP increase is 7 dB and IP improvement is 5–7 dB over
a 0.1-V range which can cover process variation. Fig. 12 shows
the measured IP at maximum IMD reduction and comparison
of conventional single-gate LC folded cascode mixer which has
only one transistor at transconductor stage. The measurement
results of the conventional mixer and the harmonic tuned mixer
are summarized in Table II. A higher noise figure is obtained
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TABLE II
MEASUREMENT SUMMARY AND COMPARISON OF CONVENTIONAL MIXER AND MGTR MIXER WITH TUNED LOAD
Fig. 13.
Bias circuitry for MGTR. (a) Voltage bias. (b) Current mirror bias.
6
6
Fig. 14. (a) IIP over process, V
( 30%), and temperature variation for voltage bias [Fig. 13(a)]. (b) IIP over process, V
(30%), and temperature variation
for current mirror bias [Fig. 13(b)]. MG and SG stand for MGTR and single gate, respectively. TT, SS, and FF stand for typical, slow, and fast model, respectively.
Supply voltage variation is assumed 30%.
Fig. 15.
Digital calibration circuitry for MGTR bias.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
from a 50- resistive input termination. Input matching that
would improve the conversion gain and lower the noise figure
is excluded, because the purpose of this paper is to find out how
much the proposed technique increases IP and degrades other
characteristics. The result shows the IP increase is almost an
order of magnitude, while the noise figure and gain degradation
due to ST is insignificant.
V. BIAS CIRCUITRY FOR MGTR
Although it seems complicated to generate MGTR bias,
conventional current mirror bias circuitry is enough for MGTR
bias. Current mirror bias and voltage bias, shown in Fig. 13, are
compared for process, temperature, and supply voltage (V )
variation with the 0.18- m CMOS BSIM3v3.2 model using a
commercial simulation tool. For this simulation, the transconductance stage of a conventional single gate mixer and the
MGTR mixer are used. As shown in Fig. 14, the current mirror
biased MGTR circuit can provide stable IIP improvement
over process, temperature, and supply voltage variations, while
the voltage biased MGTR circuit cannot. When voltage bias is
applied to MGTR, there is some degradation of the IIP improvement, while current mirror bias ensures at least 8 dB IIP
improvement at any variation. This is because current mirror
bias can provide stable bias condition for such variations. As
shown in Fig. 15, the digital trimming circuit can be applied
for further stable
cancellation in MGTR for the receiver
system. Four test chips using this scheme were measured, and
at least 5-dB mixer IIP improvement was obtained, under any
circumstance with the proper calibration algorithm [20].
VI. CONCLUSION
Highly linear CMOS LNA and mixer circuits adopting
MOSFET transconductance linearization by linearly superposing several common-source FET transistor in parallel
(MGTR), combined with some additional circuit techniques
such as cascode for the amplifier and harmonic tuned load
mixer, were reported. Experimental results showed IP improvements at given power consumption by as much as 10 dB
for the LNA at 900 MHz and 7 dB for the Gilbert cell mixer
at 2.4 GHz without sacrificing other features such as gain and
noise figure.
ACKNOWLEDGMENT
The authors would like to thank Dr. B. K. Ko of Integrant
Technologies for his continuous support.
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