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Mahesh. P 99029, International Institute of Information Technology, Gachibowli, Hyderabad, 500019 [email protected] http://gdit.iiit.net/~mahesh/ Education History B-Tech in Computer science, specialization in VLSI o International Institute of Information technology, Hyderabad o Expected May 2003. o Aggregate CGPA : 9.02 ( for 6 semesters) Intermediate (M.P.C) o Vikas Junior College, Guntur o 1997-99 o Achieved 93.6%. S.S.C o Shirisha Vidya Nikethan, Suryapet, AP o 1996-97 o Achieved 84% Skill Set: Operating Systems: Linux, UNIX, Dos, Windows 9x/NT/2000/ME/XP Programming Languages: C, C++, Java, SQL, Perl, RDBMS: MySQL, Ms-Access Web Technologies: HTML, CGI, JavaScript Project related Software Development Concepts: UML Descriptive Languages: VHDL, Verilog Tools: Active HDL, ModelSim, Leonardo Spectrum, FPGA Express, Matlab Concepts: I have an exposure to Software Engineering, System Software, Computer Networks, Compiler Design, Theory of Computation Computer Organization, Digital Logic & Design, Artificial Intelligence, Computer Graphics, Operating System Concepts, System Analysis & Design, Discrete Mathematics, Micro Processors, Digital Signal Processing, VLSI concepts. Work Experience Summer Internship at CMC ltd Hyd, 2001. Teaching assistant for Artificial Intelligence course in 7th semester. Doing final year project in Mentor Graphics, under guidance of Mr. Krishna Kumar Assets Recipient of Prathiba Merit award for securing 27th rank in EAMCET'99 (given by Govt. of AP). Listed in Deans list in IIIT for spring 2001 semester Listed in Deans list in IIIT for fall 2002 semester Major Projects: Assertion Monitor Based Verification(ABV) Methodology Technologies/Tools used Verilog, ModelSim, Active HDL Development of assertion monitor library, that can be instantiated in the design being modeled using Verilog for design validation and verification. Also the analysis of Assertion Monitor Based Verification Methodology is to be done. My contribution to this project includes: Study of assertion monitor based verification methodology Implementation of Assertion monitors using Verilog Studying some applications and verifying them using ABV Analyzing ABV over different methodologies Assertion Monitor library is built and now different applications are being studied. Description Contribution Status Dr.M.B.Srinivas,VLSI/Embedded Systems research center, IIIT-Hyd Mr. KrishnaKumar, Mentor Graphics, Hyderabad. Reference Simulation and synthesis of core of microcontroller Technologies/Tools used VHDL, Active HDL, Leonardo Spectrum Simulation and synthesis of core of a microcontroller. We modeled 8051 microcontroller core and simulated it. Then this core is synthesized using Leonardo Spectrum My contribution includes: Modeling of 8051 microcontroller core using VHDL Synthesis of the modeled 8051 core using Leonardo Spectrum. 8051 core is modeled and tested. This has to be ported on to FPGA board. Dr. M.B. Srinivas, VLSI/Embedded System Research center, IIITHyd Description Contribution: Status Reference Simulation and synthesis of DES algorithm Technologies/Tools used Description VHDL, Active HDL, Leonardo spectrum Simulation and synthesis of Data Encryption Standard Algorithm on FPGA. Implemented in VHDL and tested using C. Status My contribution includes: Modeling DES algorithm using VHDL Synthesis of modeled DES algorithm Porting on to FPGA board DES algorithm is simulated and synthesized and ported on to FPGA board. Reference Dr. M.B.Srinivas, VLSI/Embedded systems Research center IIITHyd Contribution Audio/Video Library automation Technologies/Tools used Description Contribution Status Reference C++, Qt, MySQL Database system which will keep track of daily transactions of an Audio/Video cd library. Front end is developed using C++ programming and Qt. Backend contains MySQL database. My contribution includes: Designing Database and implementing in MySQL Implementing interface using Qt Writing programs to access Mysql database using C++ Development of complete product. Working Audio/Video Library system is implemented. Prof. Kamal, IIIT-Hyd Alumni System HTML, Perl, CGI, MySQL Technologies/Tools used Description Contribution: Status Reference A web based system which stores and keeps track of information of old students. Its HTML interface is generated by Perl and CGI, with backend containing a database implemented using MySQL. My contribution includes Designing alumni system Writing CGI scripts to generate html pages dynamically Designing database in MySQL Writing scripts to access the database in PERL Working alumni system is designed and implemented Prof. Sangal IIIT-hyd, Prof. Vishal Garg IIIT-Hyd Areas of interest: VLSI Theory of Computation Embedded Systems Career Objective: To endeavor for a nourishing career in a quality environment where my knowledge and experiences can be shared and enriched in the orientation of firm’s goals. Other details: Data of Birth Address Phone Keywords that describe me Miscellaneous : 14th March, 1983 : Mahesh. P S/o Mr. P. Yadagiri C/o Mr. M. Narasimha Reddy, Co-operative bank colony, Nagole, Hyderabad-69. : 91-(40)4220196 : Hardworking, deterministic. : My interests include reading books and playing computer games.