Download Q. TTL NAND GATE: (Only Comp)

Q. TTL NAND GATE: (Only Comp)
(i)
T1 ON in forward mode and is operating in saturation as there is only a leakage current
from T2 available as collector current, i.e. T1 operates with a large base current and
negligible collector current where IC MAX = 0. The input logic LO voltage is taken as 0.1V.
Then:
Node N1 : VN1  Vi  VBE1 SAT  0.1  0.8  0.9V
(ii)
With T1 operating in saturation, its collector-emitter voltage is VCE SAT = 0.1V so that:
Node N2 : VN2  Vi  VCE1 SAT  0.1  0.1  0.2V
(iii)
With T4 operating at the point of cut-in its base current and hence its collector current can
be taken as zero. This means that there is no voltage drop across either resistor R1 or R3
and so the potential at both sides of these resistors is equal to the supply voltage VCC
giving:
Node N3, Node N5 : VN3  VN5  VCC  5V
(iv)
Node N4 is pulled low by the resistor R2 which has no current flowing through it so that:
Node N4 :
(v)
VN4  0V
Finally, with T4 operating at the point of cut-in:
Node N6 : VN6  VN3  VBE4 CUT -IN  5  0.6  4.4V
VCC
R3
R1
130
1.6 k
N5
RB
N3
4k
N1
Input 1
Input 2
T4
N6
N2
T2
T1
N7
N4
Output
(no load)
T3
R2
1k
and with the diode at cut-in also:
Node N7 : VN7  VN6  VD CUT -IN  4.4  0.4  4.0V
Q. TTL CHARACTERISTICS (Only Comp)
Fan-in is the maximum number of inputs to a gate. Although physical considerations limit fan in,
more pragmatic factors, such as limitations on the number of pins possible on IC packages and
their standardization predominate. TTL NAND gates typically provide 1, 2, 4, or 8 inputs. If
more than eight inputs are required, then a network of NAND gates must be employed.
Fan-out specifies the number of standard loads that the output of a gate can drive without
impairing its normal operation. A standard load is defined to be the amount of current required to
drive an input of another gate in the same logic family. Due to the nature of TTL gates, two
different fan out values are given, one for HIGH outputs and one for LOW outputs.
Noise immunity is a measure of the ability of a digital circuit to avert logic level changes on
signal lines when noise causes voltage level changes.
The propagation delay time for a gate is the time required for the output to respond to a change
in an input. In all practical gates, a time lag exists between an input change and the
corresponding output response. The time interval between the instants when the input and output
change states is not a satisfactory measure of the delay time of a logical device
The average propagation delay time tp is then defined by:
tp = (tPHL + tPLH) / 2.
Power Dissipation:
As the power dissipation in a system increases, more heat must be dissipated from the system
and larger, more costly power supplies are required. The static power dissipation PDP of an IC is
the product of the supply voltage VCC and the static power supply current ICC. If, on the
average, the output of a device is HIGH half the time and LOW the other half, then the average
power supply current is ICC = (ICCH + ICCL)/2.
Q. Compare TTL and CMOS (Only Comp)
Q. What is VHDL? What are its features?
The VHSIC Hardware Description Language (VHDL) is an industry standard language used to
describe hardware from the abstract to concrete level.
The language not only defines the syntax but also defines very clear simulation semantics for
each language construct.
§ It is strong typed language and is often verbose to write.
§ Provides extensive range of modeling capabilities, it is possible to quickly assimilate a core
subset of the language that is both easy and simple to understand without learning the more
complex features.
Features of VHDL:
A Simulation Modeling Language
VHDL has many features appropriate for describing the behavior of electronic components
ranging from simple logic gates to complete microprocessors and custom chips.
A Design Entry Language
Just as high-level programming languages allow complex design concepts to be expressed as
computer programs, VHDL allows the behavior of complex electronic circuits to be captured
into a design system
A Test Language
One of the most important aspects of VHDL is its ability to capture the performance
specification for a circuit, in a form commonly refered to as a test bench.
A Netlist Language
VHDL is a powerful language with which to enter new designs at a high level, but it is also
useful as a low-level form of communication between different tools in a computer-based design
environment.
A Standard Language
One of the most compelling reasons for you to become experienced with and knowledgeable in
VHDL is its adoptance as a standard in the electronic design community. Using a standard
language such as VHDL will virtually guarantee that you will not have to throw away and recapture design concepts simply because the design entry method you have chosen is not
supported in a newer generation of design tools.
Q. Differentiate between FPGA and CPLD. (Only Comp)
1. FPGA contains up to 100,000 of tiny logic blocks while CPLD contains only a few blocks of
logic that reaches up to a few thousands.
2. In terms of architecture, FPGAs are considered as ‘fine-grain’ devices while CPLDs are
‘coarse-grain’.
3. FPGAs are great for more complex applications while CPLDs are better for simpler ones.
4. FPGAs are made up of tiny logic blocks while CPLDs are made of larger blocks.
5. FPGA is a RAM-based digital logic chip while CPLD is EEPROM-based.
6. Normally, FPGAs are more expensive while CPLDs are much cheaper.
7. Delays are much more predictable in CPLDs than in FPGAs.
Q. FPGA Architecture (Only Comp)
FPGA - Field Programmable Gate Array
FPGAs are a distinct from SPLDs and CPLDs and typically offer the highest logic capacity. An
FPGA consists of an array of logic blocks, surrounded by programmable I/O blocks, and
connected with programmable interconnect. A typical FPGA contains from 64 to tens of
thousands of logic blocks and an even greater number of flip-flops. Most FPGAs do not provide
100% interconnect between logic blocks (to do so would be prohibitively expensive). Instead,
sophisticated software places and routes the logic on the device much like a PCB autorouter
would place and route components.
A generic description of an FPGA is a programmable device with an internal array of logic
blocks, surrounded by a ring of programmable input/output blocks, connected together via
programmable interconnect. There are a wide variety of sub-architectures within this group. The
secret to density and performance in these devices lies in the logic contained in their logic blocks
and on the performance and efficiency of their routing architecture.
The FPGA architecture consists of three types of configurable elements-
(i) IOBs – a perimeter of input/output blocks
(ii) CLBs- a core array of configurable logic blocks
(iii) Resources for interconnection
The IOBs provide a programmable interface between the internal; array of logic blocks (CLBs)
and the device’s external package pins. CLBs perform user-specified logic functions, and the
interconnect resources carry signals among the blocks.
A configurable program stored in internal static memory cells determines the
logic functions and the interconnections. The configurable data is loaded into the device during
power-up reprogramming function.
FPGA devices are customized by loading configuration data into internal memory cells. The
FPGA device can either actively read its configuration data out of an external serial or byte-wide
parallel PROM (master modes), or the configuration data can be written to the FPGA
devices(slave and peripheral modes).
Q. What is shift registers? What are its types or modes?
The Shift Register
The Shift Register is another type of sequential logic circuit that can be used for the storage or
the transfer of data in the form of binary numbers. This sequential device loads the data present
on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name
“shift register”.
Serial-in to Parallel-out (SIPO) Shift Register
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs
still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned
LOW again to logic “0” giving us one data pulse or 0-1-0.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA to QD.
Serial-in to Serial-out (SISO) Shift Register
This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output, the DATA
leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to SerialOut Shift Register or SISO.
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PA to PD.
Parallel-in to Parallel-out (PIPO) Shift Register
This type of shift register also acts as a temporary storage device or as a time delay device
similar to the SISO configuration above. The data is presented in a parallel format to the parallel
input pins PA to PD and then transferred together directly to their respective output pins QA to QD
by the same clock pulse.