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Design Styles
Full-custom
 Cell-based
 Gate array
 Programmable logic

 Field programmable gate array (FPGA)
Full-Custom ASIC
layout-based
 the designer draws
each polygon “by
hand”
 More compact design
but longer design
time

Cell-Based ASIC



used predefined
building blocks (“cells”)
from library
designer creates a
schematic that
interconnects these
cells
layout = placement &
interconnection of cells
Gate Array
Each chip is
prefabricated with
an array of identical
gates or cells.
 The chip is
“customized” by
fabricating routing
layers on top.
 Time to market, cost

Field programmable gate array



Chips are prefabricated
with logic blocks and
interconnects.
Logic and interconnects
can
be
programmed
(erased
and
reprogrammed) by users.
No fabrication is needed.
What is an FPGA





A Field Programmable Gate Array (FPGA) is a semiconductor chip
containing programmable logic components and programmable
interconnects.
the FPGA's function is defined by a user's program rather than
by the manufacturer of the device.
An integrated circuit that contains many (64 to over 10,000)
identical logic cells that can be viewed as standard components
A hierarchy of programmable interconnects allows the logic
blocks of an FPGA to be interconnected as needed by the system
designer.
These logic blocks and interconnects can be programmed after
the manufacturing process by the customer so that the FPGA can
perform whatever logical function that is needed.
FPGA CLASSES



Write Once or Antifuse Based FPGA
 Interconnects are formed by blowing high current
 one-time programmable in special programming machine
Nonvolatile FPGA
 A program retains in memory even when power is turned-off
 reprogrammable, when new prototype needed
Volatile or SRAM Based FPGA
 FPGA needs to be configured each time when power turned -on
FPGA - Generic Structure
Logic block
(CLB)
FPGA building blocks:


I/O
I/O
I/O

Programmable logic blocks
Implement combinatorial and
sequential logic
Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
Programmable I/O blocks
Special logic blocks at the
periphery of device for
external connections
Interconnection switches
I/O
Other FPGA Building Blocks
Clock distribution
 Embedded memory blocks
 Special purpose blocks:

 DSP blocks:
○ Hardware multipliers, adders and registers
 High-speed serial I/Os

Support for various interface standards
FPGA – Basic Logic Element
LUT to implement combinatorial logic
 Register for sequential circuits
 Additional logic :
 Expansion logic for functions requiring more than 4
inputs

Select
Out
A
B
C
D
LUT
D
Clock
Q
Look-Up Tables (LUT)


Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs
LUT is programmed with the truth-table
A
B
C
D
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
Truth-table
A
B
C
D
LUT
Z
LUT implementation
A
B
Z
C
D
Gate implementation
LUT Implementation
X1
X2
Example: 3-input
LUT
Configuration memory
cells
 Based on
multiplexers (pass
transistors)
 LUT entries stored
in configuration
memory cells

X3
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
F
Array-Based Programmable Wiring
M
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
Switch Matrix Operation
Before Programming
6 pass transistors per switch
matrix interconnect point
 Pass transistors act as
programmable switches
 Pass transistor gates are driven
by configuration memory cells

After Programming
Mesh-based Interconnect Network
Switch Box
Connect Box
Interconnect
Point
Comparing Technologies - Density
(gates per chip)
Highest to
lowest density:
Full Custom,
Standard Cell, Gate Array, FPGAs, CPLD, PLD
 Full Custom, Standard Cell, Gate Array are
called ASIC technologies (Application Specific
Integrated Circuit). Large Density gap between
ASIC technologies and Programmable logic
technologies (FPGAs, CPLD, PLD).
 Highest end FPGA density is now equal to lowend ASIC density (i.e., hundreds of thousands of
gates with embedded SRAMs).

Comparing Technologies - Speed
Highest to lowest performance: Full Custom,
Standard Cell, Gate Array, PLDs, CPLDs,
FPGAs.
 Again, large performance gap between ASIC
technologies & programmable technologies.
 Performance of programmable technologies is
in reverse order of their densities.

Comparing Technologies - Cost
Depends heavily on volume. If only
need a few hundred, then FPGAs can
be cheaper. If need thousands, then
ASIC technologies are cheaper.
 NRE cost (non-recurring engineering
costs) are higher for ASIC technologies
than FPGAs
 Per-unit-cost (chip cost) higher for
FPGAs

Performance and complexity
•No fabrication needed, rapidly claimed a significant part
of logic component market
•Advanced S/W support in terms of cell placement, signal
routing and synthesis is required
•Earlier prototypes is possible
•Can be reused and modified after manufacturing easily
•Routing architectures are complex.
•Shorter time to market
•Greater capability/performance at lower price point
•Lower nonrecurring engineering costs
FPGA Vendors & Device Families

Xilinx
 Virtex-II/Virtex-4: Feature-
packed high-performance
SRAM-based FPGA
 Spartan 3: low-cost feature
reduced version
 CoolRunner: CPLDs


 Anti-fuse based
FPGAs
 Flash-based FPGAs

Lattice
 Flash-based FPGAs
 CPLDs (EEPROM)
Altera
 Stratix/Stratix-II
○ High-performance SRAM-based
FPGAs
 Cyclone/Cyclone-II
 MAX3000/7000 CPLDs
 MAX-II: Flash-based FPGA
Actel

QuickLogic
 ViaLink-based FPGAs
FPGA BOARD PRICES
 Nexys2
Xilinx Spartan-3E FPGA (500K or 1200K gates)
$129
 Basys
Xilinx Spartan 3E FPGA (100K or 250K gates)
$79
 XUP Virtex-II Pro Development System
Xilinx Virtex-II Pro (30,816 Logic Cells)
$999
 NetFPGA
Xilinx Virtex-II Pro (53,136 Logic Cells)
$1599
 Digilent CMOD
Xilinx CoolRunner or CoolRunner II CPLD (64 Macrocells) $18
Websites






www.digilentinc.com
www.fpgaworld.com
www.altera.com
www.fpga4fun.com
www.xilinx.com/support/educationhome.htm
www.google.co.in