Download Field Programmable Gate Arrays - CE 141: Microprocessor Systems

Field Programmable
Gate Arrays (FPGAs)
An Enabling Technology
Introduction

Field Programmable Gate Array or
FPGA -a type of programmable device.

Programmable devices - a class of
general-purpose chips that can be
configured for a wide variety of
applications (e.g. PROM- Programmable
Read-Only Memory )

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A gate array where the logic network can be
programmed into the device after its manufacture. An
FPGA consists of an array of logic elements, either
gates or lookup table RAMs, flip-flops and
programmable interconnect wiring.
FPGAs are similar in principle to, but have vastly
wider potential application than, programmable readonly memory (PROM) chips.

Two basic PROM versions:
1) Mask-Programmable Chip - programmed
only by the manufacturer
 2) Field-Programmable Chip - programmed
by the end-user ; two types: the Erasable
Programmable Read-Only Memory
(EPROM) and the Electrically Erasable
Programmable Read-Only Memory
(EEPROM).

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Programmable Logic Device (PLD) constructed to implement logic circuits;
included an array AND gates connected to an
array of OR gates.
Programmable Array Logic (PAL) commonly used PLD consisting of a
programmable AND-plane followed by a fixed
OR-plane; come in both mask and field
versions; for small logic circuits .

Mask-Programmable Gate Array (MPGA) developed to handled larger logic circuits
 usually consists of rows of transistors that
can be interconnected to implement desired
logic circuits;
 User specified connects are available both
within the rows and between the rows which
enable implementation of basic logic gates
and the ability to interconnect the gates.
Overview of the FPGA

Four main categories of FPGAs commerically
available:

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symmetrical array
row-based
hierarchical PLD
sea-of-gates (Figure 1).
Currently used technologies:

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static RAM cells
anti-fuse
EPROM transistors,
EEPROM transistors.
Figure 1. Classes of FPGAs

Static RAM Technology --programmable
connections are made using pass=transistors,
transmission gates, or multiplexers that are controlled
by SRAM cells; it allows fast in-circuit
reconfiguration.

Anti-Fuse Technology - resides in a high-impedance
state; and can be programmed into low impedance or
"fused" state; less expensive than the RAM
technology, this device is a program once device.

EPROM / EEPROM Technology --same as used in
the EPROM memories; it can be reprogrammed
without external storage of configuration; EPROM
transistors cannot be re-programmed in-circuit.
Fuse
Anti- fuse
Characteristics of FPGA technology
The following table shows some of
the commercially available FPGAs
The SRAM based FPGA

Field-Programmable Gate Arrays (FPGAs) :

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provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
customized by loading configuration data into the internal
memory cells.
can either actively read its configuration data out of
external serial or byte-parallel PROM (master mode), or the
configuration data can be written into the FPGA (slave and
peripheral mode).
can be programmed an unlimited number of times and
supports system clock rates of up to 50 MHz.
FPGA Elements


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configurable logic blocks (CLBs) - provide
the functional elements for constructing
user's logic (Figure 2).
input/output blocks - provide the interface
between the package pins and internal signal
lines
Interconnects - programmable interconnect
resources provide routing paths to connect
the inputs and outputs of the CLBs and
IOBs onto the appropriate networks.
Customized configuration is established by
programming internal static memory cells
that determine the logic functions and
internal connections implemented in the
FPGA.
Figure 3. CLBs, Interconnects

Figure 3 depicts a FPGA with a twodimensional array of logic blocks that can be
interconnected by interconnect wires.

All internal connections are composed of metal
segments with programmable switching points
to implement the desired routing.

An abundance of different routing resources is
provided to achieve efficient automated
routing.

There are four main types of interconnect,
three are distinguished by the relative length of
their segments: single-length lines, doublelength lines and Longlines.

Eight global buffers drive fast, low-skew nets
most often used for clocks or global control
signals.
Figure 4. Configurable Logic Blocks


The principle CLB (Configurable
Logic Block) elements are shown in
Figure 4.
Each CLB contains a pair of flipflops and two independent 4-input
function generators. These function
generators have a good deal of
flexibility as most combinatorial
logic functions need less than four
inputs. Configurable Logic Blocks
implement most of the logic in an
FPGA. The flexability and symmetry
of the CLB architecture facilitates
the placement and routing of a given
application.
Programming the FPGA
The standard digital design flow for
Hardware Object implementation.
Digital Design Stage

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the digital design is created
with a schematic digital
design editor or a Hardware
Description Language
(HDL). The schematic entry
program utilizes graphic
symbols of the circuitry.
As the output of these
programs produce netlists,
one must be sure the library
sets of the targeted FPGA
are available in the tool you
have selected.
Design Implementation Stage

the netlist produced by the design
entry program is converted into the
bitstream file which configures the
FPGA. The first step Maps the design
onto the FPGA resources;. The second
step places or assigns logic blocks
created in the mapping process in
specific locations in the FPGA. The
third step Routes the interconnect
paths between the logic blocks. The
output is a Logic Cell Array File
(LCA) for the particular FPGA. This
LCA file is then converted into a
bitstream file for configuring the
FPGA.
Design Verification Step

tests the design's logic and
timing using input stimuli.
Various software packages
provide verification/simulation
tools. These tools are designed
to perform detailed
characterization of the design,
by performing both functional
and timing simulations. Incircuit verification tests the
circuit under typical operating
conditions, e.g. The Virtual
Computer tm , reconfigurable
computer.
FPGA Configuration

process in which the circuit design
(bitstream file) is downloaded into the
FPGA. The method of configuring the
FPGA determines the type of
bitstream file. FPGAs can be
configured by a PROM. The serial
PROM is the most common. The
FPGA can either actively read its
configuration data out of external
serial or byte-parallel PROM (master
mode), or the configuration data can
be written into the FPGA (slave and
peripheral mode). Where the FPGA is
used in a Reconfigurable Computing
Platform, the bitstream file is
converted into a High Level Language
(i.e. 'C" ) function