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For Immediate Release
Tip Sheet For
2016 IEEE International Electron Devices Meeting (IEDM)
The IEEE’s annual IEDM conference (www.ieee-iedm.org) is the world’s largest and most
influential forum for technologists to unveil breakthroughs in transistors and related
micro/nanoelectronics devices. This Tip Sheet is an advance look at some of the most newsworthy
sessions, topics and papers to be presented at the 62nd annual meeting, to be held at the Hilton San
Francisco Union Square Hotel from December 3 - 7, 2016. Please contact us to schedule press
interviews with IEDM spokespeople and/or with paper authors.
**** Definitions of acronyms and technical terms are on pages 10-11 ****
A) Complete 7nm FinFET Technology Platforms to be Unveiled by TSMC and the
IBM/Globalfoundries/Samsung Alliance
FinFETs are high-performance transistors used to make ultra-dense, powerful integrated circuits (ICs).
They have a multi-sided gate surrounding a fin-shaped channel so that precise control of the transistor
can be achieved even at the nanoscale. The most advanced FinFET transistors in production are at the
14nm or 16nm technology node, and are built using some of the most complex manufacturing processes
in existence.
In two late-news papers, TSMC and a technology development alliance of IBM, Globalfoundries and
Samsung will take the wraps off their forthcoming 7nm integrated FinFET technology platforms. The
move to this technology node is seen as a major driver of the continued progress of the electronics
industry, and the technology is expected to be in initial production in 2018 or thereabouts.

A 7nm CMOS Platform Technology for Mobility: TSMC researchers will present the world’s
first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring
FinFET transistors. The technology can be optimized to emphasize either high performance or
low power operation to accommodate the needs of diverse mobile applications. It features more
than three times the gate density and either a speed gain (35-40%) or power reduction (>65%)
versus the company’s commercial 16nm FinFET process. To demonstrate the technology, the
researchers built a fully functional, low-voltage 256Mb SRAM test chip with full read/write
functionality down to 0.5V, and the smallest SRAM cells ever reported (0.027µm2). Key features
IEDM 2016 Tip Sheet/ page 2
of the 7nm technology are an advanced patterning technique used with 193nm immersion
lithography, an optimized fin width and profile, a raised source/drain epitaxial process that
strains the transistor channel and reduces parasitics, a novel contact process, and a copper/low-k
interconnect scheme featuring different metal pitches and stacks. (Paper #2.7, “A 7nm Platform
Technology Featuring 4th Generation FinFET Transistors with a 0.027µm2 High-Density 6-T SRAM Cell for
Mobile SoC Applications,” S.Y. Wu et al, TSMC)

A 7nm CMOS Platform Technology Using EUV Lithography: The 7nm FinFET technology
to be disclosed by the IBM/Globalfoundries/Samsung technology development alliance is the
first integrated platform technology to use extreme ultraviolet (EUV) light to pattern transistors.
A long-anticipated development, EUV lithography may become a requirement for ultra-small
devices because the wavelength of EUV light is much shorter than that of the light currently used
(13.5nm vs. 193nm) and it simplifies patterning. Here, EUV lithography and other advanced
patterning approaches have led to the tightest contacted polysilicon pitch (44/48nm) and
metallization pitch (36nm) ever reported for FinFETs. The technology also features dual-strained
channels on a thick strain-relaxed buffer (SRB) virtual substrate to combine tensile-strained
NMOS and compressively strained SiGe PMOS for enhancement of drive current by 11% and
20%, respectively, versus a common planar HKMG process. It also features novel trench epitaxy
to minimize the resistance of the highly scaled contact regions. (Paper #2.6, “A 7nm FinFET
Technology Featuring EUV Patterning and Dual-Strained High-Mobility Channels,” R. Xie et al,
IBM/Globalfoundries/Samsung)
B) Special Focus Sessions
The 2016 IEDM will feature four Special Focus Sessions with invited papers from world experts
describing the latest research in some of the fastest-growing areas of electronics technology:
Wearable Electronics and Internet of Things (Session #6) – Wearable electronics are making inroads
in many areas for applications such as communications, fitness and health tracking, industrial
productivity and others. This Special Focus Session will survey and explore wearables topics such as
mechanical flexibility/stretchability, the ability to adhere to non-planar surfaces like the body, and the
heterogeneous integration of disparate technologies to create systems characterized by low-power
operation, energy autonomy, wireless capability and ultra-low manufacturing costs.
 “High Performance, Flexible CMOS Circuits and Sensors Toward Wearable Healthcare
Applications,” by K. Takei, Osaka Prefecture University
 “Circuits and Systems for Energy-Efficient Smart Wearables,” by A. Sharma, Texas Instruments
 “Flexible Metal-Oxide Thin-Film Transistor Circuits for RFID and Health Patches,” by P.
Heremans et al, Imec/University of Leuven/Holst Centre (Belgium)/National Centre for Flexible
Electronics (India)
 “Challenges and Opportunities in Flexible Electronics,” by R. D. Bringans and J. Veres, Xerox
PARC
 “Advanced Integrated Sensor and Layer Transfer Technologies for Wearable Bioelectronics,” by
D. Shahrjerdi et al, New York University
 “Wearable Sweat Biosensors,” by A. Javey et al, University of California, Berkeley
 “Flexible Metamaterials, Comprising Multiferroic Films,” by Y. P. Lee et al, Hanyang
University
IEDM 2016 Tip Sheet/ page 3
Quantum Computing (Session #13) – Quantum computing is a nascent field that exploits the laws of
quantum physics to manipulate data by taking advantage of subatomic interactions. Quantum computers
offer the potential of computational power exponentially faster than today's systems for select
algorithms and applications. A qubit (or qbit) is a unit of quantum information. This Special Focus
Session will feature papers describing several technologies to fabricate qubits, including transmon
qubits, spin qubits in silicon, and fully-depleted silicon-on-insulator (FDSOI) qubit technology with
silicon nanowire field-effect transistors. There also will be discussions of quantum technologies based
on luminescent crystalline defects in diamond, and the prospects of scalability in view of the potential
fabrication of large-scale systems with millions of qubits.
 “Quantum Computing Within the Framework of Advanced Semiconductor Manufacturing,” by J.
S. Clarke et al, Intel/TU Delft
 “Spin-Based Quantum Computing in Silicon CMOS-Compatible Platforms,” by A.S. Dzurak,
University of New South Wales
 “Coupled Quantum Dots on SOI as Highly Integrated Si Qubits,” S.Oda, Tokyo Institute of
Technology

“SOI Technology for Quantum Information Processing,” by S. De Franceschi et al,
CEA/University Grenoble Alpes
 “Cryo-CMOS for Quantum Computing,” by E. Charbon et al, Delft University of
Technology/EPFL/Institut Superieur d’Electronique de Paris/Tsinghua University/Univ.
California, Berkeley
 “Diamond–A Quantum Engineer’s Best Friend,” by Marko Lončar, Harvard University
 “Large-Scale Quantum Technology Based on Luminescent Centers in Crystals,” by M. Trupke et
al, TU Wien/University of Vienna/Nippon Telegraph and Telephone/National Institute of
Informatics (Japan)
System-Level Impact of Power Devices (Session #20) – The use of GaN and SiC has made it possible
to expand the use of electronics at very high voltages, temperatures and power levels compared to existing
silicon-based power devices, revolutionizing the way power is delivered and managed. This Special Focus
Session will describe recent advances in wide-bandgap power devices, show how they are transforming
power delivery systems, benchmark material characteristics and reliability, and consider future directions.
 “Wide Bandgap (WBG) Power Devices and Their Impacts On Power Delivery Systems,” by Alex
Huang, North Carolina State University
 “Si, SiC and GaN Power Devices: An Unbiased View on Key Performance Indicators,” by G. Deboy
et al, Infineon/ETH-Zurich
 “System-Level Impact of GaN Power Devices in Server Architectures,” by A. Lidow et al, Efficient
Power Conversion Corp.
 “GaN-based Semiconductor Devices for Future Power Switching Systems,” by H. Ishida et at,
Panasonic
 “Application Reliability Validation of GaN Power Devices,” by S. Bahl et al, Texas Instruments
 “Horizon Beyond Ideal Power Devices,” by H. Ohashi, NPERC-J (Japan’s New-Generation Power
Electronics & System Research Consortium)
Ultra-High-Speed Electronics (Session #29) – Transistors operating at terahertz (THz) frequencies will
enable revolutionary progress in many areas such as higher-resolution medical imaging, radar to see
through fog/rain/dust, non-destructive materials testing, high-speed data communications and many
IEDM 2016 Tip Sheet/ page 4
others. This Special Focus Session features papers on devices and circuits for THz applications. Topics
include the latest progress in THz oscillators using GaInAs/AlAs resonant-tunneling-diodes (RTDs); a
review of developments in InP/GaAsSb DHBTs; meta-surfaces for THz modulation; InP HEMT
technology for THz applications; electromagnetic-wave studies to maximize silicon device efficiency;
recent advances in CMOS technology in THz systems; a discussion of overshoot and ballistic transport
physics; and terahertz electronic systems based on 130 nm InP HBT integrated circuit technology.
 “InP HEMT Integrated Circuits Operating Above 1,000 GHz,” by W.R. Deal et al, Northrop
Grumman
 “A 130 nm InP HBT Integrated Circuit Technology for THz Electronics,” by M. Urteaga et al,
Teledyne Scientific Co./SungKyunKwan University
 “Resonant-Tunneling-Diode Terahertz Oscillators and Applications,” by M. Asada and S.
Suzuki, Tokyo Institute of Technology
 “Physics of Ultrahigh Speed Electronic Devices,” by M. Shur, Rensselaer Polytechnic Institute
 “InP/GaAsSb DHBTs for THz Applications and Improved Extraction of their Cutoff
Frequencies,” by C.R. Bolognesi et al, ETH-Zurich
 “On-Chip Terahertz Electronics: From Device-Electromagnetic Integration to Energy-Efficient,
Large-Scale Microsystems,” by R. Han et al, MIT/Office of Naval Research/Cornell
University/University of Michigan/STMicroelectronics/University of Texas at Dallas/Naval
Research Lab
 “Active Terahertz Metasurface Devices,” by H.T. Chen, Los Alamos National Laboratory
 “Devices and Circuits in CMOS for THz Applications,” by K. K. O et al, University of Texas at
Dallas/NXP Semiconductors/MIT/SeoulTech/Texas Instruments/MediaTek/IDT/Wright State
University /UT Southwestern Medical Center/Ohio State University/ UConn Health
C) Advances in Core CMOS Technology
Air Spacers to Reduce Capacitance in 10nm FinFETs: Parasitic capacitance slows down the
switching of transistors with closely packed features, such as the tightly packed gate and contacts in a
FinFET. Low-k dielectrics, or insulators, are used to counter it, but as devices scale smaller and
dielectrics get thinner the capacitance continues to increase. Air is considered to be the perfect insulator
but nanoscale air spacers, or voids, are difficult to fabricate. They must be very narrow, quite deep, and
yet precisely uniform. While FinFET air spacers have been demonstrated, researchers from IBM and
Globalfoundries will report the first air spacers at the 10nm FinFET node. These reduced capacitance at
the transistor level by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The
researchers say a partial air spacer scheme represents a good way to introduce air spacers at this scale
because it minimizes damage to the FinFET, as does the high-selectivity etching process used to
fabricate them. (Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al,
IBM/Globalfoundries)
10nm FinFET Reliability: Samsung researchers will present the first comprehensive reliability analysis
of 10nm FinFET technology. They will review all major aspects of multiple-threshold-voltage FinFET
technology including hot carrier injection, intrinsic ballistic transport, and gate and middle-of-the line
time-dependent dielectric breakdown (TDDB). They will describe process optimizations that overcome
roadblocks to FinFET device technology at this node, such as self-heating effects, and will describe
robust 10nm devices they built that demonstrated high reliability. (Paper #15.1, “Reliability Characteristics of
10nm FinFET Technology with Multi-Vt Gate Stack for Low Power and High Performance,” M. Jin et al, Samsung)
IEDM 2016 Tip Sheet/ page 5
D) Memory Technology
Brain-Like Computing with 3D Vertical RRAM: Brain-inspired computing aims at energy-efficient
emulation of human cognition. An aspect of cognition is “one-shot learning,” or the ability to learn from
one or a few examples at a rapid pace. By contrast, modern deep neural networks require large datasets,
brute-force iterative computations and they are energy-intensive. Stanford researchers and partners will
describe what they are calling a hyperdimensional (HD) computing environment aimed at emulating
one-shot learning by manipulating not only binary values such as 0 or 1, but vectors, or collections of
values. It is based on the use of non-volatile resistive RAM devices, or RRAM, which unlike other
computer memories can hold a range of resistive states that can correspond to the “shades of grey” in
our thinking. Here, the RRAM is a 3D vertically oriented device whose physical structure corresponds
to the team’s HD computing algorithm. The 3D VRRAM enabled the team’s HD computing framework
to recognize words in 21 different languages from sample texts. (Paper #16.1, “Hyperdimensional Computing
with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language
Recognition,” H. Li et al, Stanford/University of California, Berkeley/National Nano Device Laboratories)
First 4 GB STT-MRAM: Spin-transfer-torque magnetic random access memory (STT-MRAM) is a
promising technology for non-volatile and high-speed applications, but it is difficult to pattern and its
operating performance needs improvement. These issues arise largely from a mismatch between the
relatively high current needed for magnetic tunnel junction (MTJ) switching, and the relatively low
current available in small bit cells. Researchers from SK Hynix and Toshiba, though, will describe the
first 4 GB STT-MRAM circuit, built from memory cells having a cell area of 9F2, very close to the size
of a DRAM cell. To fabricate it successfully, the researchers used contact and channel engineering to
suppress parasitic resistance; used an optimized perpendicular MTJ with a high tunneling resistance
ratio and low switching current requirement; and also used various techniques to manage write errors
stemming from process-related defects. (Paper #27.1, “4Gbit Density STT-MRAM Using Perpendicular MTJ
Realized with Compact Cell Structure,” S.W. Chung et al, SK Hynix/Toshiba)
FeRAM Embedded Memory for IoT: Battery-operated circuits for IoT applications require lowpower, low-cost and non-volatile embedded memories. Flash memory is the dominant embedded
technology, but flash is complex, costly and doesn’t scale well. Researchers at Globalfoundries and
partners will describe an alternative: a low-power embedded non-volatile memory based on ferroelectric
FETs that was fully integrated with Globalfoundries’ commercially available low-power 28nm gate-first
HKMG CMOS platform. The hafnium-based FeFETs are relatively simple devices with one transistor,
facilitating integration into the 28nm process and at low manufacturing costs. The FeFET gate stack can
be optimized independently from the 28nm technology, and an arbitrarily mixed placement of CMOS
and FeFET devices in the same circuit is possible. The researchers say the technology is likely
transferable to gate-last and FinFET technologies as well. High-temperature data retention (≤250ºC) and
endurance up to 105 cycles were demonstrated. (Paper #11.5, “A 28nm HKMG Super-Low-Power Embedded
NVM Technology Based on Ferroelectric FETs,” M. Trentzsch et al, Globalfoundries/NaMLab gGmbH/Ferroelectric
Memory GmbH/Fraunhofer IPMS/RacyICs GmbH/TU Dresden)
Modeling CBRAM Operation: CBRAM (conductive-bridge RAM) is a promising non-volatile
memory technology offering low-power operation, fast switching, high endurance and scalability. The
basic principle is that amorphous insulating materials containing relatively large amounts of metal can
sometimes behave as solid electrolytes, because the metal ions they contain can form a conductive
IEDM 2016 Tip Sheet/ page 6
pathway when voltage is applied. The process is reversible, enabling the reading and writing of memory
data as the material switches back and forth between insulator and conductor. Accurate computer
models and simulations of CBRAM operation are essential for a better understanding of this process and
as design tools. However, it’s challenging to characterize the growth and expansion of the filament
during the set/reset process, and to correlate it with material properties. Researchers from Peking
University and partners, though, developed and verified a compact computer modeling framework based
on the essential physics which does exactly that. The outcomes of this method are then used to develop a
SPICE model for the co-design of individual devices and circuits. (Paper #7.6, “A Physics-Based Compact
Model for Material- and Operation-Oriented Switching Behaviors of CBRAM,” Y.D. Zhao et al, Peking University/
Innovation Center for MicroNanoelectronics and Integrated System (China)/Hong Kong Polytechnic University)
E) Novel Devices
Smart Contact Lens: The iris is a vital part of the eye, modulating the amount of light reaching the
retina. An estimated 200,000 individuals worldwide suffer from iris deficiencies that bring great
discomfort and extreme photosensitivity, such as aniridia and leiomyoma. Imec and KU Leuven
researchers will discuss an artificial iris system built on a contact lens that may ameliorate some of these
difficulties. It comprises an organic thin-film photovoltaic mini-module as a power supply/integrated
illumination sensor; a flexible thin-film a-IGZO circuit as a driver chip; and a liquid crystal display
which acts as the iris. The system demonstrated very low power consumption for the driver chips
(≥25μW), and while actual products are in the future, initial performance was promising. (Paper #32.1,
“An Active Artificial Iris Controlled by a 25-μW Flexible Thin-Film Driver,” F. DeRoose et al, Imec/KU Leuven)
Exquisitely Sensitive Gas Sensor: Detecting the presence of ammonia (NH3) and nitrogen dioxide
(NO2) in the environment is important because even in low concentrations they are harmful. Both can be
detected with dedicated instruments, but in limited areas and at high cost. Fujitsu researchers will
describe the use of graphene to build a compact, simple, highly sensitive and selective NO2 and NH3 gas
sensor. They replaced the metal gate electrode of a standard MOSFET transistor with graphene, the idea
being that when NH3 and NO2 molecules are adsorbed on the graphene its electrical properties change.
As a result, when exposed to NO2 the drain current of the MOSFET decreases, and when exposed to
NH3 it increases. At room temperature the sensor can detect a NO2 concentration of 7 ppb (more than an
order of magnitude greater than conventional sensors) and an NH3 concentration 420 ppb. The
graphene-gate sensor exhibits almost no response to SO2, H2S, and acetaldehyde, demonstrating high
selectivity. The researchers say doping the graphene gate can modulate sensor sensitivity, and that the
device’s threshold voltage can be changed by up to ~620 mV without degrading transistor performance.
(Paper #18.2, “Graphene-Gate Transistors for Gas Sensing and Threshold Control,” N. Harad et al, Fujitsu)
Large-Format CMOS Imager with Global Shutter for High-Performance Cameras: Canon
researchers will discuss high-resolution, large-format CMOS imaging technology for use in highperformance cameras large enough to take photographs and videos at ultra-high-definition resolution.
Most CMOS imagers use a rolling shutter, which captures an image at slightly different times at
different areas of the imager. This can lead to image artifacts, especially for moving targets, because the
image is taken while the subject is in different positions in the field. Imagers with global shutters capture
light from each pixel in the imager at the same time, eliminating these artifacts. However, a global
shutter usually leads to less dynamic range and higher noise and dark current, and thus to inferior
photographs. The Canon researchers developed a new architecture that enables the readouts of multiple
pixels to be accumulated and stored in memory, and then processed all at once. This technique enabled
IEDM 2016 Tip Sheet/ page 7
the implementation of a global shutter while also delivering excellent noise and dark current
performance and high dynamic range (92dB at a standard 30fps frame rate). (Paper #8.6, “A 1.8e- Temporal
Noise Over 90dB Dynamic Range 4k2k Super 35mm Format Seamless Global Shutter CMOS Image Sensor with
Multiple-Accumulation Shutter Technology,” K. Kawabata et al, Canon, Inc.)
Big Step Toward Silicon Photonics: In recent years silicon photonics has emerged as a solution for the
cost-effective volume manufacturing of optical transceivers for data centers. Although several silicon
photonics platforms have been demonstrated using standard silicon, and some products addressing the
100G-PSM4 standard for 100Gbps optical interconnects have been released, they all lack a
monolithically integrated light source. A common approach to try to integrate a light source is to use
selective bonding to mate a hybrid III-V laser with a silicon substrate. However, none yet demonstrated
can be manufactured in bulk with cost-effective standard CMOS BEOL processing, and that is
counterproductive. Researchers from STMicroelectronics and partners will describe the first integration
of a III-V/Si hybrid laser on the backside of an SOI wafer. The InGaAsP device preserves compatibility
with silicon waveguides and with front-side CMOS interconnects, while making use of passive and
active photonic device design. (Paper #22.2, “First Demonstration of a Back-Side Integrated Heterogeneous Hybrid
III-V/Si DBR Laser for Si-Photonics Applications,” J. Durel et al, STMicroelectronics/CEA-LETI/University Grenoble
Alpes/Vistec Electron Beam GmbH)
End-Bonded Contacts for N- and P-Type Carbon Nanotubes: Carbon nanotubes (CNTs) are a
possible replacement channel material for silicon in sub-5nm logic technology. However, CNT electrical
contacts are made by side-bonding the contact metal on top of the CNT. This is unfavorable for scaling
because the electrical resistance of the contacts increases as CNTs scale smaller. IBM researchers got
around this by directly bonding metal atoms to the ends of the nanotubes, yielding an ultimately scalable
contact. They used a low-temperature annealing process to do this so as to avoid damaging the delicate
CNTs, and employed a doping strategy that resulted in n- and p-type end-bonded CNTs, which they
tested for performance in a variety of CMOS inverter circuits. (Paper #5.1, “Carbon Nanotube Complementary
Logic with Low-Temperature Processed End-Bonded Metal Contacts,” J. Tang et al, IBM)
TFET with Record On-Current: Tunneling FETs (TFETs), which operate according to the principles
of quantum mechanics, offer a unique mechanism for low-voltage switching and may lead to dense,
powerful circuits that operate at extremely low power levels. However, tunneling behavior typically
greatly compromises the amount of current that is available, limiting their usefulness. Lund University
researchers will discuss a vertical nanowire-based TFET with a novel heterostructure design
(InAs/GaAsSb/GaSb) that makes possible aggressive dimensional scaling along with improved
electrostatic control. The result is a device with a record high on-current (10.6μA/μm) and extremely
steep on/off behavior, as low as 44 mV/dec at 0.05V, which is less than the 60 mV/decade theoretical
limit for MOSFETs. (Paper #19.1, “Vertical InAs/GaAsSb/GaSb Tunneling Field-Effect Transistor on Si with S=48
mV/decade and Ion=10 µA/µm for Ioff = 1 nA/µm at VDS = 0.3 V,” E. Memisevic et al, Lund University)
V-Shaped Channel for Record GaN Threshold Voltage: Power transistors made from gallium nitride
(GaN) alloys instead of silicon are promising alternatives for high-power applications. Planar
AlGaN/GaN transistors on silicon substrates are commercially available with blocking voltages of ≤600
V, but Panasonic researchers will describe vertical GaN devices on a bulk GaN substrate (pGaN/AlGaN/GaN ) that demonstrated a record-setting 1.7 kV threshold voltage plus a remarkably low
on-state resistance of 1.0 mΩcm2. One day such efficient devices may eliminate the need for liquid
cooling in high-power electronic systems, thereby reducing their size, weight, complexity and cost. To
IEDM 2016 Tip Sheet/ page 8
achieve this performance, the researchers created a “semipolar” gate structure that propels charge
carriers with great efficiency. They plasma-etched V-shaped grooves into an n-GaN drift layer atop the
substrate. Because these grooves were cut at a slant, they exposed a second facet of the crystalline GaN
material and thereby created the possibility of semipolar operation. The researchers then expitaxially
grew p-GaN/AlGaN/GaN layers in these grooves and built a “slanted” channel with the gate on top.
(Paper #10.1, “1.7 kV/1.0 mΩcm2 Normally-Off Vertical GaN Transistor on GaN Substrate with Regrown pGaN/AlGaN/GaN Semipolar Gate Structure,” D. Shibata et al, Panasonic.)
Conductive Filament Forms/Dissolves to Enable Sharp On/Off Switching: A grand quest in
electronics is to replace today’s relatively power-hungry transistors with devices that can be switched on
and off at much lower voltages. However, a lower voltage means that a device’s “on” and “off” states
are closer to one another electrically. Therefore, the transition between the two must be sharp and crisp,
or in electrical engineering terms there must be a very steep subthreshold slope (SS). The theoretical SS
limit for MOSFETs is 60 mV/dec, but novel steep-slope devices with different operating mechanisms
have been investigated to get around it, such as tunnel FETs, impact-ionization FETs and phasetransition FETs. Each shows promise but has significant drawbacks. At the IEDM, researchers from
Korea’s Pohang University will describe a novel AgTe/TiO2-based threshold switching (TS) device that
can be integrated with conventional silicon MOSFETs. The TS device is connected in series to the drain
of a MOSFET, and when the MOSFET is switched on an atomic-scale conductive silver filament forms
in the TS device, facilitating the flow of current. When the MOSFET is switched off, the filament
dissolves and the current flow stops. The process is reversible. In monolithically integrated devices, the
technology demonstrated a very low SS of <5mV/dec, a high on/off current ratio of >108, and a low
drain voltage of 0.5V. (Paper #25.3, “Monolithic Integration of AgTe/TiO2-Based Threshold Switching Device with
TiN Liner for Steep Slope Field-Effect Transistors,” J. Song et al, Pohang University of Science and Technology)
F) Noteworthy Papers on Diverse Topics
Devices for Studying the Brain: Optogenetics is a technology used to understand the working
principles of the brain. It involves studying neurons by stimulating their constituent proteins with light.
The neural cells aren’t damaged, as they can be when electrically stimulated. Achieving simultaneous
stimulation and response measurement in a brain is challenging because a bio-compatible, integrated
platform has been lacking. University of Michigan researchers and partners will discuss how they are
addressing this roadblock with micro-machined optoelectrodes comprising neuron-sized micro-LEDs
and electrodes integrated on thin silicon probes for high spatial and temporal accuracy. Upon insertion,
the optoelectrodes have captured the neuronal activities in targeted areas of the brain of a freely
behaving mouse. (Paper #26.5, “GaN-on-Si μLED Optoelectrodes for High-Spatiotemporal-Accuracy Optogenetics in
Freely Behaving Animals, “ K. Kim et al, University of Michigan/New York University/Tel Aviv University)
Fastest Silicon-Based HBT: Higher-speed networks and the burgeoning number of wireless computing
and communications applications are driving strong demand for speedy transistors that can send/receive
signals at millimeter-wave (mmWave) and sub-mmWave frequencies, or ≥ 30 GHz. A team from
Germany’s IHP will describe a heterojunction bipolar transistor (HBT) with the best performance a
silicon-based HBT has ever demonstrated. HBTs are usually made from III-V materials with higher
electron mobilities than silicon but they are hard to integrate with widely used silicon technologies.
Also, silicon devices can operate at lower voltages, making them more attractive for battery-powered
applications. The IHP devices featured an fT/fmax of 505 GHz/720 GHz, respectively, at 1.6V, and a gate
delay of just 1.34 ps in a ring oscillator test circuit. The researchers attribute this record performance to
IEDM 2016 Tip Sheet/ page 9
three factors: optimized vertical profiles of the emitter-base-collector regions; the use of “flash”
annealing and low-temperature backend processing to lower base and emitter resistance; and lateral
device scaling. (Paper #3.1, “SiGe HBT with fT/fmax of 505 GHz/720 GHz,” B. Heinemann et al, IHP)
Mapping Hot Spots at 10nm and Below: Localized self-heating effects, or hot spots, are becoming an
increasing reliability concern with deeply scaled devices as high power densities begin to exceed the
ability of the tiny devices to dissipate heat. It’s imperative to know where these hot spots are located so
they can be eliminated or managed, but until now most hot spot evaluations have been based on
computer simulations because measurement techniques couldn’t distinguish fine-scale temperature
variations. An IBM team will describe how they used a new Scanning Thermal Microscopy technique
(an outgrowth of AFM, or atomic force microscopy) to directly measure localized temperatures. Using a
nanoscale probe tip as a thermal sensor, they were able to discern temperatures at ≤10 nm resolutions.
To demonstrate its versatility, they used the technique to map the temperature in different regions of a
variety of nanoscale devices, including InAs nanowires and vanadium dioxide phase-change resistors.
(Paper #15.8, “Local Thermometry of Self-Heated Nanoscale Devices,” F. Menges et al, IBM)
Making & Modeling Dielectrics & Gates on 2D MoS2 Substrate: Two-dimensional, or 2D, materials
such as graphene and MoS2 are one or two atoms thick and have remarkable physical and electrical
properties that may one day revolutionize many electronics applications. 2D MOSFETs have been
proposed as one way to extend semiconductor scaling to extremely small sizes, but there are two major
obstacles. One is that gate dielectrics are difficult to grow on the surface of a 2D material, because doing
so alters the properties of the 2D material. The other is that expensive lithography is required to form the
ultra-short channel lengths required. UCSB researchers came up with a way to address both issues at the
same time. On an SiO2 carrier wafer substrate, they formed a thin (6nm) conformal Al2O3 dielectric
around Co2Si nanowire conductors, and then gently pressed the carrier wafer against a MoS2 substrate
to transfer them. Each nanowire was used as an ultra-short channel gate (<20nm) for a MoS2 MOSFET,
with the Al2O3 material as its gate dielectric. The researchers built a number of MOSFETs with various
channel materials and varying numbers of layers and nanowire/gate sizes, and then used quantum
transport simulations to identify optimal materials and device designs. (Paper #14.7, “Prospects of Ultra-Thin
Nanowire-Gated 2D-FETs for Next-Generation CMOS Technology,” W. Cao et al, University of California, Santa
Barbara)
Designing High-Current TFETs: Tunneling field-effect transistors (TFETs) operate according to
principles of quantum mechanics. They are promising for ultra-low-power applications because they
operate at low voltages, but it’s difficult to build them so that they carry useful amounts of current. At
the IEDM, researchers from Purdue University and partners will present a design methodology for
heterostructure TFETs that have a high on-current of 265 A/m at 0.18V, and 1.95 A/m at 0.12V. These
values, from calculations based on the essential physics of the device, derive from extensive modeling
and simulation of theoretical device structures. (Paper #30.2, “A Tunnel FET Design for High-Current, 120 mV
Operation,” P. Long et al, Purdue University/Imec/University of California, Santa Barbara/University of Virginia)
###
IEDM 2016 Tip Sheet/ page 10
Here are definitions of some important technical terms you may find useful:
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Back-End/BEOL and Front-End/FEOL -- In integrated circuit manufacturing, transistors and other active devices
are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built
afterward, at the “back end” of the manufacturing line (BEOL).
Carbon nanotube (CNT) – A cylinder made of carbon atoms, measured in nanometers (nm).
CMOS/MOS/MOSFET/FET-- Most transistors today are FETs, or field-effect transistors. Most FETs are built
with CMOS manufacturing technology (complementary metal oxide semiconductor). Generically they are called
MOSFETs, or sometimes MOS transistors.
Compound/III-V Semiconductors -- Most semiconductors are silicon-based, but researchers continue to
investigate other semiconducting materials with higher electron mobilities because they can be used to make faster
devices. The tradeoff is that the materials are harder to work with than silicon. Compound semiconductors are made
of two or more elements (e.g. GaAs, InP, GaN, etc.) that are generally found in groups III and V of the periodic
table of the elements.
DHBT – Double heterojunction bipolar transistor
DIBL -- Drain-induced barrier lowering is a parasitic short-channel effect in MOSFETs that influences threshold
voltage.
Electromigration -- A serious reliability issue. At tiny dimensions some materials tend to physically move when
current flows through them, leading to voids, gaps or outright breaks in what should be a uniform material.
Electron mobility -- A measure of the velocity of electrons in a semiconductor.
FinFET -- A transistor whose shape resembles a fin, usually with multiple gates surrounding it for better on/off
control.
fT -- a measure of transistor speed known as unity current gain cutoff frequency, above which the device loses its
amplifying capability.
fmax -- a measure of transistor speed denoting its maximum oscillation frequency
Front-End/FEOL and Back-End/BEOL -- In integrated circuit manufacturing, transistors and other active devices
are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built
afterward, at the “back end” of the manufacturing line (BEOL).
HEMT -- A HEMT, or high-electron-mobility transistor, is a field-effect transistor with a channel built from a
sandwich of two materials with different energy band gaps, instead of a channel built from doped silicon as is the
case with most MOSFETs. HEMTs operate at higher frequencies than ordinary transistors, up to millimeter-wave
frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage
converters, and radar equipment.
High-k Dielectrics/Metal Gates (HKMG) -- A dielectric is an insulator. “k” is a measure of how well a material
will work as a dielectric. A higher numerical value for “k” means better insulating performance without increased
physical thickness of the insulating layer. For the gate of a transistor, which turns it on and off, a high-k dielectric is
critical because if current leaks through the gate, the transistor won't work properly. In the past gates were usually
made of polysilicon with an oxide dielectric, but these are not scalable to meet the needs of the latest technology
generations. Other good dielectrics exist but they aren't compatible with polysilicon gates. The latest generations of
MOSFETs use metal gates with high-k dielectrics to enable continued scaling and higher device performance.
III-V -- see Compound/III-V Semiconductors
Integrated Circuit -- A tiny electrical circuit built on a semiconducting substrate.
Internet of Things (IoT) -- The idea of giving everyday objects network connectivity, allowing them to send and
receive data.
Lithography/Photolithography/EUV Lithography -- Transistors are built on chips using photolithography, a
process by which light is shone through a patterned photomask onto a chip’s surface. The light transfers a copy of
the image on the mask to a light-sensitive layer on the chip’s surface, in much the same way the image on a
photographic negative is transferred onto photo paper. The chip’s surface is then engraved with chemical etches and
other treatments in order to build the patterned devices and circuits. Right now various tricks and tweaks enable us
to build transistors smaller than the wavelength of light used to pattern them. But for future technology generations
of ultra-small transistors, the shorter wavelengths of extreme ultraviolet light (EUV) may be needed. Researchers are
working to develop cost-effective, high-throughput EUV systems.
Low-k Dielectrics/Interconnect -- Interconnect refers to the copper lines that connect devices on a chip. The tiny
widths and close proximity of adjacent lines introduce resistance and capacitance delays that can hinder chip
IEDM 2016 Tip Sheet/ page 11
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performance. Here a low-k dielectric is needed, to insulate the copper lines while minimizing capacitance increase,
but these materials are fragile and pose many challenges.
MEMS/NEMS -- A micro-electromechanical system/nano-electromechanical system, containing micrometer-scale
moving parts (the former) or nanometer-scale moving parts (the latter).
Multi-chip Modules -- An electronic package containing multiple ICs, other semiconductors and/or other chip
modules.
Moore’s Law -- An observation made in 1965 by Intel’s Gordon Moore, who said that the number of transistors
which can be placed on an integrated circuit doubles about every two years. Subsequent events have proved him
correct but it’s getting harder to do.
N-FET/P-FET or n-channel/p-channel -- All MOSFETs come in two varieties that work together in a
complementary fashion, N and P.
Phase-Change Memory/PCM -- Phase-change materials have crystalline and non-crystalline states that are used to
represent the digits “0” or “1,” the basis of computer memories. Electrical current is used to toggle between the two
states – heat from the current melts the material to change its state.
Scaling/Density/Integration -- Scaling is making transistors and other circuit elements smaller so that more will fit
on a chip. A denser chip has more transistors on it than one which is less dense. Integration is combining circuit
elements on a chip to add more functions at less cost.
Self-Assembly/“Bottom Up” -- A manufacturing method used at the nanometer scale, making use of the fact many
biological systems automatically self-assemble into various molecular or other structures. Self-assembly techniques
imitate these strategies by encoding a desired structure into the shape and properties of the molecules that are used.
This compares to traditional lithography, where the structure is carved out of a block of matter. Self-assembly is thus
referred to as a 'bottom-up' manufacturing technique, as compared to lithography, a “top-down” technique.
Semiconductor -- A material that can be made to conduct or to block the passage of electrical signals, giving the
ability to store and process data.
SOI -- A silicon-on-insulator substrate, used to reduce parasitic capacitance and thereby improve performance
Strained silicon & SiGe stressors -- Silicon is said to be “strained” when its atoms are pulled farther apart or closer
together than normal. Doing so alters the atomic forces that govern the flow of electrons through the silicon,
enabling transistors built with it to operate faster and /or at lower power. The external stressors which impart strain
are materials with slightly different atomic structures than silicon. For example, a common way to strain silicon is to
build a silicon layer on top of a silicon-germanium (SiGe) layer. The silicon atoms will align with the atoms of the
SiGe layer, which lie farther apart.
SRAM -- A type of computer memory (static random access memory) that uses six transistors to store each bit of
information. It can be written to and read from very quickly.
Subthreshold slope (SS) -- A measure of a MOSFET transistor’s current/voltage characteristics. The steeper it is,
the more abruptly the device can turn on and off.
Technology Generations/Nodes -- Production of 22-nm devices by leading companies is established and the
transition to 16nm/14nm is well underway. Beyond that, 10nm technology is expected to enter production by 2017.
Transconductance -- A measure of transistor performance. Transistors with higher levels of transconductance can
amplify signals more efficiently than low-transconductance devices can. Technically, in a transistor it is the ratio of
change in output current to change in input voltage.
Transistor -- A tiny electrical switch that makes electronic systems possible. It has no moving parts and is made
from semiconductors, usually silicon. Transistors can be ganged together by the millions on chips and programmed
to sense inputs, to process information and to deliver outputs.
TSV – Through-silicon via, a vertical electrical connection (i.e. a “via”) that passes through a silicon wafer or die.
TSVs are used to create 3D integrated circuits and packages of stacked microchips.