Download Title of the paper: Times New Roman, Bold

Heterogeneous Micro/Nano-Electronics :
Towards the Maturity Learning into the Zero Variability Era.
Simon Deleonibus
CEA-LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France
email address: [email protected]
Introduction
Nanoelectronics will have to face major challenges in the next decades in order to proceed with
increasing progress and drastically reduced to zero variability at the sub 10 nm nodes level. New
progress laws combined to the scaling down of CMOS based technology will emerge to enable new
paths to Functional Diversification. New materials and disruptive architectures, mixing logic and
memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End
levels, will come into play to make it possible.
1.
Nanoelectronics scaling and the use of the 3rd dimension to continue Moore’s law.
The microelectronics industry is facing historical challenges to down scale CMOS devices through
the demand for low voltage, low power, high performance and increased functionalities. The
implementation of new materials and devices architectures is necessary. HiK gate dielectric and
metal gate have been introduced to reduce power consumption and manage low supply voltage.
Fully Depleted CMOS devices made on Thin films are the key to flexible integration, leading to
Low Voltage and Low Power consumption circuits featuring low variability thanks to undoped
channels [1-10]. The integration of intentionally undoped thin films channels as well as properly
engineered source and drain architectures are important options to optimize transport properties as
well as controlled minimal leakage and variability [6-10]. Prospectively sub 60mV/dec swing
architectures can be easily implemented thanks to Tunneling Field Effect Transistors(TFET)[11].
Multigates and multichannels devices [12,13], based on wrapped around nanowires[12-15] have
been demonstrated at the same time to optimize MOSFETs electrostatics as well as increase their
drivability. Nanowires possibly combined with Tunneling structures [11] will be the ultimate
architectures to reduce power MOSFET consumption at the sub Lg=5nm level.
New memory concepts are necessary to save retention and endurance capabilities[16-20] while
improving performance and power consumption as embedded High Density Flash memories are
scaled to smaller dimensions. Moreover, the request for controlled short channel effect make gate
all around structures attractive[16,17,19]. The scaling of Flash Memories relies as well on the
memory characteristics (read, write, erase, endurance, retention,…) of the storage node and
access non-linear device. Phase change or Resistive memories [14,18] introduce new possibilities
to reduce power consumption and pave the way to new applications such as the Mixing of Logic to
Flash memories [21,22] that will enable novel low power, programmable, reconfigurable
architectures advantageously integrated in 3D schemes.
By introducing new materials(HiK, Ge, III-V, Carbon based materials, molecules,…), CMOS
scaling could be continued by possibly exploiting the 3rd dimension, because low temperature
processing will be a necessity for the integration of the new materials. At the sub 5 nm level, near
zero variability processes will have to be introduced due to the near-to- molecular size of the
devices. That is why the control of single atom doping and few electrons will be necessary at room
temperature[23,24]. Several techniques are under investigation to control doping at the single
atomic level [25,26,27].
2. Interfacing the Multiphysics World by functional diversification and 3D at Wafer Level
The connection of Nanoelectronics to the outside Multiphysics world requests the use of devices
with diversified functionalities such as selective sensing, actuation, imaging and displaying, power
generation through available electrical, mechanical, ultra narrow band RF and High Frequency,
photonic signals to address societal needs (health, energy, security, communications, transport). The
Heterogeneous integration of new materials and devices within or with CMOS[14,28,29,30] will
require new 3Dintegration schemes[28,29]. New functions such as sensing and actuation allowing
to interface the outside world (M/NEMS, filters, Imagers,…) could also be co integrated with or
within CMOS[14,31,32], allowing Si based CMOS to be scaled beyond the ITRS as the
System-on-Chip/Wafer Platform[33,34]. Through Silicon Vias, Insulator-Insulator and Cu-Cu
bonding are major technology options for this purpose[33,35]. These new applications will also
require new Packaging schemes and thus lead to the increase of effective packing density on a
system. Novel functionalities and improved systems figures of merit[28-32] will result in new
applications in the fields of future societal concerns such as safety, health and environment.
3. Conclusions
Functional diversification added to Nanoelectronics scaling will make possible new future systems
to address increasing societal needs. Drastically reduced to Zero Variability and 3D integration will
make it possible by addressing, at the wafer level, device to packaging technologies capable of
reducing cost and improving system performance.
4. Acknowledgements
These
programs
are
supported
by
various
funding:
Nano2012
Program
(CEA-LETI/STMicroelectronics/ IBM Alliance), Carnot Institute, various French National
Research Agency and European Commission Programs (FP7, ERC, …).
5. References
[1] “Electronic Devices Architectures for the NANO-CMOS Era”, PanStanford, S.Deleonibus, Editor, Singapore, (2008).
[2] C.Fenouillet et al, IEDM, p.267,(2007)
[3] O.Weber et al.,IEDM., p.176,(2008)
[4] F.Andrieu et al, VLSI Tech Symp, p. 57, (2010)
[5] V.Barral et al, IEDM., p61, (2007)
[6] J. Mazurier et al. , IEDM, p. 575, (2011).
[7] C.Le Royer et al, , IEDM, p. 394, (2011).
[8] L.Grenouillet et al, IEDM, p64(2012)
[9 ] M.Cassé et al., IEDM, p637,(2012)
[10] F.Arnaud et al., IEDM, p.48,(2012)
[11]F.Mayer et al., IEDM, p.163, (2008)
[12] E.Bernard et al., VLSI Tech. Symp. p.16, (2008).
[13] C.Dupré et al., IEDM, p.749, (2008)
[14] T.Ernst et al., IEDM, invited talk, p.745, (2008)
[15] K.Tachi et al., IEDM, p.313, (2009)
[16] J.Razafindramora et al.,ESSDERC, p.414, (2007)
[17] L.Perniola et al., IEDM, p.443, (2012)
[18] E.Vianello et al. , IEDM ,p741,(2012)
[19] A.Hubert et al, IEDM, p.637, (2009)
[20] L.Masoero et al., IEDM, p.215, (2011)
[21] M.Suri et al., IEDM, p235,(2012) and IEDM, p. 79, (2011)
[22] C.Cagli et al., IEDM, p.658, (2011)
[23] V.Deshpande et al., IEDM, p.195, (2012)
[24] M. Pierre et al., Nature Nano. 5, 133, 2010
[25] M.Fuechsle NatureNano, 2012
[26] A.Fuhrer et al. Nanoletters ,2009
[27] L.Matthey et al, Abstract #267, ECS Fall Meeting, 2012
[28] P. Batude et al. , VLSI Tech. Symp., p.166, (2009).
[29] P. Batude et al., IEDM, p. 346, (2009)
[30] P. Batude et al., IEDM, invited talk, p.151, (2011)
[31] E Mille et al, Nanotechnology, 165504, (2010)
[32] J.Arcamone et al., IEDM, p. 359, (2012) and IEDM, p. 669, (2011).
[33] N.Sillon et al. IEDM, invited talk, p. 595, (2008)
[34] G.Poupon et al., Proc IEEE, pp. 60-69, (2009)
[35] R.Taibi et al., IEDM, p.135, (2011)