Download Analysis of 7/8-nm Bulk-Si FinFET Technologies for 6T

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 4, APRIL 2016
Analysis of 7/8-nm Bulk-Si FinFET Technologies
for 6T-SRAM Scaling
Xi Zhang, Senior Member, IEEE, Daniel Connelly, Member, IEEE, Peng Zheng, Student Member, IEEE,
Hideki Takeuchi, Member, IEEE, Marek Hytha, Senior Member, IEEE, Robert J. Mears,
and Tsu-Jae King Liu, Fellow, IEEE
Abstract— The benefits of a super-steep retrograde (SSR) fin
doping profile, which can be achieved using the oxygen insertion
technology, are quantified via 3-D technology computer-aided
design simulations for the 7/8-nm bulk-Si FinFET technology
targeting low-power applications. A calibrated compact model
is then used to estimate the six-transistor static RAM cell
performance and yield. The SSR FinFET technology is projected
to provide for up to 100 mV reduction in minimum cell supply
voltage, to facilitate voltage scaling to below 0.50 V.
Index
Terms— FinFET,
six-transistor
(6T)
static
RAM (SRAM), super-steep retrograde (SSR), variability.
I. I NTRODUCTION
F
inFETs have been adopted for the high-volume production
of CMOS integrated circuits beginning at the 22-nm
technology generation [1], due to the superior electrostatic
integrity of these multigate transistor structures. Although
silicon-on-insulator wafers are ideal substrates for the manufacture of FinFETs with low OFF-state leakage current [2],
they are much more expensive than the conventional bulksi wafers. If a bulk-si wafer is used as the substrate for
FinFET fabrication, then heavy punch-through stopper (PTS)
doping is needed at the base of the fins to suppress OFF-state
leakage current. A conventional doping process results in
dopants within the fin (channel region), on the order of
5 × 1017 cm−3 , which degrades transistor ON-state current.
In addition, heavy channel doping results in increased processinduced variations in transistor performance, which pose a
serious challenge for achieving sufficiently high yield for large
static RAM (SRAM) arrays. In this paper, the benefits of a
Manuscript received November 9, 2015; revised January 26, 2016; accepted
January 28, 2016. Date of current version March 22, 2016. The work of
X. Zhang was supported by the Maxine Pao Memorial Scholarship Fund. The
review of this paper was arranged by Editor R. M. Todi.
X. Zhang, D. Connelly, and P. Zheng are with the Department of Electrical
Engineering and Computer Sciences, University of California at Berkeley,
Berkeley, CA 94720 USA (e-mail: [email protected]; djconnel@
yahoo.com; [email protected]).
H. Takeuchi, M. Hytha, and R. J. Mears are with Mears Technologies, Inc.,
Newton, MA 02459 USA (e-mail: [email protected];
[email protected];
robert.mears@mearstechnologies.
com).
T.-J. K. Liu is with the Department of Electrical Engineering and Computer
Sciences, University of California at Berkeley, Berkeley, CA 94720 USA, and
also with the Kavli Energy NanoScience Institute, Berkeley, CA 94720 USA
(e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2016.2523885
Fig. 1.
Simulated 3-D n-channel FinFET structures. The net dopant
concentration is represented in color using a hyperbolic arcsine scale.
super-steep retrograde (SSR) fin doping profile, which can be
achieved using the oxygen insertion technology [3], are quantified via 3-D device technology computer-aided design (TCAD)
simulations for the 7/8-nm bulk-si FinFET technology targeting low-power applications. The benefits of the SSR FinFET
technology [4] for facilitating reductions in six-transistor (6T)
static memory (SRAM) cell operating voltage are quantified.
II. B ULK -Si FinFET D ESIGN O PTIMIZATION
Fig. 1 shows a perspective view of the 3-D FinFET
structures simulated using Sentaurus Device [5] in this paper.
The gate length (L gate) is 15 nm, which corresponds to the
7/8-nm technology node in the International Technology
Roadmap for Semiconductors (ITRS) [6]. The equivalent gateoxide thickness is 0.64 nm. The fin height (HSi) is 40 nm,
the fin width (WSi ) is 8 nm, so that the fin aspect ratio
is 5, and the fin pitch is 30 nm based on Intel 22-nm [1]
and 14-nm FinFET technology [7]. The gate work function is
assumed to be tunable to achieve an OFF-state leakage current
specification (IOFF ) of 30 pA/μm (consistent with TSMC’s
16-nm FinFET technology [8]) for low-power applications.
The current is normalized to the effective channel width (Weff ),
which is defined as the peripheral length of the silicon fin
region. The fin shape is rectangular with rounded corners
(1-nm radius of curvature) for reduced gate leakage and
enhanced gate control [9], as in the Intel’s 14-nm FinFET
technology [7]. The thickness of the shallow trench isolation
oxide is 50 nm. The FinFET structures each comprise heavily
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ZHANG et al.: ANALYSIS OF 7/8-nm BULK-Si FinFET TECHNOLOGIES
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TABLE I
TABLE II
B ULK -Si FinFET D ESIGNS : N OMINAL PARAMETER VALUES
S UMMARY OF K EY P ERFORMANCE PARAMETERS
FOR THE O PTIMIZED FinFET D ESIGNS
doped raised source/drain (S/D) regions formed by selective
epitaxial growth (SEG) [10], for reduced parasitic resistance.
In this paper, the S/D junctions are assumed to have a
Gaussian doping profile with 2-nm/decade gradient and peak
concentrations 2 × 1020 cm−3 [11]. The SEG S/D regions
comprise doped silicon for n-channel FinFETs (nFETs), and
silicon-germanium (SiGe) with 50% germanium concentration [1] for p-channel FinFETs (pFETs), with parameter values
taken from [12]. Ohmic contacts (specific contact resistivity
3 × 10−9 · cm2 ) are made only to the top surfaces of the
SEG S/D regions. Table I summarizes the nominal values of
the various design parameters for the control FinFETs and the
SSR FinFETs.
The TCAD software package Sentaurus Device [5] was used
to simulate the FinFET performance using the drift-diffusion
transport model [13] calibrated to the ballistic Monte Carlo
simulations, the Philips unified model for carrier mobility,
the bandgap narrowing model, the density gradient quantization model, and the nonlocal-path trap-assisted tunneling
model [14]. The fin sidewall surfaces (along which the transistor current flows) are assumed to be {110} crystallographic
planes, with transistor current flow in a 110 direction.
To boost transistor ON-state current, 2-GPa (tensile) uniaxial stress is induced in the fin channel region for nFETs,
whereas −2-GPa (compressive) uniaxial stress is induced in
the fin channel region for pFETs.
The effective channel length (L eff ) and the peak location of
the PTS doping profile (X depth) for the SSR FinFETs are separately optimized to maximize the ON-state drive current Id,sat,
while meeting the same OFF-state current specification
(IOFF = 30 pA/μm). Table II summarizes the key performance
parameters for the optimized FinFET designs. Threshold voltage, Vt , is extracted based on a constant current criterion of
100 nA×(Weff /L gate ). For operating voltage VDD = 0.80 V
(consistent with ITRS 2013 specifications for the 7/8-nm
low-power technology node [6]), SSR FinFET provides for
3.6% and 3.8% improvement in Id,sat for nFETs and pFETs,
respectively. The benefit of higher carrier mobility is greater
for operation in the linear regime (Vgs = 0.8 V and
Vds = 50 mV): SSR FinFET provides for 6.7% and 6%
improvement in Id,lin for nFETs and pFETs, respectively.
Fig. 2 shows the net dopant concentration profiles along the
channel direction, from the source region to the drain region,
Fig. 2. Net dopant concentration profiles along the channel direction (left),
from the source region to the drain region, and fin doping depth profiles (right)
for the optimized control FinFETs and SSR FinFETs. L eff is defined as the
lateral distance between the points where the S/D dopant concentration falls to
2×1019 cm−3 , and is tuned to optimize the tradeoff between series resistance
and short-channel effect by adjusting spacer length L sp [15].
Fig. 3. Simulated Ids versus Vds characteristics of n-channel (left) and
p-channel (right) FinFETs.
and the optimized fin channel doping profiles, for each of
the optimized FinFET designs. The optimal value of X depth
is 46 nm and the optimal value of Nfin,peak is 5 × 1018 cm−3
for both n-channel and p-channel SSR FinFETs. Fig. 3 shows
the simulated Ids –Vds characteristics for the optimized FinFET
designs.
III. C OMPACT M ODEL C ALIBRATION
In this paper, a compact (analytical) model for transistor
current as a function of applied voltages is used to estimate
the 6T-SRAM cell performance and yield, following the
methodology established and validated with experimental
data in [16]. The model parameter values are chosen to
provide the best fit to TCAD 3-D device simulations, for each
n-channel or p-channel transistor design (SSR FinFET or
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Fig. 4. Comparison of the calibrated compact model (lines) and simulated
transfer characteristics (symbols) for nFETs.
Fig. 7.
Effects of fin-width variation on FinFET threshold voltage and
OFF-state leakage current.
TABLE III
Fig. 5. Comparison of the calibrated compact model (lines) and simulated
transfer characteristics (symbols) for pFETs.
Fig. 6. Effects of gate-length variation on FinFET threshold voltage and
OFF-state leakage current.
VARIABILITY IN FinFET S ATURATION T HRESHOLD V OLTAGE (Vt,sat ),
ON -S TATE C URRENT, AND OFF -S TATE C URRENT D UE
TO R ANDOM S OURCES OF VARIATION
predicts well the Vt roll-off effect. SSR FinFETs slightly show
the greater sensitivity of IOFF to changes in L gate , since the
heavily doped fin channel of control FinFETs mitigates the
short-channel effect.
Fig. 7 shows the dependences of Vt and IOFF on WSi .
The threshold-voltage magnitude increases (and hence, the
OFF -state leakage current decreases) with decreasing fin
width, due to the quantum confinement effect [17].
V. I MPACT OF R ANDOM S OURCES OF VARIATIONS
control FinFET). This model is based on the I –V equations
for a short-channel MOSFET, which account for channel
length modulation, velocity saturation, and bulk charge
effects. Figs. 4 and 5 show that the calibrated compact model
matches well the 3-D device TCAD simulations for both
control FinFETs and SSR FinFETs.
IV. I MPACT OF S YSTEMATIC S OURCES OF VARIATIONS
In this paper, process-induced variations in L gate and WSi are
assumed to have Gaussian distributions with ±10% variation
corresponding to three standard deviations away from the
mean (nominal) value.
Fig. 6 shows the dependencies of threshold voltage (Vt ) and
IOFF on L gate . It can be seen that the calibrated compact model
Random sources of variation become dominant as transistors are scaled down toward atomic dimensions, and can
limit the IC manufacturing yield [18]. These sources include
random dopant fluctuations (RDF) and gate work function
variation (WFV) [19], [20]. In this paper, the gate material
is assumed to be TiN with work function distributions taken
from [21]. The use of spacer lithography [22] to define
nanometer-scale critical dimensions (gate length and fin width)
is becoming prevalent, so that line-edge roughness is not
expected to be a significant source of random variability in
FinFET performance.
In this paper, random variability in transistor performance is determined using the noiselike impedance field
method [23], [24] via 3-D device TCAD simulations. The
ZHANG et al.: ANALYSIS OF 7/8-nm BULK-Si FinFET TECHNOLOGIES
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Fig. 8. Modeled write-N curves (left) and butterfly curves (right) for the
1-3-3 FinFET 6T-SRAM cell design. Iw is the minimum amount of current
flowing out of the internal storage node as it is discharged from VDD toward
ground potential. Read SNM corresponds to the length of the largest square
that fits within the smaller lobe of the butterfly plot.
TABLE IV
C OMPARISON OF FinFET-BASED 6T-SRAM C ELL
P ERFORMANCE M ETRICS (VDD = 0.80 V)
Fig. 9. Read SNM yield versus write-ability current yield, for the 1-2-1,
1-2-2, and 1-3-3 SRAM cell designs comprising either SSR FinFETs (filled
symbols) or control FinFETs (open symbols). Cell operating voltage VDD is
varied from 0.38 to 0.80 V in 60-mV steps.
results summarized in Table III show that the SSR FinFETs
have good immunity to RDF, since they have relatively light
dopant concentration within the (fully depleted) fin channel
region, so that the depletion charge negligibly affects the
threshold voltage. Note that the results show that WFV has
a dominant effect, which is consistent with the previous work,
identifying WFV as the dominant contributor to Vt variation
for the FinFET technology [18]. Overall, SSR FinFETs are
less susceptible to random sources of variation and, therefore,
are promising for achieving higher IC manufacturing yield.
VI. 6T-SRAM C ELL P ERFORMANCE
The 6T-SRAM cell read stability and write ability are
gauged by the read static noise margin (SNM) and writeability current (Iw ) [25] metrics derived from the butterfly
plot and write-N curve generated using the calibrated model
mentioned above. The cell beta ratio is defined as the ratio
of the n-channel pull-down (PD) transistor drive (ON-state)
current to the n-channel pass-gate (PG) transistor drive
current. For the planar MOSFET technology, this ratio can
be finely tuned by adjusting the drawn channel widths of the
PD and PG transistors. For the FinFET technology, it can
only be practically tuned coarsely by adjusting the number of
fins (connected in parallel between the source and the drain
regions) in each device. Better read stability is achieved by
using more fins for the PD devices than for the PG devices.
Fig. 8 shows the modeled butterfly curves and write-N
curves for the 1-3-3 FinFET 6T-SRAM cell design, which
comprises one fin in each of the p-channel pull-up (PU)
transistor, three fins in each of the PD device, and three fins
in each of the PG device. Table IV summarizes the read
SNM and Iw values for different cell designs. It can be seen
that the SSR FinFETs provide for better 6T-SRAM cell write
ability, because the gamma ratio (PG nFET to PU pFET drive
current ratio) for the SSR FinFET technology (1.08) is larger
than that for the control FinFET technology (1.06). The read
SNM for the SSR FinFET technology is comparable to that
for the control FinFET technology, since the cell beta ratio
is determined by the ratio of the number of fins in the PD
transistor to the number of fins in the PG transistor, which is
the same for both technologies.
VII. 6T-SRAM Y IELD E STIMATION
Variability in transistor performance due to systematic and
random sources of variation in the fabrication process can
result in a 6T-SRAM cell with read SNM <0 V or Iw < 0,
which does not function properly, i.e., cell failure. Previous
work [19], [26] has shown that the threshold-voltage Vt
distributions caused by random sources of variations are close
to Gaussian. Cell sigma [16] is defined as the minimum total
number of standard deviations from the nominal value, for
any combination of 18 device parameters (gate length, fin
width, and threshold voltage for each of the six transistors in a
6T-SRAM cell), that causes a read disturb error or a write
failure. By assuming that 3σ deviation from the mean
(nominal) value corresponds to ±10% variation for L gate and
for Wfin , and accounting for random Vt variations due to WFV
and RDF, the cell sigma is modeled in a multidimensional
variation space.
Lower operating voltage is beneficial for reducing power
consumption, but can result in lower nominal values of read
SNM and/or Iw and, therefore, higher probability of cell
failure due to variations. The minimum cell operating voltage (VDD,min) is defined as the lowest operating voltage for
which the cell meets the six-sigma yield requirement (for
SRAM arrays with greater than 256-Mb capacity) for both
read SNM and Iw .
The methodology established by [16] is used, herein, to
determine the read SNM and Iw cell sigma values, based
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 4, APRIL 2016
TABLE V
C OMPARISON OF M INIMUM O PERATING V OLTAGE (VDD,min )
FOR VARIOUS FinFET-B ASED 6T-SRAM C ELL D ESIGNS
on the sensitivities of these SRAM metrics to each device
parameter. Fig. 9 directly compares cell sigmas for the
SSR FinFET technology versus control FinFET technology,
for the 1-2-1, 1-2-2, and 1-3-3 cell designs. Lowest Vdd,min
is found to be 0.40 V and 0.46 V, respectively, for the
SSR FinFET technology and the control FinFET technology.
Table V summarizes Vdd,min for various SRAM cell designs.
It shows that the 1-2-1 cell design has the worst VDD,min
despite having the best read SNM, as shown in Table IV.
This is because VDD,min is actually limited by Iw cell sigma
because stronger PU devices limit PG devices’ capability to
pull the internal node down to GND. The 1-2-2, 1-3-2, and
1-3-3 cell designs implemented with the SSR FinFET
technology are projected to be able to scale to operating
voltages below 0.50 V.
VIII. C ONCLUSION
An SSR fin channel doping profile enabled by oxygen
insertion technology is beneficial for improving device
performance (particularly Id,lin by 6.7% for nMOS and
by 6% for pMOS) and for reducing the sensitivity of device
performance to process-induced variations. These benefits
are provided for superior write ability of 6T-SRAM cells,
and are projected to facilitate reductions in the minimum
cell operating voltage (by as much as 100 mV as compared
with the conventional FinFET technology), to below 0.50 V.
Noticeably, the 1-1-1 SSR FinFET cell design scales VDD,min
to 0.50 V, comparable with the 1-3-2 control FinFET
cell design. Notably, the 1-1-1 SSR FinFET cell design is
projected to allow VDD,min to be scaled down to 0.50 V,
comparable with the larger 1-3-2 control FinFET cell design.
Thus, the SSR FinFET technology can provide for 20%
savings in SRAM cell area, based on the FinFET layout
design rules in [7] and [27]. This paper shows that the bulk-si
FinFET technology can extend CMOS scaling beyond the
10-nm node.
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ZHANG et al.: ANALYSIS OF 7/8-nm BULK-Si FinFET TECHNOLOGIES
Xi Zhang (SM’14) received the B.S. degree from the
School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu,
China, in 2013. She is currently pursuing the
Ph.D. degree in electrical engineering with the
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley,
Berkeley, CA, USA.
Daniel Connelly (M’16) received the Ph.D. degree
from Stanford University, Stanford, CA, USA.
He was involved in the advanced CMOS technology development at Acorn Technologies, La Jolla,
CA, USA, and then in the device simulation and
modeling at Synopsys, Mountain View, CA, USA.
He is currently a Visiting Scholar with the University
of California at Berkeley, Berkeley, CA, USA.
1507
Hideki Takeuchi (M’00) received the B.E. and
M.E. degrees from The University of Tokyo, Tokyo,
Japan, in 1988 and 1990, respectively.
He has been involved in the DRAM product development and various research projects on advanced
CMOS, memories, and MEMS processes/devices.
He is currently with Mears Technologies Inc.,
Newton, MA, USA, where he is involved in
process integration of the oxygen-insertion
technology (MST) for various CMOS products.
Marek Hytha (SM’14) received the M.Sc. and
Ph.D. degrees in condensed matter physics from
Charles University, Prague, Czech Republic, in 1988
and 1997, respectively.
He spent five years with Charles University, as
an Assistant Professor. He has been with Mears
Technologies Inc., Newton, MA, USA, since 2003,
where he is currently the Chief Scientist.
Robert J. Mears, photograph and biography not available at the time of
publication.
Peng Zheng (S’11) received the B.S. degree in
microelectronics from Tianjin University, Tianjin,
China, in 2010, and the M.S. degree in electrical
and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2012.
He is currently pursuing the Ph.D. degree in electrical engineering with the Department of Electrical
Engineering and Computer Sciences, University of
California at Berkeley, Berkeley, CA, USA.
Tsu-Jae King Liu (SM’00–F’07) received the B.S.,
M.S., and Ph.D. degrees from Stanford University,
Stanford, MA, USA, all in electrical engineering.
She is currently the TSMC Distinguished Professor of microelectronics with the Department
of Electrical Engineering and Computer Sciences,
University of California at Berkeley, Berkeley,
CA, USA. Her current research interests include
energy-efficient IC devices.