Download An Ultra-low Power Temperature Independent Subthreshold CMOS

International Journal of Advanced Biotechnology and Research (IJBR)
ISSN 0976-2612, Online ISSN 2278–599X,
Vol-7, Special Issue-Number5-July, 2016, pp1024-1029
http://www.bipublication.com
Research Article
An Ultra-low Power Temperature Independent Subthreshold
CMOS Bandgap Reference
Nima Alimohammadi1, Mohamad Hossain Mesgarof Asad Abadi2,
Abbas Golmakani 2
1
Faculty of Electrical Engineering,
Iran University of Science and Technology, Tehran, Iran
2
Faculty of Electrical Engineering,
Sadjad University of Technology, Mashhad, Iran
ABSTRACT
An ultra-low power reference voltage circuit is presented. It works in the range of 500 mV to 2 V with a current
range of 600 pA to 5.24 nA respectively. In order to minimize power consumption all transistors are biased in weak
inversion region. A mean reference voltage of 341.14 mV is calculated by using Monte Carlo statistical analysis.
Simulating in different circumstances demonstrates a minimum dependency of this circuit on the corners of process
changing only from 337.8 mV to 347.1 mV. Power Supply Rejection Ratio of this circuit is less than -40dB at 10 Hz
and maximum Equivalent output simulated noise is 65.97 uV/ (Hz) 1/2.
Key words:- voltage reference; sub threshold design; low power; standard CMOS design; Analog design.
1. INTRODUCTION
Owing to low power consumption, sub-threshold
circuits are being pervasively used in new designs
of many electronic scenarios where battery
replacement is not cost-effective. This growing
interest drives the demands for circuits operating
in sub-microwatt power. For instance, in sensor
networks and biomedical implants, power
consumption is the most important factor to make
the lifetime of the system long enough for a
practical use, or in a digital circuit sub-threshold
and near-threshold circuits can be employed for
low power operations. This supply voltage
reduction is achieved by using sub-threshold
circuits that can provide power for extra
applications like biomedical implants and micro
sensors in the same circuit.
Bandgap references (BGR) circuits are able to
create exact voltage reference therefore they have
been used in many applications [1]. The
importance
of
achieving
lower
power
consumption is even more in voltage reference
generators since they play an important role in
Analog to Digital and Digital to Analog
Converters where a stable DC voltage independent
of supply voltage and temperature is needed. They
are also widely used in comparators, flash
memories, PLLs, capacitance-to-digital convertors
and Power management circuits [2], [3]. The
desire for low-power circuits is increasing rapidly
in portable devices [4]. For a better compatibility,
voltage reference circuits are usually designed in
standard CMOS process by exploiting the
parasitic vertical BJTs [5], [6]. However, this is
not the sole solution, There are other voltage
references based on using transistors with two
different threshold voltages in the same CMOS
technology, Employing various materials for the
gate stack [7], or using a selective channel implant
[8], [9]. Because of requiring additional steps
while fabricating, these solutions cannot be
An Ultra-low Power Temperature Independent Subthreshold CMOS Bandgap Reference
implemented. Typically, Bandgap voltage
references provide a nearly voltage independent of
about 1.25 V and therefore they require a higher
supply voltage. But some solutions have been
offered in order to generate a sub-1V reference
voltage [10]. Resistive subdivision is used in [11],
[12] to decrease the reference voltage. Floating
gate structure has also been used as another
approach to reach high precision programmable
voltage reference [13]. Most of PN-junction BGRs
are substituted with MOSFETs working in subthreshold region [14].
In this paper a CMOS voltage reference, which
exploits the MOS characteristics in the subthreshold voltage is proposed. This design is able
to operate with a supply voltage between 0.5V and
2.2V, with power consumption lower than 10
Nano Watt. This paper is organized as follows: in
section 2 the principle of voltage reference’s
operation is discussed. In part 3 the schematic and
configuration of proposed circuit is presented and
in section 4 simulation results are shown and
compared with other works. Finally, in section 5
we summarize our work.
gate-source voltage (VGS) and the drain-source
voltage.
(1)
Where k= (W/L) COX , It is obvious that W/L and
COX are the transistor aspect ratio and capacitor
per unit area respectively. µ is electron mobility,
VT =KBT/q is thermal voltage, Vth is the MOSFET
threshold voltage, n is the sub-threshold slope
parameter and VGS and VDS are the gate-to-source
and drain-to-source voltages respectively.
Considering VDS>4VT, ID will not be depended on
VDS, therefore VREF is calculated as below:
(2)
It should be mentioned that threshold voltage of
MOSFET is reduced linearly by temperature as
shown in equation 3.
(3)
VTH0 is the threshold voltage at T= 273.15k, VBS is
body-to-source voltage of the transistor and Kt1
and Kt2 are negative temperature coefficients.
Satisfying equation (4) will make us sure to have a
temperature compensated output reference voltage
[15]:
(4)
Using equation (2), a simple solution of (4) can be
obtained by generating the current ID with the
following temperature dependence:
Fig. 1. Simple voltage reference
2. OPERATING PRINCIPLE
Using a current source and a diode connected
NMOS; a voltage reference can be represented.
Fig.1 demonstrates this simple circuit. As shown
in Fig.1 voltage reference consists of three main
parts namely, start-up circuit, current reference
and output reference voltage. All transistors in
proposed voltage reference are standard threshold
voltage MOSFETs. The main aim of using startup circuit is to guarantee a desirable operation
condition which is biased in weak inversion
region. The drain current of a MOSFET in subthreshold region is an exponential function of the
Nima Alimohammadi, et al.
(5)
Since VBS=0 we have:
(6)
It is worth noting that this solution does not
necessarily provide sub-threshold operation for
the active load. Therefore further calculation and
analysis is needed [11].
(7)
If the term in brackets in (7) be constant with
temperature it is highly likely that we reach a
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An Ultra-low Power Temperature Independent Subthreshold CMOS Bandgap Reference
temperature compensation. A possible solution for
ensuring sub-threshold operation is satisfying
equation (8):
(8)
In which A, B and C are constant with
temperature. The reason for choosing this
solution is easy generation with a sub –
threshold MOSFETs based current reference.
Substituting (8) in (2) gives following formula:
(9)
The load transistor can work in sub-threshold
region if the term B/C is negative.
Fig. 2 (a). Pseudo resistor used in start-
3. PROPOSED CONFIGURATION
A pseudo resistor has been employed in start-up
circuit in order to have a stable bias point while
we have supply voltage or temperature variation.
The structure of this resistor and simulation results
of this section are illustrated in Fig. 2. The main
purpose of this design is using no resistor which
reduces the power consumption of whole circuit.
An optimized current circuit is being exploited for
a standard CMOS implementation rather than
using dual threshold MOSFETs. This is because
of many reasons such as lower price.
The current reference part of this circuit provides
the current of third section to generate the output
reference voltage. Fig. 3 demonstrates the
proposed circuit in this paper.
Simulations are carried out in 0.18um TSMC
technology. Table I. shows the transistor sizes
used in the simulations. In order to lower the
current leakage of proposed circuit the length of
transistors are maximized then the required
resistance is calculated. Another pseudo resistor
structure is used in output circuit which generates
the appropriate voltage.
up
Fig. 2 (b). Simulated Resistance for pseudo Resistor
Fig. 3. Proposed voltage reference
TABLE 1. Transistor Size
Transistors size W/L
Transistor
0.22µm/20µm
0.22µm/20µm
8 µm/20 µm
15 µm/20 µm (m=5)
20 µm/20 µm (m=5)
2 µm/2 µm
20 µm/20 µm (m=2)
M4
M5
M7
M8
M9
M10
M11
Nima Alimohammadi, et al.
0.22µm/20µm
100µm/0.22µm
M12-15
M16
The high impedance elements per branch are
potentially capable of absorbing supply voltage
variations leaving their current almost unchanged
[16].
4. SIMULATION RESULTS
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An Ultra-low Power Temperature Independent Subthreshold CMOS Bandgap Reference
In this section, simulated results of proposed
circuit are discussed. Using 0.18- µm TSMC
CMOS processes, following simulation results are
achieved. In Fig. 4 the characteristic of circuit at
27º C is reported. Simulations in different corners
of process are illustrated and compared in this
Figure. It is clearly seen that designed circuit is
noticeably process independent.
A proper work of presented circuit starts at 500
mV, but for more insurance it is suggested to be
used after 600 mV. The mean reference voltage of
341.14 mV is produced in the supply voltage
range from 0.45 V to 1.8 V. As it is shown in Fig.
5 there is almost no change in DC current for
supply voltages varied from 0V to 0.9 V (it is in
the order of hundred Pico Amperes). Maximum
power consumption of proposed circuit is 9.36 nW
at room temperature. The dependency of output
voltage reference to temperature is shown in Fig.
6. It should be mentioned that VREF in this figure
is normalized to the mean of Vref.
Fig. 6. Supply voltage versus temperature
Fig. 7. Equivalent output noise from 0.1 Hz to 10
Hz
Fig. 4. VRef Versus VSupply
Fig. 8. PSRR at 1.8V
Fig. 5. DC current versus VSupply
Nima Alimohammadi, et al.
The equivalent output noise of proposed circuit is
simulated, which is always less than 65.97 uV/ .
Fig. 7 shows the results of this part. The simulated
power supply rejection ratio (PSRR) values is
demonstrated in Fig. 8 which satisfies our
demands in this circuit.
The high output impedance of proposed circuit is
also an advantage which makes it suitable for
using in various circuit designs.
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An Ultra-low Power Temperature Independent Subthreshold CMOS Bandgap Reference
5. CONCLUSION
A 340 mV Low Power process Independent Subthreshold Standard CMOS Voltage Reference is
presented. All transistors are biased in weak
inversion which paves the way to reach a lower
power consumption. The performance of
presented circuit is almost independent to
temperature and process. Line sensitivity of
0.51mV/V in the range of 600 mV to 1.8 V. The
maximum current at 1.8V is about 5.24 nA which
leads to have just 9.4 Nano watt power
dissipation. The low power consumption and high
output impedance make this circuit suitable for
driving digital gates.
Table 2. Comparison Of Published Cmos Voltage Reference Circuits
Ref.[15]
Ref.[16]
Ref.[17]
This work
Technology(CMOS)
Supply Voltage(V)
Vref(mV)
PSRR(dB)
0.18µm
0.45- 2
263.5
-12
0.18µm
0.9-2
670
-40
0.18µm
0.6-2.3
220
-41
0.18µm
0.5-2.2
341.14
-39.036
Supply Current(nA) At room Temp
[email protected]
[email protected]
[email protected]
[email protected]
Line Sensitivity (%/V)
0.440
0.270
~2.730
0.51
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