Download I3600 Homework 3

I3600 Homework 3 Solutions
R1. Because in a MOSFET, most of the important things happen at the silicon surface
including the path of the charge carriers through the channel. In a BJT, the interfaces
between the emitter and base and the base and collector are within the silicon and not
next to any silicon surface. Hence the surface properties of silicon play much less of a
role in BJTs than they do in MOSFETs.
R2. MOSFET: The acronym stands for Metal Oxide Silicon Field Effect Transistor.
The MOS part means that there are three layers: a metal gate layer, a thin gate oxide
layer and a silicon layer. The FET part means that the transistor or trans-resistor is
operated by effect of electric fields applied to it by the gate oxide.
R3. Identify the materials most commonly used in MOSFET devices. This has changed
throughout the years but generally it would include:
1. Polysilicon for the gate
2. Thermally grown oxide for the gate oxide
3. Silicon, whether it is float zone or CZ grown silicon or epitaxially grown silicon.
R4. There are JFETs and MESFETs besides the more common MOSFETs. JFETs or
Junction Field Effect Transistors use a PN junction to define the conducting channel and
MESFETs Metal Semiconductor Field Effect Transistors use a Schottky junction to
define the channel.
R5. The source in a MOSFET is the region of the device that supplies the charge carriers
to the channel, either electrons in a NMOSFET or holes in a PMOSFET. The drain
therefore is the region of the device that receives the carriers from the channel and
supplies it to the external circuit.
R6. The bias polarity that produces useful results depends on the type of MOSFET. We
have either enhancement mode MOSFETs and depletion mode MOSFETs. In both, we
can have n-channel MOSFETs and p-channel MOSFETs. We have therefore the
following important bias conditions:
1.
2.
3.
4.
N-channel Enhancement Mode: VGS>0
P-channel Enhancement Mode: VGS<0
N-channel Depletion Mode: VGS<0
P-channel Depletion Mode: VGS>0
R7. Flatband voltage is the voltage, applied at the gate relative to the source, necessary
to produce flat conduction, valence energy bands and intrinsic Fermi levels.
R8. What is subthreshold current and what accounts for it. Subthreshold current is
produced by a diffusion current component.
R9. Explain, with examples, the terms unipolar and bipolar. Unipolar devices such as
the FETs rely on the flow of one type of carriers for the operation. Bipolar devices such
as the BJT rely on the flow of two types of carriers for its operation.
R10 There were numerous fabrication issues that needed to be dealt with including
contamination issues and oxide defects that produced unreliable or low quality devices.
R11. The mobility of electrons is much higher than the mobility of holes both in the bulk
and at a surface. The mobility is decreased at a surface because of scattering effects.
R12. The threshold for weak inversion is when the intrinsic Fermi level coincides with
the Fermi level.
R13. The threshold for strong inversion is when the minority carrier concentration at the
oxide/Si interface is equal to the majority carrier concentration in the bulk Si material.
R14. Sheet resistance is the resistance per unit square parallel to current flow as shown
in Fig. 1-3. The total resistance for the actual device is easily obtained by multiplying the
sheet resistance by the length L and dividing by the width Z.
R15. The dielectric constant of Si at about 11.7 is about three times larger than the
dielectric constant of oxide at around 3.9.
R16. The surface depletion layer stops growing because any additional applied gate
voltage and associated gate charge is compensated by the inversion layer charge near the
oxide/Si interface. Only the inversion layer charge grows and not any addition charge in
the depletion layer. Essentially, the inversion layer acts like a clamp on the size of the
depletion layer.
R17. When analyzing the current versus VDS dependence using VGS as a parameter, it
was seen that the drain current ID had a maximum. For higher VDS, the current saturated
and stayed constant. This saturated drain current was proportional to the square of VGS
and hence the aptly named square law equation.
R18. We assume the device is one dimensional, the channel is long, and the MOS
capacitor is a parallel plate capacitor.
R19. The two operating regimes are the curved regime and the saturation regime which
reside at VDS  VGS  VT and VDS  VGS  VT respectively.
R20. The drain current is independent of source-drain voltage in saturation because there
are two competing phenomena that offset each other. One phenomenon is the increasing
VDS should cause for increasing current due to an increased electric field along the length
of the channel. However, the second phenomenon of decreasing channel depth caused by
the increasing VDS offsets the first phenomenon by increasing the channel resistance.
R21. E-mode means enhancement mode MOSFETs where the initial state is
nonconducting and an applied gate voltage “enhances” the conductance of the device. Dmode is when the initial state is conductive and an applied gate voltage of the proper size
and polarity will deplete the channel of carriers and minimize the conduction. E-D
circuits are circuits composed of both E-mode and D-mode MOSFETs and are
advantageous because an applied gate voltage can turn on the E-mode MOSFET while at
the same time turning off the D-mode MOSFETs. There are also advantages in terms of
power consumption.
R22. The D-mode MOSFET is essentially a hybrid MOSFET/JFET with a depletion
layer produced next to the oxide/Si interface as would be done in an E-mode MOSFET
but this depletion layer will eventually cause the device to be less conduction. The
bottom junction of the D-mode MOSFET is a pn junction similar to a JFET.
R23. Using the square-law model, the transconductance will depend linearly on the input
gate voltage according to the equation: g m  2 K VGS  VT  .
R24. The following circuit where the E-mode MOSFET is operated in the linear regime
or when VDS  VDS sat . The input voltage is Vin and the amplified signal is Vout.
R25. The saturated load circuit is shown in Fig. 1-14. With this inverter circuit it is seen
that the load is another E-mode transistor that is turned on an off as the driver is turned on
and off. The circuit has the disadvantage that the performance in terms of frequency
response is much lower than the resistive load. The circuit has the advantages of lower
cost, smaller area, and easier fabrication.