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Article
An Isolated Three-Port Bidirectional DC-DC
Converter with Enlarged ZVS Region for HESS
Applications in DC Microgrids
Cheng-Shan Wang 1 , Wei Li 1 , Yi-Feng Wang 1, *, Fu-Qiang Han 1 , Zhun Meng 1
and Guo-Dong Li 2
1
2
*
School of Electrical Engineering and Automation, Tianjin University, Tianjin 300072, China;
[email protected] (C.-S.W.); [email protected] (W.L.); [email protected] (F.-Q.H.);
[email protected] (Z.M.)
Electric Power Research Institute, State Grid Tianjin Electric Power Company, Tianjin 300384, China;
[email protected]
Correspondence: [email protected]; Tel.: +86-022-2740-1479
Academic Editor: Gabriele Grandi
Received: 15 February 2017; Accepted: 24 March 2017; Published: 1 April 2017
Abstract: In this paper, a two-stage three-port isolated bidirectional DC-DC converter (BDC) for
hybrid energy storage system (HESS) applications in DC microgrids is proposed. It has an enlarged
zero-voltage-switching (ZVS) region and reduced power circulation loss. A front-end three-phase
interleaved BDC is introduced to the supercapacitor (SC) channel to compensate voltage variations
of SC. Consequently, wide ZVS range and reduced circulation power loss for SC and DC bus
ports are achieved under large-scale fluctuating SC voltage. Furthermore, a novel modified
pulse-width-modulation (PWM) and phase-shift (PHS) hybrid control method with two phase-shift
angles is proposed for BA port. And it contributes to an increasing number of switches operating
in ZVS mode with varying battery (BA) voltage. Phase shift control with fixed driving frequency is
applied to manage power flow. The ZVS range as well as the current stress of resonant tanks under
varying port voltages is analyzed in detail. Finally, a 1 kW prototype with peak efficiency of 94.9% is
built, and the theoretical analysis and control method are verified by experiments.
Keywords: hybrid energy storage system; there-port isolated converter; series resonant BDC;
phase shift control; hybrid control method
1. Introduction
The development and utilization of renewable energy have turned out to be new solutions for
the worldwide energy depletion and environmental pollution problems [1]. In order to achieve
efficient utilization of distributed energy generations, DC microgrid has become a research focus
in recent years [2–4]. However, the output of several renewable energy sources is intermittent and
time-varying, and the load demand is uncertain [5]. Therefore, storage units are usually used to balance
the power supplies and loads in DC microgrids. Several studies use hybrid energy storage systems
(HESSs), which are composed of SC and BA, to improve stability and reliability of DC microgrid [6–8].
Numerous literatures have researched on energy management and power sharing strategy of HESS in
DC microgrid [9–16]. While, the design of interface converters between HESS and DC microgirds is
still considered as an emerging area of research.
Three-port BDC, which integrates SC and BA converters into one dual-input converter, will assist
to improve the efficiency, power density and control coordination of HESS converters. Many three-port
BDCs have been reported in literatures. According to the connection methods, three-port BDCs can be
Energies 2017, 10, 446; doi:10.3390/en10040446
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Energies 2017, 10, 446
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categorized into three types: non-isolated, partly-isolated and isolated converters. Typical structures
of three-port BDCs are shown in Figure 1 [17].
Energies 2017, 10, 446
Energies 2017, 10, 446
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Figure 1. Typical structure of three-port converter: (a) non-isolated; (b) partly-isolated; (c) isolated.
Figure 1. Typical structure of three-port converter: (a) non-isolated; (b) partly-isolated; (c) isolated.
Figure 1a shows the diagram of non-isolated three-port converter [18,19], and Figure 1b presents
the topology of partly-isolated converter [20–22]. The common shortcomings of non-isolated and
Figure 1a
shows the diagram of non-isolated three-port converter [18,19], and Figure 1b presents
partly-isolated three-port converters are the lack of complete electrical isolation among three ports,
the topologyand
ofbeing
partly-isolated
converter
[20–22].
The
common
shortcomings
of non-isolated
and
unable to cope with
wide operating
voltage
ratio.
For the HESS
application, security
is of
greatthree-port
importance, converters
and thus, electrical
isolation
isof
essential.
In consequence,
the
isolated structure
partly-isolated
are
the
lack
complete
electrical
isolation
among
three
ports,
Figure 1. Typical structure of three-port converter: (a) non-isolated; (b) partly-isolated; (c) isolated.
shown in Figure 1c is adopted in this article [23,24].
and being unable
to cope with wide operating voltage ratio. For the HESS application, security is
Numerous isolated three-port DC-DC converters have been proposed to integrate two energy
Figure
1a shows
the diagram
of non-isolated three-port
converter
[18,19], and Figure
1bisolated
presents structure
of great importance,
thus,
electrical
is essential.
In consequence,
the
sources intoand
one dual-input
converter.isolation
The three-port
triple-active-bridge
(TAB) converter
shown
in
the topology of partly-isolated converter [20–22]. The common shortcomings of non-isolated and
Figure1c
2, is
as adopted
the most widely
disseminated
isolated three-port topology, attracts a lot of attentions
shown in Figure
in
this
article
[23,24].
partly-isolated
three-port converters are the lack of complete electrical isolation among three ports,
from researchers [23–29]. In [26], a TAB converter is used to deal with a hybrid energy source
Numerous
isolated
DC-DC
converters
have
proposed
to integrate
two energy
andconsisting
being
unable
tothree-port
cope
with
wide
operating
voltagethat
ratio.
Forbeen
the HESS
application,
securityofis of
of full
cell
and
super
capacitor.
It appears
TAB
converter
has
attractive features
great
importance,
andbidirectional
thus, electrical
isolation
is essential.
Inand
consequence,
isolated
structure
sources into
one
dual-input
converter.
The
three-port
triple-active-bridge
(TAB)
converter
shown in
galvanic
isolation,
power
flow,
ZVS
operation
phase shift the
control
with
fixed
shown
in Figure
1c is adopted
in this
article
[23,24].
switching
frequency.
However,
power
transfer
among
three ports
in TABattracts
is coupled,
therefore,
Figure 2, as
the
most
widely
disseminated
isolated
three-port
topology,
a lot
of attentions from
Numerous
isolated three-port
DC-DCWhat’s
converters
been proposed
to integrate
two energy
decoupling
is required.
more,have
the power
of TAB topology
is
researchers
[23–29].
Incontrol
[26], algorithm
a TAB
converter
is
used
totriple-active-bridge
deal
withtransmission
a hybrid
energy source
consisting of
sources
into proportional
one dual-input
converter.
The of
three-port
(TAB)ofconverter
shown in
inversely
to the
impedance
inductance.
While, the inductance
TAB is inherent
full cell and
super
capacitor.
It appears
TAB
converter
hastopology,
attractive
features
ofattentions
galvanic isolation,
greater
than
leakage
inductor
ofthat
transformer.
In case
of high
power
levels,
switching
frequency
Figure
2, as
thethe
most
widely
disseminated
isolated
three-port
attracts
a lot of
has
to be reduced
toZVS
get realizable
value.
In
thedeal
driving
frequency
areenergy
all 20 kHz,
from
researchers
[23–29].
Inoperation
[26], ainductance
TABand
converter
is [26–29]
used to
with
a hybrid
source frequency.
bidirectional
power
flow,
phase
shift
control
with
fixed
switching
and this of
will
be cell
detrimental
for realizing
high
power density.
consisting
full
and
super
capacitor.
It
appears
that
TAB
converter
has
attractive
features
of algorithm
However, power transfer among three ports in TAB is coupled, therefore, decoupling control
galvanic isolation, bidirectional power flow, ZVS operation and phase shift control with fixed
is required.
What’s more, the power transmission of TAB topology is inversely proportional to the
switching frequency. However, power transfer among three ports in TAB is coupled, therefore,
impedance
of
inductance.
While, the
inductance
TABthe
is power
inherent
greater of
than
leakage
decoupling
control algorithm
is required.
What’sofmore,
transmission
TABthe
topology
is inductor
inversely
to power
the impedance
inductance.frequency
While, the inductance
TAB is inherent
of transformer.
In proportional
case of high
levels,ofswitching
has to beofreduced
to get realizable
greater
thanIn
the[26–29]
leakage the
inductor
of transformer.
In case
switching
frequency
inductance
value.
driving
frequency
are of
allhigh
20 power
kHz, levels,
and this
will be
detrimental for
has to be reduced to get realizable inductance value. In [26–29] the driving frequency are all 20 kHz,
realizing high
power density.
and this will be detrimental for realizing high power density.
Figure 2. Topology of the isolated three-port BDC based on transformer and inductor.
In order to solve problems of TAB mentioned above, a series-resonant (SR) based converter is
proposed in [30]. The impedance of SR tank is determined by value of inductor and capacitor together
with the switching frequency. Therefore, it can operate at higher frequency under high power level.
In [31,32], renewable source, battery and load are integrated to a three-port SR BDC. The driving
frequency is 100 kHz, which is apparently higher than 20 kHz of TAB as shown in [26–29]. What’s
more, power flow among three ports can be controlled independently since there are only two SR
tanks. Nevertheless, the three-port SR BDC still suffers disadvantages including losing ZVS operation
Figurecurrent
2. Topology
the isolated
three-port
BDC based
on transformer
and inductor.
and increased
stressofunder
wide voltage
variations.
However,
previously
published works
Figure 2. Topology of the isolated three-port BDC based on transformer and inductor.
mainly concentrated on the operating characteristics of SR BDC with fixed port voltages. The
In order to solve problems of TAB mentioned above, a series-resonant (SR) based converter is
proposed in [30]. The impedance of SR tank is determined by value of inductor and capacitor together
In order to solve problems of TAB mentioned above, a series-resonant (SR) based converter is
with the switching frequency. Therefore, it can operate at higher frequency under high power level.
proposed in
[30]. The
impedance
SR tank
determined
bytovalue
of inductor
and
In [31,32],
renewable
source,of
battery
and is
load
are integrated
a three-port
SR BDC.
Thecapacitor
driving together
with the switching
Therefore,
it can
operate
higher
frequency
high
power level.
frequency isfrequency.
100 kHz, which
is apparently
higher
than 20atkHz
of TAB
as shown inunder
[26–29].
What’s
power flow
amongbattery
three ports
canload
be controlled
independently
since there are
only
two SR
In [31,32],more,
renewable
source,
and
are integrated
to a three-port
SR
BDC.
The driving
Nevertheless, the three-port SR BDC still suffers disadvantages including losing ZVS operation
frequencytanks.
is 100
kHz, which is apparently higher than 20 kHz of TAB as shown in [26–29]. What’s
and increased current stress under wide voltage variations. However, previously published works
more, power
flow
among three
can characteristics
be controlled
since
areThe
only two SR
mainly concentrated
on theports
operating
of independently
SR BDC with fixed
portthere
voltages.
tanks. Nevertheless, the three-port SR BDC still suffers disadvantages including losing ZVS operation
and increased current stress under wide voltage variations. However, previously published works
Energies 2017, 10, 446
3 of 23
mainly concentrated on the operating characteristics of SR BDC with fixed port voltages. The methods,
which can enlarge ZVS region and reduce circulation power loss under varying port voltages, are still
considered as emerging area of research.
Two methods for enlarging ZVS range and decreasing power circulation loss under DAB and TAB
topologies are reported in [33–36]. One method is to adopt improved control algorithm. Literature [34]
has presented an improved modulation control approach, where two phase-shift angles are employed
to minimize the switching losses for DAB under light load. Another alternative method is to use
a front-end converter to keep input voltage of bridge constant, as suggested in [36]. These two methods
effectively improve the characteristics of TAB converters with wide voltage variations. Unfortunately,
few of literatures have ever investigated the validity of these two methods in three-port SR BDC under
varying port voltages.
Based on the SR BDC, this article proposes a two-stage three-port BDC to integrate HESS and
DC microgrid. The subject of this paper is to enlarge the ZVS operating range and to reduce the
circulation power loss of the proposed three-port SR BDC. Then, by comprehensively considering the
large SC’s and small BA’s voltage fluctuation ranges, two different methods are adopted in SC and
BA channels respectively. For the SC channel, a three-phase interleaved BDC is introduced to convert
the widely fluctuating V SC to a fixed voltage V dc-link . This method guarantees the unity voltage gain
between SC and DC bus ports. The BDC adopts the interleaved structure to improve the power level
of the BDC, and to reduce the SC current ripple as well as the inductor size [37,38]. Additionally,
a PWM and PHS (PWM-PHS) control method is developed to enlarge ZVS operating range when the
voltage gain between DC bus and BA ports is greater than 1. The control objectives of three-port SR
BDC and there-phase interleaved BDC are to maintain the DC bus voltage and dc-link voltage stable
respectively. Finally, a prototype platform is built to verify the feasibility of the proposed topology.
The structure of this article is organized as followings: the topology of proposed converter is given
in Section 2. Operating principles are introduced in Section 3. Section 4 explains the variation of
ZVS region and the peak value of resonant current under varying voltage gain. Principles of the
proposed PWM-PHS control method are also introduced in Section 4. Finally, the experimental results
are presented in Section 5, while the conclusion is drawn in Section 6. The main contributions of this
paper are summarized below:
(1)
(2)
(3)
(4)
A new two-stage three-port isolated BDC topology is proposed to integrate SC and BA.
Methods to enlarge ZVS region and to reduce power circulation loss for three-port SR BDC under
varying port voltages are first investigated.
A front-end converter in SC channel is introduced to keep input of full bridge constant. For BA
channel, PWM-PHS control method is developed to improve the characteristics of the proposed
three-port BDC.
By adopting the two-stage structure, all switches of SC and DC bus ports have realized ZVS with
variable V SC . By applying the proposed PWM-PHS control method, two more switches of BA
port realize ZVS even under the worst input voltage condition of MBA = 1.15.
2. Proposed System
The overall structure of the proposed two-stage three-port BDC is shown in Figure 3. It contains
two parts: a three-port SR BDC and a three-phase interleaved BDC. Three-port SR BDC is presented to
maintain DC bus voltage stable and to control power transmission among three ports. The function
of three-phase interleaved BDC is converting the widely fluctuating super capacitor voltage V sc to
a constant voltage V dc-link .
2.1. Three-Port SR BDC
The three-port SR BDC is composed of a three-winding transformer, three full bridges and two SR
tanks formed by Cr1 , Lr1 and Cr2 , Lr2 respectively. The three-winding transformer provides electrical
Energies 2017, 10, 446
4 of 23
isolation among three ports. What’s more it has inherent bidirectional power flow characteristic,
since all power switches of three full bridges are MOSFETs. The converter works at a constant
switching frequency f s , which is above the resonant frequency of SR tanks. As a consequence, it works
Energies 2017, 10, 446
4 of 23
only in continuous current mode. Phase shift control method is implemented, the amount and direction
continuous
current
mode. Phase
is implemented,
theswitches
amount and
of full bridges
of transmitted
power are
controlled
byshift
thecontrol
phasemethod
shift angles.
All the
ofdirection
the three
transmitted power are controlled by the phase shift angles. All the switches of the three full bridges
work with 50% duty cycle.
work with 50% duty cycle.
Figure 3. Topology of the proposed HESS bidirectional DC/DC system.
Figure 3. Topology of the proposed HESS bidirectional DC/DC system.
Through theoretical analysis, the three-port SR BDC is shown to have the best operating
characteristics such as maximum ZVS operating region, reduced current stress and cutoff current
Through
theoretical
analysis,
the three-port
SR BDC
is shown
toa have
the best operating
only
under unity voltage
gain among
three ports. Whereas,
the voltage
of SC has
large fluctuation
range
withas
themaximum
change of residual
To solveregion,
the contradictions
of the
varyingstress
VSC and and
the best
characteristics
such
ZVSenergy.
operating
reduced
current
cutoff current
operating voltage gain restraint of SR BDC, a three-phase interleaved BDC is applied in the system.
only under unity voltage gain among three ports. Whereas, the voltage of SC has a large fluctuation
The interleaved BDC is used to convert the widely fluctuating SC voltage to a fixed voltage Vdc-link.
range with the
change
residual
energy.
To solve
contradictions
of theofvarying
Vthe
SC and the best
However,
theof
fluctuation
range
of battery
voltage the
is relatively
small, the method
converting
battery
voltage
to
a
fixed
voltage
by
increasing
a
BDC
converter
is
not
the
best
solution.
In
addition,
operating voltage gain restraint of SR BDC, a three-phase interleaved BDC is applied in the system.
a new PWM-PHS hybrid control strategy which has two phase-shift angles is proposed to improve
The interleaved
BDC is used to convert the widely fluctuating SC voltage to a fixed voltage V dc-link .
the operation characteristics of battery channel under a variation range of voltage gain. The proposed
However, the
fluctuation
range
ofthe
battery
is operating
relatively
small, the method of converting the
control method can
increase
number voltage
of MOSFETs
in ZVS.
The
features
of
the
three-port
SR
BDC
are:
battery voltage to a fixed voltage by increasing a BDC converter is not the best solution. In addition,
(1) Three-port
transformer
coupling
amount of power
switches,
increases to improve
a new PWM-PHS
hybridstructure
controlwith
strategy
which
has reduces
two phase-shift
angles
is proposed
power density. of battery channel under a variation range of voltage gain. The proposed
the operation characteristics
(2) Power flow between BA port and DC bus port, SC port and DC bus port are bidirectional.
control method
increase
themethod
number
of MOSFETs
operating
in ZVS.
(3) can
Centralized
control
of power
flow by changing
the direction
and magnitude of the phase
between three
is applied.
The featuresshift
of angles
the three-port
SRports
BDC
are:
(4) Three-phase interleaved BDC is introduced in the SC channel to keep voltage gain MSC = 1, which
(1)
(2)
(3)
(4)
(5)
bestwith
operating
characteristics
of SC channel
of SR BDC.
Three-portguarantee
structure
transformer
coupling
reduces
amount of power switches, increases
(5)
PWM-PHS
hybrid
control
strategy
is
proposed
for
the
BA
channel
to increase the number of
power density.
switches, which can achieve ZVS, under a variation voltage VBA.
Power flow between BA port and DC bus port, SC port and DC bus port are bidirectional.
2.2. Three-Phase
Centralized
control Interleaved
method BDC
of power flow by changing the direction and magnitude of the phase
three-phasethree
interleaved
is introduced to the SC channel of SR BDC to convert the widely
shift anglesAbetween
portsBDC
is applied.
fluctuating SC voltage VSC to a fixed voltage Vdc-link. The SC is connected to the low-voltage side, and
Three-phase
interleaved
is introduced
in energy
the SC
channel
keep
voltage
gain MSC = 1,
the SR BDC
is placed onBDC
the high-voltage
side. When
flows
from SC to
to the
SR BDC,
it works
which guarantee
best
of SC channel of SR BDC.
at boost mode,
and operating
conversely, itcharacteristics
works under buck mode.
non-isolated bidirectional buck/boost converter topology is adopted in this paper. In order to
PWM-PHSAhybrid
control strategy is proposed for the BA channel to increase the number of
achieve high efficiency and high power density, the converter is designed to operate in discontinuous
switches,
which
can
ZVS,
a variation
.
BAbuck/boost
conducting modeachieve
(DCM), such
thatunder
all the switches
realizevoltage
ZVS, andV
the
inductors are
minimized. However, the DCM also has the drawback of large current ripple. To reduce current
2.2. Three-Phase Interleaved BDC
A three-phase interleaved BDC is introduced to the SC channel of SR BDC to convert the widely
fluctuating SC voltage V SC to a fixed voltage V dc-link . The SC is connected to the low-voltage side,
and the SR BDC is placed on the high-voltage side. When energy flows from SC to the SR BDC,
it works at boost mode, and conversely, it works under buck mode.
A non-isolated bidirectional buck/boost converter topology is adopted in this paper. In order to
achieve high efficiency and high power density, the converter is designed to operate in discontinuous
Energies 2017, 10, 446
5 of 23
conducting mode (DCM), such that all the switches realize ZVS, and the buck/boost inductors are
minimized. However, the DCM also has the drawback of large current ripple. To reduce current
ripple, the interleaved multi-phase structure is introduced to reduce current ripple. All of the
interleaved channels adopt the same control strategy, while hold a phase shift of π/3 in driving
signal from each other. As a consequence, the inductor currents of three phases are shifted by π/3.
Hence, with interleaved inductor currents, the ripple current of SC is minimized. The features of the
Energies 2017, 10, 446
5 of 23
three-phase interleaved BDC are:
(1)
(2)
(3)
(4)
ripple, the interleaved multi-phase structure is introduced to reduce current ripple. All of the
The
structure
is simple,
and
it combines
a boost
with
a buck
converter
interleaved
channels
adopt the
same
control strategy,
whileconverter
hold a phasetogether
shift of π/3
in driving
signal
from eachin
other.
As a consequence, the inductor currents of three phases are shifted by π/3. Hence,
connected
antiparallel.
with interleaved
inductor currents,
current
of SC is current
minimized.
The features
of power
the threeThree-phase
interleaved
structurethe
is ripple
adopted
to reduce
ripple,
improve
level and
phase interleaved BDC are:
reduce current stress of the converter.
(1) Theunder
structure
is simple,
combines
boost converter
together with a buck converter
It works
DCM,
whichand
canitreduce
theainductance
value.
connected in antiparallel.
Two MOSFETs of one phase-leg conduct complementarily, and the inductor operates under DCM
(2) Three-phase interleaved structure is adopted to reduce current ripple, improve power level and
condition,
and
thusstress
ZVS of
ofthe
MOSFETs
reduce
current
converter.is achieved.
(3) It works under DCM, which can reduce the inductance value.
3. Operating
Analysis
(4) Two
MOSFETs of one phase-leg conduct complementarily, and the inductor operates under
DCM condition, and thus ZVS of MOSFETs is achieved.
In this section, operating principles of three-port SR BDC and three-phase interleaved BDC are
introduced
respectively.
For the three-port SR BDC, relationship between phase shift angle and power
3. Operating
Analysis
transmission is deduced. What’s more, ZVS soft-switching realizing region and current stress of the
In this section, operating principles of three-port SR BDC and three-phase interleaved BDC are
resonant
tank are respectively.
analyzed inFor
detail.
For three-phase
the phase
operating
principle
introduced
the three-port
SR BDC,interleaved
relationshipBDC,
between
shift angle
and as well
as the inductance
designing
method
is
introduced.
power transmission is deduced. What’s more, ZVS soft-switching realizing region and current stress
of the resonant tank are analyzed in detail. For three-phase interleaved BDC, the operating principle
3.1. Operating
Principle
of Three-Port
SRmethod
BDC is introduced.
as well as
the inductance
designing
The
three-port
SR BDC
shown in Figure 4. It is composed of three full bridges,
3.1.proposed
Operating Principle
of Three-Port
SR is
BDC
a three-winding transformer, two SR tanks formed by Cr1 and Lr1 , Cr2 and Lr2 , and filter capacitors
The proposed three-port SR BDC is shown in Figure 4. It is composed of three full bridges, a
Cf1 –Cf3 . Port 1 is connected to SC through a three-phase interleaved BDC, port 2 is and port 3 are
three-winding transformer, two SR tanks formed by Cr1 and Lr1, Cr2 and Lr2, and filter capacitors Cf1–
BA portCf3and
respectively.
Phase
shift method
is applied
among
three
to port
control the
. PortDC
1 is bus
connected
to SC through
a three-phase
interleaved
BDC, port
2 is and
portports
3 are BA
direction
and
magnitude
of
the
power
transmission,
all
the
switches
of
the
converter
are
driven
and DC bus respectively. Phase shift method is applied among three ports to control the direction at 50%
and magnitude
the power
transmission,
all constant
the switches
at 50% duty
duty cycle.
Since the of
voltage
of three
ports are
dc,ofVthe
V T2 and are
V T3driven
are square-waves
with
T1 , converter
cycle.ofSince
the voltage
of and
three±ports
constant dc,
T1, VT2 and VT3 are square-waves with
amplitudes
±V dc-link
, ±V BA
V bus are
respectively.
InVthe
subsequent analysis, phase shift angles
amplitudes of ±Vdc-link, ±VBA and ±Vbus respectively. In the subsequent analysis, phase shift angles of
of SC and BA ports are defined as ϕ1 and ϕ2 , which are shown in Figure 4. They control the phase
SC and BA ports are defined as φ1 and φ2, which are shown in Figure 4. They control the phase shift
shift between
outputsofofthe
theactive
active
bridges.
phase
ϕ1φ2and
2 are considered
betweenthe
thesquare-wave
square-wave outputs
bridges.
TheThe
phase
shiftsshifts
φ1 and
are ϕ
considered
positivepositive
if V T1 ifand
V
lead
V
,
and
conversely,
ϕ
and
ϕ
are
considered
negative.
T2 VT2 lead T3
1 φ2 are2considered negative.
VT1 and
VT3, and conversely, φ1 and
Figure
Structure of
of the
SRSR
BDC.
Figure
4. 4.Structure
thethree-port
three-port
BDC.
3.1.1. Operating Mode Analysis
Energies 2017, 10, 446
6 of 23
3.1.1. Operating Mode Analysis
The operating principles when both SC and BA ports are providing energy to DC bus port are
Energies 2017, 10, 446
6 of 23
analyzed. In this condition both ϕ1 and ϕ2 are positive. The theoretical waveforms, when ϕ1 > ϕ2 > 0,
The operating
principles when both SC and BA ports are providing energy to DC bus port are
are shown in Figure
5.
analyzed. In this condition both φ1 and φ2 are positive. The theoretical waveforms, when φ1 > φ2 > 0,
There are
different
in one switching cycle. Dead time is considered in the analysis,
are 18
shown
in Figureintervals
5.
however, the charging
discharging
intervals
of snubber
are very
There areand
18 different
intervals in
one switching
cycle. Deadcapacitors
time is considered
in thesmall,
analysis,and they can
however,
the
charging
and
discharging
intervals
of
snubber
capacitors
are
very
small,
and
they can
be neglected.
be neglected.
Figure 5. Theoretical waveforms of the three-port SR BDC.
Figure 5. Theoretical waveforms of the three-port SR BDC.
Interval 1 (t0–t1): S1 and S4, S5 and S8 are on. This interval is dead time of port 3 and all the switches
of port 3 are off. Since i3 is positive, i3 flows through the anti-parallel diodes of S9 and S12. i1 flows
Intervalthrough
1 (t0 –tS11and
): SS14, and
S4 , Sthrough
are
on. This interval is dead time of port 3 and all the
5 and SS5 8and
and i2 flows
S8. This interval ends at t1, when S9 and S12 are turned on.
switches of portInterval
3 are off.
i3 is
flows
the anti-parallel
diodestoof S9 and S12 .
2 (t1–tSince
2): S1 and
S4, positive,
S5 and S8, S9i3and
S12 arethrough
on. This interval
ends when i2 increases
zero. The
anti-parallel
diodes
of S9 and
S12 conduct
prior S
to the
maininterval
switches, ends
thus, S9at
and
12 are
i1 flows through
S1 and
S4 , and
i2 flows
through
S5 and
.
This
t1 ,Swhen
S9 and S12
8
turned on with ZVS. The operating characteristics of port 1 and 2 are exactly same with interval 1.
are turned on. Interval 3 (t2–t3): This interval begins at t2 when i2 increases to zero, and it ends when switches
IntervalS21 and
(t1 –t
): turned
S1 and
S8 , S9 Sand
This
interval
ends
when
S4 2are
off.SDuring
this interval,
1 and S
S412
of are
port on.
1, S5 and
S8 of
port 2 and
S9 as well
as Si122 increases to
4 , S5 and
of port 3 are on.diodes
i1, i2 and iof
3 are positive and flow through S1 and S4, S5 and S8, and S9 and S12 respectively.
zero. The anti-parallel
S9 and S12 conduct prior to the main switches, thus, S9 and S12 are
Interval 4 (t3–t4): This interval is dead time of port 1 and all the switches of port 1 are off. i1 is
turned on with
ZVS.soThe
operating
characteristics
ofofport
1 and
2 arethis
exactly
positive,
i1 flows
through the
anti-parallel diodes
S2 and
S3. During
interval,same
i2 and with
i3 flowinterval 1.
Intervalthrough
3 (t2 –tS35):and
This
interval
at t2 This
when
i2 increases
zero,
and
it ends
S8, and
S9 and Sbegins
12 respectively.
interval
ends when to
S2 and
S3 are
turned
on. when switches
Intervaloff.
5 (t4During
–t5): At t4, Sthis
2 and S3 are turned on, and this interval ends when S5 and S8 are turned
S1 and S4 are turned
interval, S1 and S4 of port 1, S5 and S8 of port 2 and S9 as well
off. Since the anti-parallel diodes conduct before main switches of S2 and S3, S2 and S3 are turned on
as S12 of portwith
3 are
on.
i
,
i
and
i
are
positive
through
1
2
3
1 and4.S4 , S5 and S8 , and S9 and
ZVS. The operating characteristics
of port 2and
and 3flow
are identical
withSinterval
S12 respectively. Interval 6 (t5–t6): At t5, switches S5 and S8 are turned off, this interval ends when i1 decreases to zero.
is dead time of port 2 and all the switches of port 2 are off. i2 is positive, hence i2 flows
IntervalThis
4 (tinterval
3 –t4 ): This interval is dead time of port 1 and all the switches of port 1 are off. i1 is
through the anti-parallel diodes of S6 and S7. i1 and i3 flow through S2 and S3, and S9 and S12 respectively.
positive, so i1 flows
through
anti-parallel
S2 andtoSzero,
this
interval,
3 . During
Interval
7 (t6–t7): the
This interval
begins atdiodes
t6 when iof
1 decreases
and it ends
when
S6 and Si72 and i3 flow
through S5 and
S8 , and
S12 respectively.
when
turned on.
are turned
on. S
The
difference
between intervalThis
7 and interval
6 is that theends
direction
of i1 S
changes.
2 still
flows
9 and
2 and iS
3 are
anti-parallel diodes of S6 and S7.
Intervalthrough
5 (t4 –tthe
5 ): At t4 , S2 and S3 are turned on, and this interval ends when S5 and S8 are turned
off. Since the anti-parallel diodes conduct before main switches of S2 and S3 , S2 and S3 are turned on
with ZVS. The operating characteristics of port 2 and 3 are identical with interval 4.
Interval 6 (t5 –t6 ): At t5 , switches S5 and S8 are turned off, this interval ends when i1 decreases
to zero. This interval is dead time of port 2 and all the switches of port 2 are off. i2 is positive, hence
i2 flows through the anti-parallel diodes of S6 and S7 . i1 and i3 flow through S2 and S3 , and S9 and
S12 respectively.
Interval 7 (t6 –t7 ): This interval begins at t6 when i1 decreases to zero, and it ends when S6 and S7
are turned on. The difference between interval 7 and 6 is that the direction of i1 changes. i2 still flows
through the anti-parallel diodes of S6 and S7 .
Energies 2017, 10, 446
7 of 23
Interval 8 (t7 –t8 ): At t7 , S6 and S7 are turned on, and this interval ends when i3 decreases to zero.
The anti-parallel diodes conduct ahead the main switches of S6 and S7 , therefore, S6 and S7 are turned
on with ZVS. The operating characteristics of port 1 and 3 are exactly same with interval 7.
Interval 9 (t8 –t9 ): This interval begins at t8 when i3 decreases to zero, and it ends when S9 and S12
are turned off. The difference between interval 9 and 8 is that the direction of i3 changes. The operating
characteristics of port 1 and 2 are exactly the same with interval 8.
Interval 10 (t9 –t10 ): This interval is dead time of port 3. Because i3 is negative, so i3 flows through
the anti-parallel diodes of S10 and S11 . During this interval, i1 and i2 flow through S2 and S3 , and S6
and S7 respectively. This interval ends when S10 and S11 are turned on.
7 of 23 i2 decreases
IntervalEnergies
11 (t2017,
): At t10 , S10 and S11 are turned on, and this interval ends when
10 –t10,
11446
to zero. The anti-parallel diodes conduct before main switches of S10 and S11 , so that S10 and S11 are
Interval 8 (t7–t8): At t7, S6 and S7 are turned on, and this interval ends when i3 decreases to zero.
turned on with
The diodes
operating
characteristics
of port
are exactly
same
The ZVS.
anti-parallel
conduct
ahead the main switches
of 1
S6 and
and S2
7, therefore,
S6 and
S7 are with
turnedinterval 10.
operating
characteristics
1 and 3 iare
exactly
same
with
interval
7.
Intervalon
12with
(t11ZVS.
–t12The
): This
interval
begins of
atport
t8 when
decreases
to
zero,
and
it
ends
when S2 and
2
Interval 9 (t8–t9): This interval begins at t8 when i3 decreases to zero, and it ends when S9 and S12
S3 are turnedareoff.
The difference between interval 12 and 11 is that the direction of i2 changes.
turned off. The difference between interval 9 and 8 is that the direction of i3 changes. The operating
Intervalcharacteristics
13 (t12 –t13 ):of This
is dead
timewith
of port
1. 8.During this interval, i1 is negative, so i1
port 1 interval
and 2 are exactly
the same
interval
Interval
10
(t
9
–t
10
):
This
interval
is
dead
time
of
port
3.
Because
i3 isthrough
negative, so
through
flows through the anti-parallel diodes of S1 and S4 . i2 and i3 flow
S6i3 flows
and S
7 , and S10 and S11
the anti-parallel diodes of S10 and S11. During this interval, i1 and i2 flow through S2 and S3, and S6 and
respectively. SThis
interval
ends
when
S
and
S
are
turned
on.
1
4
7 respectively. This interval ends when S10 and S11 are turned on.
Interval 14 Interval
(t13 –t1411):(tAt
t13
, St110,and
S4Sare
onand
and
interval
ends
at t14 when
S6 and S7
10–t11
): At
S10 and
11 areturned
turned on,
thisthis
interval
ends when
i2 decreases
to
zero.
The
anti-parallel
diodes
conduct
before
main
switches
of
S
10
and
S
11
,
so
that
S
10
and
S
11
are
turned
are turned off. The anti-parallel diodes conduct prior to the main switches of S1 and S4 , so S1 and S4
on with ZVS. The operating characteristics of port 1 and 2 are exactly same with interval 10.
are turned on with
ZVS. The operating characteristics of port 2 and 3 are exactly same with interval 13.
Interval 12 (t11–t12): This interval begins at t8 when i2 decreases to zero, and it ends when S2 and
IntervalS15
(tturned
): This
intervalbetween
is dead
time 12
ofand
port
2.that
During
this interval,
i2 is negative, thus i2
3 are
The difference
interval
11 is
the direction
of i2 changes.
14 –t15off.
Interval
13 (t12–t13): This
interval
1. During
interval, iS
1 is and
i1 S10 and S11
flows through the
anti-parallel
diodes
of isS5dead
andtime
S8 .ofi1port
and
i3 flowthis
through
S4 , so
and
1 negative,
flows through the anti-parallel diodes of S1 and S4. i2 and i3 flow through S6 and S7, and S10 and S11
respectively. respectively.
This interval
ends at t15when
when
i1 increases
to zero.
This interval ends
S1 and
S4 are turned on.
Interval 16 (t
): (tThis
begins
t15 when
i1 increases
toatzero
andS6ends
S5 and S8
Interval
13–t14):interval
At t13, S1 and
S4 are at
turned
on and this
interval ends
t14 when
and S7 when
are
15 –t1614
turned
off.interval
The anti-parallel
prior
to the
of S1 and
S4, so S1 interval
and S4 are 16 and 15 is
are turned on.
This
is stilldiodes
deadconduct
time of
port
2.main
Theswitches
difference
between
turned on with ZVS. The operating characteristics of port 2 and 3 are exactly same with interval 13.
that the directionInterval
of i1 15
changes.
(t14–t15): This interval is dead time of port 2. During this interval, i2 is negative, thus i2
Intervalflows
17 (tthrough
interval
begins
at t16
S8 are
turned
andS11ends when i3
theThis
anti-parallel
diodes
of S5 and
S8. when
i1 and i3 S
flow
through
S1 and
S4, andon,
S10 and
16 –t17 ):
5 and
This interval
ends at t15 whendiodes
i1 increases
to zero. prior to the main switches of S and S ,
increases to respectively.
zero. Because
the anti-parallel
conduct
5
8
Interval 16 (t15–t16): This interval begins at t15 when i1 increases to zero and ends when S5 and S8
so S5 and S8 are
areturned
turned
on
with
ZVS.
The
operating
characteristics
of
port
1
and
3
are
exactly
same
on. This interval is still dead time of port 2. The difference between interval 16 and 15 is
with intervalthat
16.the direction of i1 changes.
16–t17):interval
This interval
beginsatattt16 when
S5 and S8 are turned on, and ends when i3
Interval 18 Interval
(t17 –t1817): (tThis
begins
17 when i3 increases to zero, and ends when S10 and
increases to zero. Because the anti-parallel diodes conduct prior to the main switches of S5 and S8, so
S11 are turned
off. The difference between interval 18 and 17 is that the direction of i changes.
S5 and S8 are turned on with ZVS. The operating characteristics of port 1 and 3 are exactly same3with
interval 16.
3.1.2. Analysis for
Voltage
Interval
18 (t17Source
–t18): ThisLoad
interval begins at t17 when i3 increases to zero, and ends when S10 and
S11 are turned off. The difference between interval 18 and 17 is that the direction of i3 changes.
This section analyzes the relationship between phase shift angle and power transmission,
3.1.2. Analysis
for Voltage
Source Load
ZVS soft-switching
realizing
condition
and peak current of the resonant tank under a given voltage
This section analyzes the relationship between phase shift angle and power transmission, ZVS softsource load.
switching realizing condition and peak current of the resonant tank under a given voltage source load.
The equivalent
circuits of the three-port SR BDC are shown in Figure 6. In Figure 6a the output of
The equivalent circuits of the three-port SR BDC are shown in Figure 6. In Figure 6a the output
three active bridges
are bridges
represented
by square
waves
V T1
and
and in Figure 6b
T2and
T3 respectively,
of three active
are represented
by square
waves
VT1,, V
VT2
VT3V
respectively,
and in Figure
T3 of port 3 is transferred
port 1port
and port
2 according to
to the
ratio. ratio.
V T3 of port 36bisVtransferred
to port 1toand
2 according
thetransformer
transformer
(a)
(b)
Figure 6. Equivalent circuits for analysis: (a) equivalent circuit of three-port SR BDC; (b) transformer
Figure 6. Equivalent
circuits for analysis: (a) equivalent circuit of three-port SR BDC; (b) transformer
equivalent model.
equivalent model.
Energies 2017, 10, 446
8 of 23
In the proposed three-port SR BDC, Lr1 = Lr2 = Lr , Cr1 = Cr2 = Cr , and the resonant frequency of SR
tanks are f r . The operating frequency of three ports is f s , which is greater than f r , and the corresponding
angular velocity is ω s . Then the impedance value of two resonant tanks can be given by:
X = ω s Lr −
1
ωs Cr
(1)
The Fundamental Harmonics Approximation (FHA) method is a commonly used approach for
steady-state analysis in resonant-type converters. And the accuracy level of the results obtained from
FHA is acceptable for our work. To simplify the analysis procedure, all harmonics except fundamental
component of all voltages and currents are neglected. V T1,1 , V T2,1 and V T3,1 are the fundamental
components of square waves V T1 , V T2 and V T3 , and phase shift angles between port 1 and port 3,
port 2 and port 3 are ϕ1 and ϕ2 respectively. Using the Fourier series, V T1,1 , V T2,1 and V T3,1 are shown
as follows:
4Vdc-link
(2)
sin(ωs t + ϕ1 )
VT1,1 =
π
4VBA
VT2,1 =
sin(ωs t + ϕ2 )
(3)
π
4Vbus
VT3,1 =
sin ωs t
(4)
π
The variables MSC and MBA are defined as the voltage gain between port 1 and port 3, port 2 and
port 3 respectively. They are given by (5) and (6):
MSC =
n13 Vbus
Vdc-link
(5)
MBA =
n23 Vbus
VBA
(6)
Resonant currents of three ports can be obtained as follows:
i1 ( t ) =
h
i
VT1,1 − n13 VT3,1
◦
◦
4V
= dc-link sin(ωs t + ϕ1 − 90 ) − MSC sin(ωs t − 90 )
jX
πX
(7)
i
VT2,1 − n23 VT3,1
◦
◦
4V h
= BA sin(ωs t + ϕ2 − 90 ) − MBA sin(ωs t − 90 )
jX
πX
(8)
i2 ( t ) =
i3 (t) = n13 i1 (t) + n23 i2 (t)
(9)
Switches in port 1 and port 2 can realize ZVS only when the resonant tank currents lag their
applied square wave voltages. While for port 3, the defined positive current direction is contrary to
port 1 and 2, the condition for ZVS realization is that the resonant current leads its applied square
wave voltage. Then the constraint conditions for ZVS of port 1–3 can be given by (10)–(12) respectively:
ϕ 4Vdc-link
i1 − 1 =
( MSC cos ϕ1 − 1) < 0
t
πX
ϕ 4V
2
i2 −
= BA ( MBA cos ϕ2 − 1) < 0
t
πX
4V
4V
i3 (0) = n13 dc-link ( MSC − cos ϕ1 ) + n23 BA ( MBA − cos ϕ2 ) > 0
πX
πX
(10)
(11)
(12)
By calculating the maximum value of i1 (t) and i2 (t), the peak current of two resonant tanks can be
derived as:
q
4Vdc-link
i1max =
1 + MSC 2 − 2MSC cos ϕ1
(13)
πX
Energies 2017, 10, 446
9 of 23
i2max =
4VBA
πX
q
1 + MBA 2 − 2MBA cos ϕ2
(14)
The transferred power from SC and BA ports to the bus port can be calculated as follows:
P1 =
1
2π
P2 =
Z 2π
0
1
2π
VT1 (t)·i1 (t)d(ωs t) =
Z 2π
0
8Vdc-link 2 MSC
sin ϕ1
π2 X
(15)
8VBA 2 MBA
sin ϕ2
π2 X
(16)
VT2 (t)·i2 (t)d(ωs t) =
Equations (15) and (16) indicate that the power transferred from SC and BA ports to the DC
bus port are proportional to the sinusoidal values of ϕ1 and ϕ2 respectively. It is obviously that the
power transmission is positive when ϕ1 and ϕ2 values are positive, and conversely the power flow
is negative.
3.1.3. Analysis for Resistive Load
This section explains the relationship of voltage gain, power transmission and phase shift angles
under a resistive load. If the DC bus port is connected to a pure resistive load, the output voltage
V bus needs to be derived. According to superposition theorem, in the three-port SR BDC with linear
resistive load, the output voltage V bus can be divided into two parts: V busSC and V busBA . V busSC and
V busBA are output voltage values when only one of the two inputs works alone. MbusSC and MbusBA
are the corresponding voltage gain, and are given by:
MbusSC =
n13 VbusSC
Vdc-link
(17)
MbusBA =
n23 VbusBA
VBA
(18)
Under specific output voltage value and phase shift angles conditions, the transferred power
is given in (15) and (16), no matter what kind of load is connected to the DC bus port. If the load
resistance is defined as RL . Combing (15) and (16), the output power P1 and P2 , when V dc-link and V BA
work alone, can be given by:
P1 =
2
VbusSC 2
8V
M
= dc-link2 busSC sin ϕ1
RL
π X
(19)
VbusBA 2
8V 2 M
= BA 2 busBA sin ϕ2
RL
π X
(20)
P2 =
By combing (17)–(20), the voltage gain MbusSC and MbusBA can be given as follows:
MbusSC =
8n13 2 RL
sin ϕ1
π2 X
(21)
MbusBA =
8n23 2 RL
sin ϕ2
π2 X
(22)
According to the superposition theorem, the output voltage V bus with resistive RL can be given by:
Vbus =
8n13 RL
8n23 RL
sin ϕ1 Vdc-link +
sin ϕ2 VBA
π2 X
π2 X
(23)
3.2. Operating Principle of Three-Phase Interleaved BDC
The operating principles of the three-phase interleaved BDC are analyzed in this section.
The proposed three-phase interleaved BDC is shown in Figure 7. When power transfers from SC
8n R
8n R
Vbus = 8n 132R L sin ϕ1Vdc-link +8n 232R L sin ϕ2 VBA
(23)
13
L
π
X
XLL sin ϕ2 VBA
R
Vbus = 8n132 RL sin ϕ1Vdc-link + 8nπ23
(23)
23
Vbus = π 2X sin ϕ1Vdc-link + π 22X sin ϕ2 VBA
(23)
π X
π X
3.2. Operating Principle of Three-Phase Interleaved BDC
3.2.
Operating
of Three-Phase Interleaved BDC
Energies
2017, 10, Principle
446
10 of 23
3.2. Operating
Principle
of Three-Phase
BDC
The operating
principles
of theInterleaved
three-phase
interleaved BDC are analyzed in this section. The
The operating
principles
of the
three-phase
arepower
analyzed
in this
section.
proposed
three-phase
interleaved
BDC
is showninterleaved
in Figure 7.BDC
When
transfers
from
SC toThe
the
The operating
principles
of the
three-phase
interleaved
BDC
are analyzed
in this
section.
The
proposed
three-phase
interleaved
BDC
is
shown
in
Figure
7.
When
power
transfers
from
SC
to the
dc-link,
it
works
under
boost
mode
and
switches
Q
D1
–Q
D3
are
main
switches.
If
direction
of
power
to
the
dc-link,
it
works
under
boost
mode
and
switches
Q
–Q
are
main
switches.
If
direction
of
D1
D3
proposed three-phase interleaved BDC is shown in Figure 7. When power transfers from SC to the
dc-link,
itisworks
under
boost
mode
and
switches
QD1mode
–Q
D3 are main switches. If direction of power
transfer
reversed,
the
BDC
works
under
buck
mode
and
switches
Q
U1
–Q
U3
are
main
switches.
L
1–
power
transfer
is
reversed,
the
BDC
works
under
buck
and
switches
Q
–Q
are
main
switches.
U1 IfU3direction of power
dc-link, it works under boost mode and switches QD1–QD3 are main switches.
transfer
is
reversed,
the
BDC
works
under
buck
mode
and
switches
Q
U1
–Q
U3
are
main
switches.
L
1
–
are
buck/boost
C1 Cand
Cf1Care
filter
capacitors.
By
three-phase
interleaving
LL13–L
inductors,
are
filter
capacitors.
Byadopting
adopting
three-phase
interleaving
3 are
1 and
f1 buck
transfer
isbuck/boost
reversed,inductors,
the
BDC works
under
mode
and switches
QU1–QU3
are main switches.
L 1–
Lstructure,
3 are buck/boost inductors, C1 and Cf1 are filter capacitors. By adopting three-phase interleaving
of
and
required
filter
capacitance
cancan
be
current ripple
ripple
of SC
SC
can
beminimized
minimized
andthus
thus
the
required
filter
capacitance
Lstructure,
3 are buck/boost
inductors,
Cport
1port
andcan
Cf1be
are
filter capacitors.
Bythe
adopting
three-phase
interleaving
structure,
current ripple of SC port can be minimized and thus the required filter capacitance can be
reduced.
be
reduced.
structure, current ripple of SC port can be minimized and thus the required filter capacitance can be
reduced.
reduced.
Figure 7. Circuit diagram of the proposed three-phase interleaved BDC.
Figure 7. Circuit diagram of the proposed three-phase interleaved BDC.
Figure 7. Circuit diagram of the proposed three-phase interleaved BDC.
Figure 7. Circuit diagram of the proposed three-phase interleaved BDC.
For the proposed three-phase interleaved BDC, switches of one phase leg conduct
For the
the proposed
proposed
three-phase
interleaved
BDC, switches
switches
of one
one
phase leg
leg conduct
conduct
For
interleaved
BDC,
of
phase
complementarily,
and thethree-phase
inductor current
can go through
from positive
to negative
raise
For the proposed
three-phase
interleaved
BDC, switches
of one
phase and
leg then
conduct
complementarily,
and
the
inductor
current
can
go
through
from
positive
to
negative
and
then
raise
to
complementarily,
andensure
the inductor
current can
go through
from
positive to negative and then
raise
to
positive.
This
will
all
the
switches
realize
ZVS
turn
on.
complementarily, and the inductor current can go through from positive to negative and then raise
positive.
will
ensure
allall
thethe
switches
realize
ZVS
turn
on.
to
positive.
This
will
ensure
switches
realize
ZVS
turn
on. strategy, but hold a phase shift of
The This
three-phase
interleaved
same
control
to positive.
This will ensure
all thechannels
switchesadopt
realizethe
ZVS
turn
on.
The
three-phase
interleaved
channels
adopt
the
same
control
strategy,
but hold
hold aa phase
phase
shift
of
The
three-phase
interleaved
channels
adopt
the
same
control
strategy,
but
of
π/3 in
driving
signal.
In
order
to
simplify
the
analysis,
the
operating
characteristics
singleshift
phase
The three-phase interleaved channels adopt the same control strategy,
but hold aofphase
shift
of
π/3
in
driving
signal.
In
order
to
simplify
the
analysis,
the
operating
characteristics
of
single
phase
π/3
driving signal.
In diagram
order to simplify
analysis,
the operating
of single
phase
are in
introduced.
Circuit
of singlethe
phase
is shown
in Figure characteristics
8, and theoretical
waveforms
π/3
in
driving signal.
In order to simplify
the
analysis,
the operating
characteristics
of single
phase
are
introduced.
Circuit
diagram
of
single
phase
is
shown
in
Figure
8,
and
theoretical
waveforms
under
are
introduced.
Circuit
diagram
of
single
phase
is
shown
in
Figure
8,
and
theoretical
waveforms
under
boost
mode
are
shown
in
Figure
9.
are introduced. Circuit diagram of single phase is shown in Figure 8, and theoretical waveforms
boost mode
shown
in Figure
9.
under
boost are
mode
are shown
in Figure
9.
under boost mode are shown in Figure 9.
Figure 8. Circuit diagram of single phase.
Figure
8.
Figure
8. Circuit
Circuit diagram
diagram of
of single
single phase.
phase.
Figure 8.
Circuit
diagram
of
single
phase.
Figure 9. Theoretical waveforms of single phase under boost mode.
Figure
Figure 9.
9. Theoretical
Theoretical waveforms
waveforms of
of single
single phase
phase under
under boost
boost mode.
mode.
Figure
9.
Theoretical
waveforms
of
single
phase
under
boost
mode.
The parameters are defined as follows: V SC and V dc-link are the voltage of SC and dc-link; iL and
vL are voltage and current of the buck/boost inductor L; imax and imin are the maximum and minimum
value of iL respectively; ∆i is the variation of iL during one switching cycle; iSC is the current of SC. tdb is
dead band time; Ts is switching period; tD and tU are the conducting time of QU and QD separately.
Energies 2017, 10, 446
11 of 23
For single-phase BDC, there are four different intervals in one switching cycle. Same as the above
analysis of three-port SR BDC, dead time is considered, while charging and discharging intervals of
snubber capacitors are neglected.
Interval 1 (t0 –t1 ): This interval is dead band time, both QU and QD are off, and it ends when QD
is turned on. During this interval, iL < 0 and it flows through the anti-parallel diode of QD . If the
conduction voltage drop of anti-parallel diode is neglected, vL = V SC and iL increases linearly.
Interval 2 (t1 –t2 ): During this interval, QD is on and QU is off, iL flows through QD . Since the
anti-parallel diodes conduct prior to the main switches of QD , thus it is turned on with ZVS. Same as
interval 1, iL increases linearly.
Interval 3 (t2 –t3 ): This interval is also dead band time, both QU and QD are off, and it ends
when QU is turned on. Different from interval 1, during this interval iL > 0, so it flows through the
anti-parallel diode of QU . vL = V SC − V dc-link and this value is less than zero, so iL decreases linearly.
Interval 4 (t3 –t4 ): During this interval, QU is on and QD is off. iL flows through QU . Same as
interval 3, iL decreases linearly. Since the anti-parallel diodes conduct before main switches of QU , it is
turned on with ZVS.
Compared to tD and tU , tdb can be ignored, so ∆i can be derived as follows:
∆i =
VSC Vdc-link − VSC
· TS
·
L
Vdc-link
(24)
To maintain ZVS switching of QU and QD , it must be ensured that imax > 0 and imin < 0.
4. ZVS Region Analysis and Proposed Method for Expanding ZVS Realization Range
Since the transformer voltage of port 3 is clamped by the output voltage V bus , so there is no
direct energy interaction between port 1 and port 2. Thus, the three-port SR BDC can be decomposed
into two single input SR BDCs. The ZVS realization and current stress of single channel SR BDC can
provide reference for the three-port SR BDC. To simplify the analysis, the ZVS realization region and
current stress of single channel SR BDC are analyzed in this section.
4.1. ZVS Region and Current Stress Analysis of Single Channel SR BDC
Through (10)–(12), the ZVS constraint conditions for primary-side and secondary-side can be
simplified as follows:
Primary-side : M cos ϕ − 1 < 0
(25)
Secondary-side : M − cos ϕ > 0
(26)
The ZVS regions of primary and secondary sides of single channel SR BDC are shown in
Figure 10a,b, respectively. Figure 10a shows that when M < 1 all switches of primary side can
realize ZVS, while as shown in Figure 10b, switches of secondary side can only realize ZVS when ϕ is
greater than a certain value. When M > 1 situations are just contrary to situations when M < 1. It can
be obtained that, the ZVS realization regions of primary and secondary sides change reversely under
varying M. So during the design process, M should be as close to 1 as possible, and M = 1 is the best
choice to achieve ZVS for all the switches of primary and secondary sides.
Energies 2017, 10, 446
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Energies 2017, 10, 446
12 of 23
12 of 23
12 of 23
(a)
(a)
(b)
(b)
Figure 10. ZVS range of single channel SR BDC versus phase shift angel φ under different M: (a)
primary
side;
(b)range
secondary
side.channel SR BDC versus phase shift angel φ under different M: (a)
Figure 10.
ZVS
of single
Figure 10. ZVS range of single channel SR BDC versus phase shift angel ϕ under different M: (a) primary
primary side; (b) secondary side.
side; (b) secondary side.
Before analyzing the peak value of resonant current under varying M, it must be noticed that
analyzing
the peak
value
of resonant
currentMunder
varyingIf M,
must bethat
noticed
that
phaseBefore
shift angles
to transfer
same
power
under different
are varying.
we itsuppose
the phase
Before
analyzing
the peak
value
of resonant
currentM
under
varyingIfM,
itsuppose
must bethat
noticed
that
phase
shift angles
to transfer
same
power
different
are varying.
weto
thepower
phase
shift
angle
under unity
voltage
gain
(M =under
1) is φ,
and the phase
shift angel
transfer same
phase
shift angles
to
transfer
same
power
M are varying.
If weto
suppose
that
the power
phase
shift angle
under
unity
voltage
gain
(Mbetween
=under
1) is different
φ,
angel
transfer
same
under
varying
M is
α. The
relationship
φ and αthe
is phase
shownshift
in (27)
and (28).
It is shown
in (13)
shift
angle
under
voltage
gain (Mresonant
= 1) is ϕ,φ
and
shift
angel
to(28).
transfer
same
under
varying
M unity
is
α. The
relationship
between
and the
α is phase
shown
in (27)
and
It isthe
shown
in
(13)
and
(14)
that
with
certain
input
voltage,
parameters
and switching
frequency,
peakpower
value
under
varying
M
is
α.
The
relationship
between
ϕ
and
α
is
shown
in
(27)
and
(28).
It
is
shown
in
and
(14) thatcurrent
with certain
inputproportional
voltage, resonant
parameters
and switching
frequency,
peak
value
of
resonant
is directly
to N which
is shown
in (29). The
diagramsthe
of N
under
M
(13)
and
(14)
that
with
certain
input
voltage,
resonant
parameters
and
switching
frequency,
the
peak
is directly
proportional
to N which is shown in (29). The diagrams of N under M
<of1resonant
and M > current
1 are shown
in Figure
11a,b, respectively:
value
ofM
resonant
currentinisFigure
directly
proportional
to N which is shown in (29). The diagrams of N
< 1 and
> 1 are shown
11a,b,
respectively:
Vdc-link 2 11a,b, respectively:
8Vdc-link 2 M
under M < 1 and M > 1 are shown in8Figure
(27)
sin α
2 sin ϕ =
2
2
8Vπdc-link
X sin ϕ = 8Vdc-link
π 2X M
(27)
α
sin
2
2
2
8Vdc-link
X M sin α
π 2 X sin ϕ = 8Vπdc-link
(27)
sin2ϕ
π2 X
α = arcsin π X
(28)
sin
Mϕ
α = arcsin sin ϕ
(28)
α =4Varcsin M
(28)
M
dc-link
×N
imax =
4V
πdc-link
X
(29)
4V
dc-link
×× N
imax
= πX
imax=
√
2
(29)
π
X
(29)
M cos
+M
N N== 11+
M22 −−22M
cosαα
N = 1 + M − 2 M cos α
(a)
(a)
(b)
(b)
Figure 11. Peak current of single channel SR BDC versus phase shift angel φ under different M:
Figure 11. Peak current of single channel SR BDC versus phase shift angel ϕ under different M:
(a)
M < 1;
(b)
M > 1.
Figure
11.(b)
Peak
of single channel SR BDC versus phase shift angel φ under different M:
(a)
M < 1;
M >current
1.
(a) M < 1; (b) M > 1.
Figure 11 shows that, when M < 1, the peak current of resonant tanks increases with the decreases
11
that,
when
M
1,
the
peak
current
of resonant
resonant
tankswith
increases
with
Figure
11 shows
shows
that,
when
M << 1,
of
tanks
increases
with the
the decreases
decreases
of MFigure
in a large
range.
While
when
Mthe
> 1,peak
the current
peak current
increases
the increases
of
M in a
of
M
in
a
large
range.
While
when
M
>
1,
the
peak
current
increases
with
the
increases
of
M
in
a
certain
of M inrange.
a largeInrange.
Whileprocess,
when Mthe
> 1,
the peak
with
the increases
M intoa
certain
the design
phase
shift current
must beincreases
limited in
a relatively
smallofrange
range.
the
the phase
shift
must
bemust
limited
in apeak
relatively
small
range
torange
restrict
certain In
range.
In
the process,
design
process,
phase
shift
be limited
in
a relatively
small
to
restrict
cut
offdesign
current
of switches.
So,the
from
the
point
of
limiting
value
of
resonant
current,
M
restrict be
cutdesigned
off current
switches.
from the
point
value
of resonant
current,
M
should
as of
close
to 1 as So,
possible.
And
M = of
1 islimiting
the bestpeak
choice
to achieve
minimize
peak
should be designed as close to 1 as possible. And M = 1 is the best choice to achieve minimize peak
Energies 2017, 10, 446
13 of 23
switches. So, from the point of limiting peak value of resonant current, M should
13 of 23
be designed as close to 1 as possible. And M = 1 is the best choice to achieve minimize peak value
value
of resonant
current.
Through
the analysis
above,
SC and
BA should
be designed
to be
1
of resonant
current.
Through
the analysis
above,
both both
MSC M
and
MBAMshould
be designed
to be
1 to
to
achieve
best
operating
characteristics.
While
the voltages
ofand
SC and
BAall
are
allfixed
not fixed
To
achieve
best
operating
characteristics.
While
the voltages
of SC
BA are
not
value.value.
To solve
solve
this problem,
different
methods
forchannels
two channels
are proposed.
this problem,
different
methods
for two
are proposed.
cut off 2017,
current
of
Energies
10, 446
(1) For
For the
the SC
SCchannel,
channel, the
the voltage
voltage has
has aa large
large variation
variation range,
range, and
and can’t
can’t get
get an
an ideal
ideal operating
operating state
only
by
reasonable
parameters
design.
Therefore,
a
three-phase
interleaved
BDC
is introduced
only by reasonable parameters design. Therefore, a three-phase interleaved
between
betweenSC
SC and
and port
port 11 of
of the
the three-phase
three-phase SR
SR BDC.
BDC. The
The interleaved
interleaved BDC
BDC is used to convert the
widely
to
a
fixed
V
dc-link
,
and
thus
ensuring
M
SC
=
1.
widely fluctuating
fluctuating V
VSC
to
a
fixed
V
,
and
thus
ensuring
M
=
1.
SC
SC
dc-link
(2) Since
Since voltage
voltage variation
variation scale
scale is
is relatively
relatively small
small for
for the
the BA
BA channel,
channel, it is not essential to add BDC
converter
converter as
as SC
SCchannel
channel does.
does.AAnew
newPWM-PHS
PWM-PHScontrol
controlstrategy
strategyisisproposed
proposed for
forthe
theBA
BAchannel.
channel.
The
newly
proposed
control
method
has
two
phase
shift
angles
for
modulation,
and
can
increase
The newly proposed control method
two phase shift angles for modulation,
can increase
number
number of
of MOSFETs
MOSFETs which can realize ZVS.
4.2. Proposed PWM and Phase Shift Hybrid Control Strategy
The difference of the newly proposed PWM-PHS control strategy and the traditional phase shift
control method is that there are two phase-shift
phase-shift angles to modulate
modulate for
for the
the BA
BA channel.
channel. This can
provide more control flexibility,
flexibility, and
and can
can increase
increase the
the number
number of ZVS switches under a wide variation
VBA
Inthis
thismethod,
method,two
twoswitches
switchesinineach
eachphase
phaseleg
legalso
alsowork
workcomplementary
complementarywith
with50%
50%duty
dutycycle.
cycle.
of V
BA. .In
The two phase legs of BA port are defined as phase leg A and phase leg B, and corresponding phase
angles are
are represented
representedas
asφϕ
and
phase
angles
between
shift angles
2A2A
and
φ2Bϕrespectively.
TheThe
phase
shiftshift
angles
between
two two
legs legs
is δ,
2B respectively.
is2Bδ,= ϕφ2B
= δ.
ϕ2A
− δ. when
While,S5when
S5 and
or S8
S6 conduct
and S8 conduct
the instantaneous
φ
2A −
While,
and S7,
or S6S7,
and
together,together,
the instantaneous
value of value
VT2 is
◦ any more. The pulse width of the newly proposed
of V T2soisthe
zero,
so the
pulse
is not
zero,
pulse
width
of width
is not of
180°
any180
more.
The pulse width of the newly proposed control
◦
control method
(180so
− itδ) can
, so be
it can
be regarded
the combination
of PWM
and PHS
control.
method
is (180 −is δ)°,
regarded
as the as
combination
of PWM
and PHS
control.
The
The theoretical
waveforms
for the
channel
under
PWM-PHS
control
strategy
is shown
Figure
theoretical
waveforms
for the
BA BA
channel
under
PWM-PHS
control
strategy
is shown
in in
Figure
12.12.
Figure 12.
= 1.15.
1.15.
12. Theoretical waveforms for
for BA
BA channel
channel under
under PWM-PHS
PWM-PHS control
control method
method with
with M
MBA
BA =
The
fundamental components
components of
of square
square waves
waves V
VT2
T2 under
The fundamental
under PWM-PHS
PWM-PHS control
control method
method can
can be
be
shown
as
(30).
Referring
to
the
analysis
above,
the
resonant
current
and
power
transmission
value
shown as (30). Referring to the analysis above, the resonant current and power transmission value of
of
port
under PWM-PHS
PWM-PHS control
control method
method can
can be
be shown
shown as
as (31)
(31) and
and (32)
(32) respectively:
respectively:
port 22 under
2VBA
2V
sin
 )]
VT2,1
t + ϕ2A )) ++sin
ϕ2Bϕ)2B
VT2,1
= = BA
sin(ω
[sin
(ω(ω
(ωsts+t +
s ts+ ϕ2A
ππ
(30)
(30)
i
◦
◦
2V 2hVBA
° ◦
°
= sin(ωsin(
+ ϕ−
− 90° )+ sin(ω t + ϕ2B2B−−
ωsϕt 2A
9090
) −)2−
M2M
sin(ωst(−ω90
) 90 )
i2 (t) =i2 ( t ) BA
st +
st −
2A 90 ) + sin( ωss + ϕ
BA BA sin
πX π X
(31)
(31)
P2 =
4VBA 2 MbusBA
4V 2 2 MbusBA
4VBA 2 MbusBA
(sin ϕ2A + sin ϕ2B ) = 4VBABAM2busBA
[sin ϕ + sin( ϕ − δ)]
2
P2 = π X 2
(sin ϕ2A + sin ϕ2B ) =
[sin ϕ2A +2Asin(ϕ2A − δ2A)]
π
2 X
π X
π X
(32)
(32)
The ZVS constraint conditions for phase leg A and B of primary side and secondary side can be
shown as follows:
Energies 2017, 10, 446
14 of 23
Energies 2017, 10, 446
14 of 23
The ZVS constraint conditions for phase leg A and B of primary side and secondary side can be
 ϕ  2V
shown asPrimary-side
follows:
i2  − 2A  = BA (2 MBA cos ϕ2A − 1 − cos δ ) < 0
(33)
leg A:
 t  πX
ϕ BA
(33)
(2MBA cos ϕ2A − 1 − cos δ) < 0
Primary-side leg A : i2 − 2A
= 2V
t
 ϕ2B πX 2VBA
i
−
=
[2
M
cos(
ϕ
−
δ
)
−
cos
δ
−
1]
<
0
Primary-side leg B:
(34)


2A
ϕ 2
t BA [2M
π X cos(BA
(34)
ϕ − δ) − cos δ − 1] < 0
Primary-side leg B : i − 2B = 2V
2
t
πX
BA
2A
2VBA
2V
ϕ2A
− cos
πX
i2 0(2M
MBA
= BABA−(2cos
− cos
ϕ2A
( )
ϕ
) ϕ> 0) > 0
cos
−2B
(35)(35)
2B
πX
Equations (26) and (35) show that when MBA > 1, all switches of secondary side can realize ZVS
Equations (26)
and (35)
show and
that the
when
MBA >proposed
1, all switches
of secondary
side
can realize
ZVS
under traditional
control
method
newly
PWM-PHS
control
method.
Therefore,
under
traditional
control
method
and
the
newly
proposed
PWM-PHS
control
method.
Therefore,
only the ZVS realization conditions for the primary side are analyzed. The designed maximum value
ZVS and
realization
conditions
for theisprimary
side are analyzed.
The
designed maximum value
of only
MBAthe
is 1.15,
the following
analysis
under condition
of MBA =
1.15.
of MBA is 1.15, and the following analysis is under condition of MBA = 1.15.
To transfer same power under traditional phase shift control method and newly proposed
To transfer same power under traditional phase shift control method and newly proposed
PWM-PHS control method, phase shift angles of ϕ2 , ϕ2A and δ should satisfy the constraint condition
PWM-PHS control method, phase shift angles of φ2, φ2A and δ should satisfy the constraint condition
shown in (36) and (37). The diagram of ZVS operating range of primary side phase leg A and B for the
shown in (36) and (37). The diagram of ZVS operating range of primary side phase leg A and B for
variation of δ under MBA = 1.15 is given in Figure 13:
Secondary-side :
Secondary-side:
i2 (0) =
the variation of δ under MBA = 1.15 is given in Figure 13:
22
2
4V
MbusBA
8VBA82V
MBAbusBA
MbusBA
4VBA
BA
busBA [sin ϕ
sin
ϕ
=
+ sin
ϕ
=
+ sin(
ϕ2A( ϕ−2A
δ )]− δ)]
sin
[sin ϕ2A2A
2
2
2
2
2
π Xπ X
π 2X
X
π
(36)(36)
sin ϕ2
δ δ
ϕ2A
arcsin[ sin ϕ 2 ] +] +
ϕ 2A== arcsin[
cos
(
0.5δ
)
cos(0.5δ ) 2 2
(37)(37)
Figure 13a,c shows the ZVS range of phase leg A and B in the primary side, Figure 13b,d is the
Figure 13a,c shows the ZVS range of phase leg A and B in the primary side, Figure 13b,d is the
zoom-in
diagrams of Figure 13a,c, respectively. The enlarged ZVS range of phase leg A and B are
zoom-in diagrams of Figure 13a,c, respectively. The enlarged ZVS range of phase leg A and B are
defined
as
shows that
that the
theZVS
ZVSrange
rangeofofphase
phaselegleg
and
B can
defined asη ηand
andγ γrespectively.
respectively. Figure
Figure 13
13 shows
AA
and
B can
be be
enlarged
with
the
increase
of
δ.
The
enlarged
ZVS
range
of
phase
leg
A
and
B
are
represented
enlarged with the increase of δ. The enlarged ZVS range of phase leg A and B are represented in in
Figure
13b,d.
During
η and
γ, γ,
thethe
ZVS
MOSFETs
number
of of
primary
side
under
traditional
phase
shift
Figure
13b,d.
During
η and
ZVS
MOSFETs
number
primary
side
under
traditional
phase
control
(δ
=
0)
is
0,
while
the
ZVS
MOSFETs
number
under
PWM-PHS
control
(δ
6
=
0)
is
2.
shift control (δ = 0) is 0, while the ZVS MOSFETs number under PWM-PHS control (δ ≠ 0) is 2.
(a)
(b)
(c)
(d)
Figure 13. Soft switching range of primary side for variation of δ under MBA = 1.15: (a) phase leg A;
Figure 13. Soft switching range of primary side for variation of δ under MBA = 1.15: (a) phase leg A;
(b) zoom-in figure of (a); (c) phase leg B; (d) zoom-in figure of (c).
(b) zoom-in figure of (a); (c) phase leg B; (d) zoom-in figure of (c).
Energies 2017, 10, 446
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15 of 23
15 of 23
increase
The theoretical analysis results prove that the proposed PWM-PHS control method can increase
the number of MOSFETs which can realize
realize ZVS
ZVS under
under specific
specific power
power condition.
condition.
4.3. Control
Control Strategy
Strategy of
of the
the Proposed
Proposed Two-Stage
Two-Stage Three-Port
4.3.
Three-Port BDC
BDC
Through the
the proposed
proposed two-stage
two-stage three-port
three-port BDC,
BDC, HESS
HESS is
is integrated
integrated to
to the
the DC
DC bus
bus of
of DC
DC
Through
microgrid.
The
proposed
three-port
BDC
is
composed
of
two
parts:
three-port
SR
BDC
and
three-phase
microgrid. The proposed three-port BDC is composed of two parts: three-port SR BDC and threeinterleaved
BDC. BDC.
The control
targettarget
of three-port
SR BDC
is toiskeep
DC DC
busbus
voltage
constant
by
phase
interleaved
The control
of three-port
SR BDC
to keep
voltage
constant
compensating
the
mismatch
between
generation
and
demand.
Meanwhile,
the
control
objective
of
the
by compensating the mismatch between generation and demand. Meanwhile, the control objective
three-phase
interleaved
BDC isBDC
converting
the widely
fluctuating
SC voltage
V sc to aVsc
constant
voltage
of
the three-phase
interleaved
is converting
the widely
fluctuating
SC voltage
to a constant
V
.
The
control
scheme
for
the
proposed
two-stage
three-port
BDC
is
shown
in
Figure
14.
dc-link
voltage Vdc-link. The control scheme for the proposed two-stage three-port BDC is shown in Figure 14.
Figure 14. Control scheme for the proposed two-stage three-port BDC.
Figure 14. Control scheme for the proposed two-stage three-port BDC.
The basic idea of the three-port SR BDC is that the battery supports slow transients, and SC
The fast
basictransients.
idea of the
three-port
SR BDC has
is that
the battery
supports
transients,
SC
supports
The
control structure
an inner
current
loop as slow
well as
an outer and
control
supports
fast
transients.
The
control
structure
has
an
inner
current
loop
as
well
as
an
outer
control
loop
loop for voltage stabilization. The bus voltage Vbus is compared with the reference voltage Vbus*, and
for voltage
stabilization.
bus voltage
V bus is compared
with
reference
voltage
V bus *,
and the
the
deviation
of voltage isThe
tracked
by the voltage
PI controller
to the
produce
the total
current
reference
deviation
of
voltage
is
tracked
by
the
voltage
PI
controller
to
produce
the
total
current
reference
ibus **.
ibus*. By using a low-pass filter (LPF), the total current is divided into a dynamic component ibus_SC
By using
a low-pass
filter (LPF),
the
totalthe
current
is divided
intoofaSC
dynamic
and
and
an average
component
ibus_BA*.
Then,
reference
currents
and BAcomponent
are derivedibus_SC
as iP1** and
an
average
component
i
*.
Then,
the
reference
currents
of
SC
and
BA
are
derived
as
i
*
and
P1
bus_BA
iP2* respectively. Through the inner current loops, phase shift angles are adjusted to maintainiP2a*
respectively.
Through
the inner current loops, phase shift angles are adjusted to maintain a constant
constant
DC bus
voltage.
DC bus
Thevoltage.
control objective of the three-phase interleaved BDC is to keep the dc-link voltage constant.
control
objective
of the three-phase
BDC
is to keep the dc-link voltage constant.
SameThe
with
the control
method
of three-portinterleaved
SR BDC, V
dc-link is compared with reference voltage
Same
with
the
control
method
of
three-port
SR
BDC,
V
is compared
with reference
dc-linkvoltage
Vdc-link*. The current reference is obtained through the outer
loop. Combining
the voltage
current
V
*.
The
current
reference
is
obtained
through
the
outer
voltage
loop.
Combining
the
current
dc-link
reference and voltage values, the driving frequency f and duty ratio D are deduced. Through
the
reference
and
voltage
values,
the
driving
frequency
f
and
duty
ratio
D
are
deduced.
Through
the
interleaved PWM generator, driving signals of three-phase interleaved BDC are acquired.
interleaved PWM generator, driving signals of three-phase interleaved BDC are acquired.
5. Experimental Results
5. Experimental Results
To verify the validity of theoretical analyses, a 1 kW prototype was built in the laboratory. The
To verify the validity of theoretical analyses, a 1 kW prototype was built in the laboratory.
MOSFETs adopted in the system are C3M0065090D units from CREE (Durham, NC, USA). The
The MOSFETs adopted in the system are C3M0065090D units from CREE (Durham, NC, USA).
control platform is a TMS320F28379D from Texas Instruments (Dallas, TX, USA). Based on the
The control platform is a TMS320F28379D from Texas Instruments (Dallas, TX, USA). Based on
theoretical analysis above, a set of optimized parameters of the proposed system are selected and
the theoretical analysis above, a set of optimized parameters of the proposed system are selected and
shown in Table 1.
shown in Table 1.
Energies
Energies2017,
2017,10,
10,446
446
16
16ofof23
23
Table 1. Parameters of the proposed system.
Table 1. Parameters of the proposed system.
Converter Parameter
Value
Converter
Parameter
Value
Resonant Inductor Lr1 and Lr2
15 μH
ResonantCapacitors
Inductor LC
r1r1and
r2r2
Resonant
andLC
Resonant Capacitors Cr1 and Cr2
:n23:1
Transformer turns
turns ratio
rationn13:n
Transformer
13 23 :1
dc-link
Port11voltage
voltageVVdc-link
Port
Port
2
voltage
V
BA
Port 2 voltage VBA
Port 3 voltage V bus
Port
3 voltage
Vbus
Voltage
Gain M
15 µH141 nF
141 nF
0.425:0.51:1
0.425:0.51:1
85 V 85 V
90 V–102
V
90 V–102
V
200 V
1 200 V
Voltage
SC
Voltage Gain
Gain M
MBA
Super Capacitor Voltage V SC
Voltage Gain MBA
Buck/Boost Inductor of BDC L
Super Capacitor Voltage VSC
1–1.15 1
30 V–75 V
1–1.15
15 µH
30 V–75 V
SC
Buck/Boost Inductor of BDC L
15 μH
5.1. SC and BA Charging Mode
Forand
theBA
SCCharging
and BA Mode
charging mode, a 200 V voltage source is provided for port 3, port 1 and
5.1. SC
port 2 are connected to resistive loads of 15 Ω, in this experiment V T1 and V T2 lag V T3 . Port 1 and 2
For the SC and BA charging mode, a 200 V voltage source is provided for port 3, port 1 and port
are entirely independent from each other. The concrete data of this experiment are as follows: input
2 are connected to resistive loads of 15 Ω, in this experiment VT1 and VT2 lag VT3. Port 1 and 2 are
voltage V bus = 200 V, output voltage V dc-link = 84 V, driving frequency f s = 130 kHz, ϕ1 = −18.5◦ ,
entirely independent from each other. The concrete data of this experiment are as follows: input
ϕ2 = −20◦ ; V BA = 102 V, P1 = −458.2 W, P2 = −684.5 W, P3 = −1204.3 W. The efficiency is 94.9%.
voltage Vbus = 200 V, output voltage Vdc-link = 84 V, driving frequency fs = 130 kHz, φ1 = −18.5°, φ2 = −20°;
MSC = MBA = 1, thus all switches of 3 ports can realize ZVS. The required phase shift angles to realize
VBA = 102 V, P1 = −458.2 W, P2 = −684.5 W, P3 = −1204.3 W. The efficiency is 94.9%. MSC = MBA = 1, thus
MSC = MBA = 1 are compared in Table 2. It is proved that the experimental results are consistent with
all switches of 3 ports can realize ZVS. The required phase shift angles to realize MSC = MBA = 1 are
theoretical analysis.
compared in Table 2. It is proved that the experimental results are consistent with theoretical analysis.
Table 2. Comparison of ϕ1 and ϕ2 under theoretical calculation and experiment.
Table 2. Comparison of φ1 and φ2 under theoretical calculation and experiment.
MethodMethod
Theoretical
Calculation
Theoretical
Calculation
Experiment
Experiment
ϕ1
−19.1◦
φ1
ϕ2
−19.1◦
−19.1°
◦
−18.5
−20◦
−18.5°
φ2
−19.1°
−20°
Figure
Figure15
15shows
showsthe
thewaveforms
waveformsofofresonant
resonantcurrents
currentsofofthe
thethree-port
three-portSR
SRBDC.
BDC.
Figure
Figure15.
15.Waveforms
Waveformsof
ofresonant
resonantcurrents
currentsofofthree
threeports
portsunder
underSC
SCand
andBA
BAcharging
chargingmode.
mode.
Figure16
16shows
showsthe
thewaveforms
waveforms of
ofresonant
resonant currents
currents and
and transformer
transformer voltages
voltages of
of three
three ports.
ports.
Figure
Figure
16a,b
show
the
operating
waveforms
of
port
1,
such
as
resonant
current
i
1
,
drain-source
Figure 16a,b show the operating waveforms of port 1, such as resonant current i1 , drain-source voltage
voltage
andvoltage
drivingofvoltage
of S1
vDS_S1
and
vG_S1. 16b
Figure
16bzoom-in
is the zoom-in
waveforms
Figure
16a,
and
driving
S1 vDS_S1
and
vG_S1
. Figure
is the
waveforms
of Figureof16a,
from
it
from
it
we
can
see
that
the
MOSFETs
of
port
1
can
realize
ZVS.
Figure
16c,d
show
the
operating
we can see that the MOSFETs of port 1 can realize ZVS. Figure 16c,d show the operating waveforms of
waveforms
of port
2, resonant
currentvoltage
i2, drain-source
voltage
voltage of S5 vDS_S5 and
port
2, resonant
current
i2 , drain-source
and driving
voltageand
of Sdriving
5 vDS_S5 and vG_S5 . Figure 16e,f
vG_S5. Figure 16e,f show waveforms of port 3. It is shown that MOSFETs of port 2 and 3 can realize
ZVS under SC and BA charging mode with MSC = MBA = 1.
Energies 2017, 10, 446
17 of 23
show waveforms of port 3. It is shown that MOSFETs of port 2 and 3 can realize ZVS under SC and BA
charging
mode
with
Energies
2017, 10,
446 MSC = MBA = 1.
17 of 23
(a)
(b)
(c)
(d)
(e)
(f)
Figure 16. Experimental results of three-port SR BDC under SC and BA charging mode: (a,b) SC port;
Figure 16. Experimental results of three-port SR BDC under SC and BA charging mode: (a,b) SC port;
(c,d) BA port; (e,f) DC bus port.
(c,d) BA port; (e,f) DC bus port.
5.2. SC and BA Discharging Mode
5.2. SC and BA Discharging Mode
In the SC and BA discharging mode, two voltage sources are connected to SC and BA port
respectively,
a resistive
load of 40 Ωmode,
is connected
to port 3.sources
Power isare
transferred
from
and BA
2 to port
In
the SC and
BA discharging
two voltage
connected
toport
SC 1and
port
3.
Both
M
busSC and MbusBA are designed as 0.5. The concrete data of this experiment are as follows:
respectively, a resistive load of 40 Ω is connected to port 3. Power is transferred from port 1 and 2
input voltage VSC = 30 V, VBA = 102 V, Vdc-link = 85 V, output voltage Vbus = 200 V; driving frequency fs =
to port
3. Both MbusSC and MbusBA are designed as 0.5. The concrete data of this experiment are as
130 kHz, φ1 = 18.2°, φ2 = 13.4°; P1 = 521.5 W, P2 = 533.9 W, P3 = 993.1 W. The efficiency of two stage
follows: input voltage V SC = 30 V, V BA = 102 V, V dc-link = 85 V, output voltage V bus = 200 V; driving
three-port BDC is 94.1%. All switches
of three
can realize ZVS.
◦ ; Pports
frequencyThe
f s =required
130 kHz,phase
ϕ1 =shift
18.2◦angles
, ϕ2 = to
13.4
= 521.5 W, P2 == 533.9
W, P3 = 993.1
W. The efficiency
realize1 MbusBA = MbusSC
0.5 are compared
in Table 3. It is
of two
stage
three-port
BDC
is
94.1%.
All
switches
of
three
ports
can
realize
ZVS.
proved that the experimental results are consistent with theoretical analysis. For the three-phase
The
required
phase
shiftcurrents
angles ito
realize
M
MbusSC
= 0.5 are
compared
Table 3. It is
interleaved
BDC,
inductor
L1–i
L3 and V
dc-link
are =
shown
in Figure
17, and
they are in
completely
busBA
proved
that the
experimental
results
arewaveforms.
consistent with theoretical analysis. For the three-phase
consistent
with
the theoretical
analysis
interleaved BDC, inductor currents iL1 –iL3 and V dc-link are shown in Figure 17, and they are completely
consistent with the theoretical analysis waveforms.
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18 of 23
Energies 2017, 10, 446
18 of 23
Table
1 1and
Table3.3.Comparison
Comparisonofofϕφ
andϕφ22 under
under theoretical
theoretical calculation
calculation and
and experiment.
experiment.
Energies 2017,
2017,10,
10,446
446
Energies
Method
Method
ϕ1
φ1 ϕ2
φ2
18 of
of23
23
18
Theoretical
Calculation
19.8◦calculation
13.6◦ and
Theoretical
Calculation
19.8°
13.6°
Table
3. Comparison
Comparison
of φφ11 and
and
under theoretical
theoretical
calculation
and experiment.
experiment.
Table
3.
of
φφ22 under
Experiment
Experiment
Method
Method
18.2◦
13.4◦
18.2°
13.4°
φφ22
φφ11
Theoretical Calculation
Calculation
Theoretical
19.8°
19.8°
13.6°
13.6°
Experiment
Experiment
18.2°
18.2°
13.4°
13.4°
Figure
Figure17.
17.Waveforms
Waveformsof
ofthree-phase
three-phaseinterleaved
interleavedBDC.
BDC.
Figure 17.
17. Waveforms
Waveforms of
of three-phase
three-phase interleaved
interleaved BDC.
BDC.
Figure
Figure18
18shows
showsthe
thewaveforms
waveformsofofresonant
resonantcurrents
currentsofofthree
threeports.
ports.Figure
Figure19a
19ashows
shows
vDS_S1
Figure
i1 ,i1v, DS_S1
Figure
18
shows
the
waveforms
of
resonant
currents
of
three
ports.
Figure
19a
shows
i
1
,
v
DS_S1
the
waveforms
of three
ports.19e
Figure
19a ishows
, vDS_S1
andvvG_S1
G_S1 Figure
of
Figure
19c
shows
v,DS_S5
and vcurrents
G_S5 of port
2. Figure
shows
3, vDS_S9i1and
vG_S9 of
and
of port
port181.1.shows
Figure
19c
showsi2,i2of
vresonant
DS_S5 and vG_S5 of port 2. Figure 19e shows i3 , vDS_S9 and
and
G_S1 of
of 19b,d,f
port 1.
1. Figure
Figure
19c shows
shows
DS_S5 and
and
G_S5 of
of port
port
2. Figure
Figure
19e
shows ii33,, vvDS_S9
DS_S9 and
and vvG_S9
G_S9 of
of are
and
vvG_S1
port
19c
ii22,, vvDS_S5
vvG_S5
2.
19e
shows
port
3.
Figure
is
enlarged
waveforms
of
Figure
19a,c,e.
The
waveforms
of
three
ports
vG_S9 of port 3. Figure 19b,d,f is enlarged waveforms of Figure 19a,c,e. The waveforms of three ports
port 3.
3. Figure
Figure 19b,d,f
19b,d,f is
is enlarged
enlarged waveforms
waveforms of
of Figure
Figure 19a,c,e.
19a,c,e. The
The waveforms
waveforms of
of three
three ports
ports are
are
port
consistent
with
analysis
above,
and
ofofthree-ports
can
realize
under
conditions
when
are
consistent
with
analysis
above,
andall
allMOSFETs
MOSFETsof
three-ports
can
realize
under
conditions
when
consistent
with
analysis
above,
and
all
MOSFETs
three-ports
can
realize
under
conditions
when
consistent with analysis above, and all MOSFETs of three-ports can realize under conditions when
M
SC = MBA = 1.
MSC = MBA = 1.
MSC
SC =
=M
MBA
BA =
= 1.
1.
M
Figure
18. Waveforms
Waveforms
of resonant
resonant
currentsof
ofthree
three ports
ports and
and
transformer
port
voltages.
Figure
18.
currents
of
three
port
voltages.
Figure
18. Waveforms
of of
resonant
currents
ports
andtransformer
transformer
port
voltages.
Figure 18. Waveforms of resonant currents of three ports and transformer port voltages.
(a)
(a)
(a)
(b)
(b)
Figure 19. Cont.
(b)
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19 of 23
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19 of 23
(c)
(d)
(e)
(f)
Figure 19. Experimental results of three-port SR BDC under SC and BA charging mode: (a,b) SC port;
Figure 19. Experimental results of three-port SR BDC under SC and BA charging mode: (a,b) SC port;
(c,d) BA port; (e,f) DC bus port.
(c,d) BA port; (e,f) DC bus port.
5.3. Proposed PWM-PHS Control Method
5.3. Proposed PWM-PHS Control Method
The effectiveness of proposed PWM-PHS control method is verified based on the BA channel
for battery
discharging
mode. A 80
Ω resistivecontrol
load is method
connectedisto
port 3. The
operating
The
effectiveness
of proposed
PWM-PHS
verified
based
on the parameters
BA channel for
are
defined
as
follows:
V
BA = 45 V, Vbus = 100 V, MBA = 1.15. Two groups of contrast experiment are
battery discharging mode. A 80 Ω resistive load is connected to port 3. The operating parameters are
done, two groups adapt traditional phase-shift and the newly proposed PWM-PHS control method,
defined as follows: V BA = 45 V, V bus = 100 V, MBA = 1.15. Two groups of contrast experiment
respectively.
are done, two groups adapt traditional phase-shift and the newly proposed PWM-PHS control
The operating parameters under traditional phase shift control method are as follows: driving
method,
respectively.
frequency
fs = 130 kHz, φ2A = φ2B = 23.4°, P2 = 138.3 W, P3 = 124.6 W, the efficiency is 90.1%. Figure 20a,c
The
operating
parameters
under
traditional
phase shift
control
method are
as follows:
driving
shows
the operating
waveforms
of port
2 and 3. Resonant
current
i2, drain-source
voltage
and driving
◦
frequency
130
ϕ2A
= ϕFigure
, P
= 138.3 waveforms
W, P3 = 124.6
W, the
efficiency
is 90.1%.
voltagef sof=S5
andkHz,
S9 are
given.
20b,d
is2 enlarged
of Figure
20a,c.
Experimental
2B = 23.4
Figure
20a,cshow
shows
theMOSFETs
operatingofwaveforms
of realize
port 2 ZVS,
and 3.MOSFETs
Resonantofcurrent
, drain-source
voltage
results
that
BA port can’t
DC busi2port
operate under
ZVS when
MBA = 1.15.
and driving
voltage
of S5 and S9 are given. Figure 20b,d is enlarged waveforms of Figure 20a,c.
As shown
in show
Figurethat
20a,b,
MOSFETsofofBA
BAport
port can’t
can’t realize
realize ZVS,
signal of
of DC
S5 turns
Experimental
results
MOSFETs
ZVS,drive
MOSFETs
bus port
positive
before
the
output
capacitor
of
S5
gets
fully
discharged.
Parasitic
ringing,
which
is
due to
operate under ZVS when MBA = 1.15.
oscillation between output capacitance of S5 and parasitic inductance present in the converter layout,
As shown in Figure 20a,b, MOSFETs of BA port can’t realize ZVS, drive signal of S5 turns positive
occurs during turn-on switching transient. In Figure 20c,d, output capacitor is fully discharged before
before the output capacitor of S5 gets fully discharged. Parasitic ringing, which is due to oscillation
driving signal turns positive. Consequently, ZVS is achieved for MOSFETs of DC bus port, and
between
output
capacitance
of S5 and parasitic inductance present in the converter layout, occurs
parasitic
ringing
is avoided.
during turn-on switching transient. In Figure 20c,d, output capacitor is fully discharged before driving
signal turns positive. Consequently, ZVS is achieved for MOSFETs of DC bus port, and parasitic
ringing is avoided.
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2017, 10, 446
20 of 23
20 of 23
(a)
(b)
(a)
(b)
(c)
(d)
Figure 20. Experimental results of BA channel using phase-shift control method under MBA = 1.15:
Figure 20.
ExperimentalDC
results
of BA channel using phase-shift control method
under MBA = 1.15:
(d)
(a,b) BA port; (c,d)(c)
bus port.
(a,b) BA port; (c,d) DC bus port.
Figure 20. Experimental results of BA channel using phase-shift control method under MBA = 1.15:
The operating parameters under phase shift control method are as follows: driving frequency fs
(a,b) BA port; (c,d) DC bus port.
= 130 kHz, φ2A =35.8°, φ2B = 10.8°, P2 = 134.8 W, P3 = 125 W, the efficiency is 92.7%. The efficiency is
The operating parameters under phase shift control method are as follows: driving frequency
relatively low since
power level
low.
◦ ,the
◦ , Pisphase
The operating
parameters
under
shiftW,
control
method
areefficiency
as follows:isdriving
fs
f s = 130 kHz,
ϕ2A =35.8
ϕ2B = 10.8
= 134.8
P3 = 125
W, the
92.7%.frequency
The efficiency
Figure
21a,c shows
the operating2 waveforms of phase
leg A and B of port 2 respectively. Figure
= 130 kHz,
φ2A
=35.8°,
φpower
2B = 10.8°,
P2 =is134.8
W, P3 = 125 W, the efficiency is 92.7%. The efficiency is
is relatively
low
since
the
level
low.
21e shows waveforms of port 3. Resonant current i2, drain-source voltage and driving voltage of S5,
relatively
low
since
the
level
is is
low.
Figure
21a,c
thepower
operating
waveforms
phase legofAFigure
and B21a,c,e.
of portExperimental
2 respectively.
Figure 21e
S7 and
S9 shows
are
given.
Figure
21b,d,f
enlargedof
waveforms
results
Figure
21a,c
shows
the
operating
of
phase
leg
A and
B of Bport
2 respectively.
Figure
show that MOSFETs
of Resonant
phase A of current
BAwaveforms
port realize
ZVS,
MOSFETs
of phase
of BA
port
can’t realize
shows waveforms
of port 3.
i2 , drain-source
voltage
and
driving
voltage
of S5,
S7 and
21e ZVS,
shows
waveforms
of
port
3.
Resonant
current
i
2
,
drain-source
voltage
and
driving
voltage
of S5,
MOSFETs
of
DC
bus
port
achieve
ZVS
operating
when
M
BA = 1.15.
S9 are given. Figure 21b,d,f is enlarged waveforms of Figure 21a,c,e. Experimental results show that
S7 and S9
are
Figure
21b,d,f
is enlarged
waveforms
of Figure
21a,c,e.
results
Like
thegiven.
conditions
shown
in Figure
20a,b, MOSFETs
of phase
B can’t
realize Experimental
ZVS, and parasitic
MOSFETs of phase A of BA port realize ZVS, MOSFETs of phase B of BA port can’t realize ZVS,
show
that MOSFETs
of phase
A of BAswitching
port realize
ZVS, MOSFETs
of phaseresults
B of BA
portshow
can’tthat,
realize
ringing
presents during
the turn-on
transients.
The experimental
above
MOSFETs
of DC
bus port achieve
ZVS
operating
when MBA
= 1.15.
using traditional
shift control
method, only
four
switches
ZVS,when
MOSFETs
of DC bus phase
port achieve
ZVS operating
when
MBA
= 1.15. can realize ZVS, and the
Like
the the
conditions
shown
20a,b,
MOSFETs
of
phase
can’t
realize
ZVS,
parasitic
efficiency
is
90.1%. While,
byin
adopting
the
newly
proposed,of
thephase
number
of
switches
which
can
realize
Like
conditions
shown
inFigure
Figure
20a,b,
MOSFETs
BBcan’t
realize
ZVS,
andand
parasitic
ringing
presents
during
the
turn-on
switching
transients.
The
experimental
results
above
show
ZVS
increases
to
6,
and
the
efficiency
increases
to
92.7%.
The
experimental
results
are
consistent
with
ringing presents during the turn-on switching transients. The experimental results above show that,that,
theoretical
analysis.phase
Itphase
is proved
that the
PWM-PHS
control
method
can
improve
operating
when
using
traditional
shift
method,
only
fourswitches
switches
can
realize
ZVS,
when
using
traditional
shiftcontrol
control
method,
only
four
can
realize
ZVS,
andand
the the
characteristics
of
SR
BDC
under
the
condition
of
M
BA > 1.
efficiency is 90.1%. While, by adopting the newly proposed, the number of switches which can realize
efficiency is 90.1%. While, by adopting the newly proposed, the number of switches which can realize
increases
andthe
the efficiency
efficiency increases
to to
92.7%.
The The
experimental
resultsresults
are consistent
with
ZVSZVS
increases
to to
6, 6,and
increases
92.7%.
experimental
are consistent
theoretical
analysis.
It
is
proved
that
the
PWM-PHS
control
method
can
improve
operating
with theoretical analysis. It is proved that the PWM-PHS control method can improve operating
characteristics
of SR
BDC
under
thecondition
conditionof
ofM
MBA
BA >>1.
characteristics
of SR
BDC
under
the
1.
(a)
(b)
(a)
(b)
Figure 21. Cont.
Energies 2017, 10, 446
21 of 23
Energies 2017, 10, 446
21 of 23
(c)
(d)
(e)
(f)
Figure 21. Experimental results of BA channel using PWM-PHS control method under MBA = 1.15:
Figure 21. Experimental results of BA channel using PWM-PHS control method under MBA = 1.15:
(a,b) phase leg A of BA port; (c,d) phase leg B of BA port; (e,f) DC bus port.
(a,b) phase leg A of BA port; (c,d) phase leg B of BA port; (e,f) DC bus port.
6. Conclusions
6. Conclusions
In this paper, a two-stage three-port BDC is fabricated to interface SC and BA with the DC
In this paper,
a two-stage
BDC
fabricated
to interface
SC BDC.
and BA
the DC
microgrid.
It is composed
of a three-port
three-port SR
BDCisand
a three-phase
interleaved
The with
particular
two-stage
makes
possible toSR
handle
variations
at SC port,
and The
will ensure
microgrid.
It isstructure
composed
of aitthree-port
BDCwide
and voltage
a three-phase
interleaved
BDC.
particular
unity voltage
gainmakes
between
SC and DC
ports.
In addition,
PWM-PHSat
hybrid
control
is
two-stage
structure
it possible
to bus
handle
wide
voltageavariations
SC port,
andmethod
will ensure
applied
on
the
BA
channel.
The
proposed
control
method
contributes
to
an
increasing
number
of
unity voltage gain between SC and DC bus ports. In addition, a PWM-PHS hybrid control method
switches
under ZVS
under
variable
voltage
gain. Together
with to
thean
proposed
PWM-PHS
is applied
onoperating
the BA channel.
The
proposed
control
method
contributes
increasing
number of
control strategy, the proposed BDC acquires optimized operation characteristics with both enlarged
switches operating under ZVS under variable voltage gain. Together with the proposed PWM-PHS
ZVS range and reduced power circulation loss. Finally, a 1 kW prototype is built, and the efficiency
control strategy, the proposed BDC acquires optimized operation characteristics with both enlarged
of SC and BA charging and discharging mode are 94.9% and 94.1% respectively. The experimental
ZVSresults
range validate
and reduced
power circulation loss. Finally, a 1 kW prototype is built, and the efficiency
that all switches of SC and DC bus ports can realize ZVS under varying VSC. With the
of SC
and
BA
charging
and
discharging
mode
are 94.9%
andswitches
94.1% respectively.
The experimental
proposed topology and PWM-PHS
control
method,
two more
of BA port achieve
ZVS even
results
validate
that
all
switches
of
SC
and
DC
bus
ports
can
realize
ZVS
under
varying
V SC . With the
under the worst input condition of MBA = 1.15.
proposed topology and PWM-PHS control method, two more switches of BA port achieve ZVS even
Acknowledgments:
research of
wasMsupported
by the National High Technology Research and Development
under
the worst inputThis
condition
BA = 1.15.
Program of China (863 Program) (Grant: 2015AA050603) and supported by Tianjin Municipal Science and
Technology Commission
(Grant:
14ZCZDGX00035).
authorsHigh
would
also like to
thank the
This research
was
supported by theThe
National
Technology
Research
andanonymous
Development
Acknowledgments:
reviewers
for their
valuable
comments
and2015AA050603)
suggestions to improve
the qualityby
of the
paper.
Program
of China
(863
Program)
(Grant:
and supported
Tianjin
Municipal Science and
Technology Commission (Grant: 14ZCZDGX00035). The authors would also like to thank the anonymous
Author Contributions: Cheng-Shan Wang, Wei Li and Yi-Feng Wang designed the main parts of the study,
reviewers
for their valuable comments and suggestions to improve the quality of the paper.
including the circuit simulation model, topology innovation and simulation development. Fu-Qiang Han and
Author
Contributions:
Cheng-Shan
Wang,
Wei Li and
Wang
designed
of thefor
study,
Zhun
Meng helped in
the hardware
development
and Yi-Feng
experiment.
Guo-Dong
Li the
weremain
also parts
responsible
including
the
writing
thecircuit
paper.simulation model, topology innovation and simulation development. Fu-Qiang Han and
Zhun Meng helped in the hardware development and experiment. Guo-Dong Li were also responsible for writing
Conflicts of Interest: The authors declare no conflict of interest.
the paper.
Conflicts of Interest: The authors declare no conflict of interest.
References
Energies 2017, 10, 446
22 of 23
References
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Marzband, M.; Ardeshiri, R.R.; Moafi, M.; Uppal, H. Distributed generation for economic benefit
maximization through coalition formation based on Game Theory. Int. Trans. Electr. Energy Syst. 2017, 1–16.
[CrossRef]
Han, Y.; Chen, W.; Li, Q. Energy Management Strategy Based on Multiple Operating States for
a Photovoltaic/Full Cell/Energy Storage DC Microgrid. Energies 2017, 10, 136. [CrossRef]
Liu, J.; Zhang, L. Strategy Design of Hybrid Energy Storage System for Smoothing Wind Power Fluctuations.
Energies 2016, 9, 991. [CrossRef]
Marzband, M.; Ghazimirsaeid, S.S.; Uppal, H.; Fernando, T. A real-time evaluation of energy management
systems for smart hybrid home Microgrids. Electr. Power Syst. Res. 2017, 143, 624–633. [CrossRef]
Marzband, M.; Moghaddam, M.M.; Akorede, M.F.; Khomeyrani, G. Adaptive load shedding scheme for
frequency stability enhancement in microgrids. Electr. Power Syst. Res. 2016, 140, 78–86. [CrossRef]
Xu, Q.; Hu, X.; Wang, P.; Xiao, J.; Tu, P.; Wen, C.; Lee, M.Y. A Decentralized Dynamic Power Sharing Strategy
for Hybrid Energy Storage System in Autonomous DC Microgrid. IEEE Trans. Ind. Electr. 2016. [CrossRef]
Kollimalla, S.K.; Mishra, M.K.; Ukil, A.; Gooi, H.B. DC Grid Voltage Regulation Using New HESS Control
Strategy. IEEE Trans. Sustain. Energy 2016, 8, 772–781. [CrossRef]
Jin, Z.; Hou, M.; Dong, F.; Li, Y. A New Control Strategy of DC Microgrid with Photovoltaic Generation and
Hybrid Energy Storage. In Proceedings of the IEEE PES Asia-Pacific Power and Energy Conference, Xi’an,
China, 25–28 October 2016; pp. 434–438.
Marzband, M.; Alavi, H.; Ghazimirsaeid, S.S.; Uppal, H.; Fernando, T. Optimal Energy Management System
Based on Stochastic Approach for a Home Microgrid with Integrated Responsive Load Demand and Energy
Storage. Sustain. Cities Soc. 2017, 28, 256–264. [CrossRef]
Marzband, M.; Parhizi, N.; Savaghebi, M.; Guerrero, J.M. Distributed Smart Decision-Making for
a Multi-microgrid System Based on a Hierarchical Interactive Architecture. IEEE Trans. Energy Convers. 2016,
31, 637–648. [CrossRef]
Marzband, M.; Azarinejadian, F.; Savaghebi, M.; Guerrero, M. An Optimal Energy Management System for
Islanded Microgrids Based on Multiperiod Artificial Bee Colony Combined With Markov Chain. IEEE Syst. J.
2015, 100, 1–11. [CrossRef]
Marzband, M.; Yousefnejad, E.; Sumper, A.; Domínguez-García, J.L. Real Time Experimental Implementation
of Optimum Energy Management System in Standalone Microgrid by Using Multi-layer Ant Colony
Optimization. Int. Trans. Electr. Energy Syst. 2016, 75, 265–274. [CrossRef]
Marzband, M.; Ghadimi, M.; Sumper, A.; Domínguez-García, J.L. Experimental validation of a real-time
energy management system using multi-period gravitational search algorithm for microgrids in islanded
mode. Appl. Energy 2014, 128, 164–174. [CrossRef]
Marzband, M.; Parhizi, N.; Adabi, J. Optimal energy management for stand-alone microgrids based on
multi-period imperialist competition algorithm considering uncertainties: Experimental validation. Int. Trans.
Electr. Energy Syst. 2016, 26, 1358–1372. [CrossRef]
Marzband, M.; Sumper, A.; Ruiz-Álvarez, A.; Domínguez-García, J.L. Experimental evaluation of a real
time energy management system for stand-alone microgrids in dayahead markets. Appl. Energy 2013, 106,
365–376. [CrossRef]
Marzband, M.; Sumper, A.; Domínguez-García, J.L.; Gumara-Ferret, R. Experimental Validation of a Real
Time Energy Management System for Microgrids in Islanded Mode Using a Local Day-Ahead Electricity
Market and MINLP. Energy Convers. Manag. 2013, 76, 314–322. [CrossRef]
Zhang, N.; Sutanto, D.; Muttaqi, K.M. A review of topologies of three-port DC–DC converters for the
integration of renewable energy and energy storage system. Renew. Sustain. Energy Rev. 2016, 56, 388–401.
[CrossRef]
Chien, L.J.; Chen, C.C.; Chen, J.F.; Hsieh, Y.P. Novel Three-Port Converter with High-Voltage Gain.
IEEE Trans. Power Electron. 2014, 29, 4693–4703. [CrossRef]
Lai, C.M.; Yang, M.J. A High-Gain Three-Port Power Converter with Fuel Cell, Battery Sources and Stacked
Output for Hybrid Electric Vehicles and DC-Microgrids. Energies 2016, 9, 180. [CrossRef]
Hu, Y.; Xiao, W.; Cao, W.; Ji, B. Three-Port DC–DC Converter for Stand-Alone Photovoltaic Systems.
IEEE Trans. Power Electron. 2015, 30, 3068–3076. [CrossRef]
Energies 2017, 10, 446
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
23 of 23
Wang, Z.; Li, H. An Integrated Three-Port Bidirectional DC-DC Converter for PV Application on a DC
Distribution System. IEEE Trans. Power Electron. 2013, 28, 4612–4624. [CrossRef]
Sun, X.; Shen, Y.; Li, W. A Novel LLC Integrated Three-port DC-DC Converter for Stand-alone PV/Battery
System. In Proceedings of the IEEE Transportation Electrification Conference and Expo, Asia-Pacific, Beijing,
China, 31 August–3 September 2014; pp. 1–6.
Duarte, J.L.; Hendrix, M.; Simões, M.G. Three-Port Bidirectional Converter for Hybrid Fuel Cell Systems.
IEEE Trans. Power Electron. 2007, 22, 480–487. [CrossRef]
Phattanasak, M.; Gavagsaz-Ghoachani, R.; Martin, J.P.; Pierfederici, S. Flatness Based control of an Isolated
Three-port Bidirectional DC-DC converter for a Fuel cell hybrid source. In Proceedings of the IEEE Energy
Conversion Congress and Exposition, Phoenix, AZ, USA, 17–22 September 2011; pp. 977–984.
Fontana, C.; Buja, G.; Bertoluzzo, M.; Kumar, K. Power and control characteristics of an isolated three-port
DC-DC converter under DCM operations. In Proceedings of the Annual Conference of the IEEE Industrial
Electronics Society, Florence, Italy, 24–27 October 2016; pp. 4211–4216.
Phattanasak, M.; Gavagsaz-Ghoachani, R.; Martin, J.P.; Nahid-Mobarakeh, B. Control of a Hybrid Energy
Source Comprising a Fuel Cell and Two Storage Devices Using Isolated Three-Port Bidirectional DC–DC
Converters. IEEE Trans. Ind. Appl. 2015, 51, 491–497. [CrossRef]
Wang, L.; Wang, Z.; Li, H. Asymmetrical Duty Cycle Control and Decoupled Power Flow Design of
a Three-port Bidirectional DC-DC Converter for Fuel Cell Vehicle Application. IEEE Trans. Power Electron.
2012, 27, 891–904. [CrossRef]
Wang, Z.; Liu, B.; Zhang, Y.; Cheng, M.; Chu, K.; Xu, L. The Chaotic-Based Control of Three-Port Isolated
Bidirectional DC/DC Converters for Electric and Hybrid Vehicles. Energies 2016, 9, 83. [CrossRef]
Ling, Z.; Wang, H.; Yan, K.; Gan, J. Optimal Isolation Control of Three-Port Active Converters as a Combined
Charger for Electric Vehicles. Energies 2016, 9, 715. [CrossRef]
Li, X.; Bhat, A.K.S. Analysis and Design of High-Frequency Isolated Duan-Bridge Series Resonant DC/DC
Converter. IEEE Trans. Power Electron. 2010, 25, 850–862.
Krishnaswami, H.; Mohan, N. Three-Port Series-Resonant DC-DC Converter to Interface Renewable Energy
Sources with Bidirectional Load and Energy Storage Ports. IEEE Trans. Power Electron. 2009, 24, 2289–2297.
[CrossRef]
Shreelekha, K.; Arulmozhi, S. Multiport isolated bidirectional DC-DC converter interfacing battery and
supercapacitor for hybrid energy storage application. In Proceedings of the International Conference on
Electrical, Electronics, and Optimization Techiniques, Chennai, India, 3–5 March 2016; pp. 2763–2768.
Tao, H.; Kotsopoulos, A.; Duarte, J.L.; Hendrix, M.A.M. Transformer-Coupled Multiport ZVS Bidirectional
DC–DC Converter with Wide Input Range. IEEE Trans. Power Electron. 2008, 23, 771–781. [CrossRef]
Oggier, G.; Garcia, G.O.; Oliva, A. Switching Control Strategy to Minimize Dual Active Bridge Converter
Losses. IEEE Trans. Power Electron. 2009, 24, 1826–1838. [CrossRef]
Xu, D.; Zhao, C.; Fan, H. A PWM Plus Phase-Shift Control Bidirectional DC-DC Converter. IEEE Trans.
Power Electron. 2004, 19, 666–675. [CrossRef]
Tao, H.; Duarte, J.L.; Hendrix, M.A.M. Three-Port Triple-Half-Bridge Bidirectional Converter with
Zero-Voltage Switching. IEEE Trans. Power Electron. 2008, 23, 782–792.
Baek, J.-B.; Choi, W.-I.; Cho, B.-H. Digital Adaptive Frequency Modulation for Bidirectional DC-DC Converter.
IEEE Trans. Power Electron. 2013, 60, 5167–5176. [CrossRef]
Nandankar, P.V.; Rothe, J. Hihgly efficient discontinuous mode interleaved DC-DC converter. In Proceedings
of the International Conference on Electrical, Electronics, and Optimization Techiniques, Chennai, India,
3–5 March 2016; pp. 476–481.
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