Download stripfet iii and optimal choice of mosfets in high current vrms

AN1730
APPLICATION NOTE
STripFETTM III and optimal choice of MOSFETs
in high current VRMs
M. Melito, G. Belverde
1. ABSTRACT
The need for very high current supplies in modern CPU core power regulation is continuously growing.
Up to now the best approach has been the conventional synchronous buck topology regulator powered
directly from a portable’s battery. It’s simple enough and exhibits very high efficiency if its Power
MOSFET characteristics are well matched to the required currents and switching frequency.
However, if the CPU core current requirements exceed 30A, component costs and thermal problems rise
very suddenly. The main issues to be faced are the high cost of very low on-resistance Power MOSFETs,
the gate drive requirements for this kind of device necessary to minimize switching losses, the heat
sinking of the devices and the necessity of designing and acquiring non standard high current inductors.
In addition the increased switching frequency, needed to support the more demanding requirements in
terms of transient response, leads to efficiency problems.
The multiphase buck converter topologies solve both the performance and economic weakness points of
the single-phase solution.
The total output current is shared among the parallel power channels allowing the use of higher onresistance, lower cost Power MOSFETs and lower current, lower cost inductors. The heat is now spread
out over a larger board area allowing the use of the SMD device without the heatsink required to
dissipate the localized power generated by the single switch in single-phase buck converter.
Using n channels the effective switching frequency is n-times the switching frequency of a single channel
thus reducing the size and cost of the output capacitors and solving the transient specification
requirements.
However the benefits of using the multi phase approach can be wasted if the selection of the Power
MOSFET switches is not well optimized.
2. POWER LOSSES ESTIMATION
The increasing power demand together with supply voltage drop leads to dc-dc converters becoming
more and more inefficient mainly due to increased conduction losses. Efficiency is a key issue. The
power losses associated with the FET’s in a Synchronous Buck converter can be estimated using the
equations shown in Appendix A.
The formulas used give a good approximation, for the sake of performance comparison, of how different
couples of devices affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior depends on how the heat generated inside the
devices is drained out to allow a safe working junction temperature. The thermal resistance between the
junction and the printed board
is
a
key parameter for the final efficiency because of the
temperature dependent parameters (RDS(on), Qrr…) involved.
Table I compares the thermal performances of several packages and it can be used as a starting point for
choosing the right device. To avoid overheating the power MOSFETs a realistic evaluation of the thermal
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AN1730 - APPLICATION NOTE
resistance is mandatory. Several aspects have to be considered because the thermal resistance values
used in the data sheet refers to a well defined external environment that is generally very different from
the final application one.
It must be taken into account the real copper area that performs the most part of the power dissipation.
The presence of nearby components and spaces together with the airflow distribution greatly affects the
real value of the thermal resistance. The use of paralleled devices reduces the heat generation by
reducing the power losses but it has not much influence on power dissipation if not enough copper area
is available.
Figure 1: BUCK Converter Simplified Schematic and Waveforms
/
6:
9
LQ
+
-
9
C
&RQWURO
,&
R
6:
TS
ton
Vgs(SW1)
δTS
toff
(1−δ)TS
Vgs(SW2)
dead time
ISW1
IL
ISW2
ID_SW2
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IL
IL
AN1730 - APPLICATION NOTE
Table 1: Typical Thermal Resistance of MOSFET Packages
PACKAGE
RJA(OC/W)
Minimum footprint
RJC(OC/W)
62
42
90
100
85
85
RJA(OC/W)
2
1 inch of 2oz
COPPER
50
34
50
50
42
42
DPACK
2
D PACK
SOT-223
SO-8
PowerSO-8
Reverse
PowerSO-8
PowerFLAT
PowerSO-10
50
50
35
35
1.8
0.8
1.25
1
*
1.8
1.8
*The RJC value is not useful for this kind of packages in typical applications.
3. DEVICES SELECTION
The right choice of the switches is fundamental to reach the maximum power efficiency. The switching
and conduction losses due to the step-down conversion are both critical even if the weights are different
for the upper and lower devices. In typical conditions the resulting duty factor is lower than 15% meaning
the low-side FET is conducting the other 85% of the time. Moreover I2R conduction losses increase as
the square of the current, which explains the sudden drop-off in efficiency as output current increases.
Besides the low side switch works in zero voltage condition during both turn-on and turn-off. As a
consequence each one of the two switches is required to have different characteristic for efficiency
maximization.
The high-side Power MOSFET selection is the simpler choice, as it is very stressed due to both switching
losses and conduction losses. So the best FOM (Ron*Qg) is desirable.
First-order switching losses depend on how fast the gate-driver current can charge/discharge the Power
MOSFET input capacitance. Switching losses are dependent on many variables, including Power
MOSFET source inductance, internal gate resistance, and the effect of internal gate layout on the
propagation of the gate-drive signal through the die. We must also take into account the external gatedriver current sourcing and sinking capability, Miller capacitance, and stray inductance induced by circuit
board layout. As the switching frequency increases became more important the role of the switching
losses due to the minority-carrier recombination in the freewheeling diode of the lower switch. The
contribution of the output capacitance becomes not negligible too.
Due to the small duty factor conduction losses in the high-side Power MOSFET are less important, so die
sizes can be made much smaller than those of the low-side one. The resulting smaller die size leads to
reducing parasitic capacitances and so switching losses.
Switching losses are less important for the low-side Power MOSFET because of zero voltage switching.
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AN1730 - APPLICATION NOTE
The consequence is that RDS(on) in a CPU supply low side Power MOSFET is the main parameter that
must be minimized. Losses due to Qrr of the internal diode are to be taken in account if the switching
frequency becomes considerably high (typically several hundreds kHz). The contribution of the output
capacitance and of the gate charge has to be taken into account too. In addition the low side switch has
to be extremely rugged to avoid efficiency degradation or even device failure due to cross conduction
during the high side turn-on.
Summarizing the switch characteristics, the low side device requires:
- Very low Rds(on) to reduce conduction losses
- Small Qg to reduce the gate charge losses
- Small Co to reduce losses due to output capacitance
- Small Qrr to reduce losses on SW1 during its turn-on
- The Cgd/Cgs ratio lower than Vth/Vgg ratio expecially with low
drain to source voltage to avoid the cross conduction phenomenon;
the high side device requires:
- Small Rg and Ls to allow higher gate current peak and to limit
the voltage feedback on the gate
- Small Qg to have a faster commutation and to reduce gate charge losses
- Low R DS(on) to reduce the conduction losses.
4. EXPERIMENTAL RESULTS
Based on some typical VRM (Voltage Regulator Module) specifications, shown in the table II, some
investigations have been made to find the best solutions in terms of number of phases and also number
of devices to be paralleled. Such investigation deals with the task of finding the optimal pair of devices
and number of phases. The switching frequency is around 300 KHz. The total output current is 70 A. We
have opted for building a single phase VRM using the optimal devices found by using theoretical
simulation techniques. The main characteristics of the compared device are summarized in Table III.
Table IV resumes the different couples of devices tested.
Table 2: VRM Target Specifications
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Vin
[V]
Vout
[V]
Iout
[A]
Frequency
[KHz]
Total
Phases
MOSFETs
per phase
12
1.5
70
300
2-3
TBD
AN1730 - APPLICATION NOTE
Table 3: Main Characteristics of the Tested Devices
Ron[mΩ] Qg[nC]
STD38NH02L
STD90NH02L
STD100NH02L
STB70NF03L
STB90NF03L
11.0
5.0
3.6
8.0
5.6
18
47
62
35
60
Ron*Qg Qsw Qgd Coss Qrr Rg Package
[mΩ *?nC] [nC] [nC] [pF] [nC] [Ω]
198.00
4.5
2.5
305
22
1.0 DPACK
235.00
12
7
800
35
1.0 DPACK
223.20
14
8
1020 58
1.1 DPACK
280.00
11
10
490
90 NA D2 PACK
336.00
25
18
860 110 NA D2 PACK
Table 4: Tested Boards
Board A
Boar d B
Board C
Boar d D
high-side
STB70NF03L
STD38NH02L
STD38NH02L
2 x STD38NH02L
low-si de
STB90NF03L
2 x STD90NH02L
STD100NH02L
2 x STD100NH02L
The devices performances have been tested in a DC-DC step down buck converter. The converter used
for drawing efficiency curves and measuring temperatures is single-phase and its schematic is shown in
figure 2. It represents only the power stage of VRM. It’s basically one phase of the total converter that can
be realized by both two and three phases. Output voltage Vout is regulated manually and the board
exhibits no voltage feedback. The overall efficiency has been measured and is given in figure 3.
Figure 2: Single-phase Simplified Schematic
DRIVER
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AN1730 - APPLICATION NOTE
Figure 3: Efficiency Comparison
88.00
86.00
efficiency [%]
84.00
82.00
STB70NF03L
80.00
STB90NF03L
STD38NH02L 2x STD90NH02L
STD38NH02L STD100NH02L
78.00
STD38NH02L 2x STD100NH02L
76.00
0
5
10
15
20
25
30
35
40
45
50
Output Current [A]
The obtained results can be helpful when choosing the most suitable configuration in terms of number of
phases and of number of devices to be connected in parallel.
As an example, referring to figure 3, and assuming the minimum efficiency should be greater than 86%
@ 70A the target specification reported in Table II can be satisfied choosing a two phases converter
(board B or board D configuration) or a three phases one (board C). The three phases solution has
efficiency a little bit better over the whole range. However the final decision has to take into account the
overall number of switches and drivers together with the available copper space for power dissipation
optimization.
Figure 4: Extrapolated Efficiencies Comparison
88.00
efficiency [%]
86.00
84.00
82.00
2 phases board B
80.00
3 phases board C
2 phases board D
78.00
76.00
0
10
20
30
40
50
Total Output Current [A]
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AN1730 - APPLICATION NOTE
5. CONCLUSION
Power efficiency in high performances dc-dc converters is tied to Power MOSFET choice. Even if the
multiphase approach allows improving dc-dc performances at a reasonable cost it is mandatory the
choice of dedicated Power MOSFET for the high-side switch and the low-side one. Thermal
management plays a crucial role in choosing the converter configuration in terms of number of phases
and of number of devices to put in parallel.
Moreover additional parameters have to be taken into account as the operating frequency increases. The
contribution of the recovery charge of the lower switch diode and the output capacitance of both increase
significantly the power losses.
APPENDIX A
According to the simplified schematic and waveforms reported in Fig. 1, and the gate charge curve
reported in Fig. 5, note that SW1 refers to the high side transistor in the buck converter, SW2 refers to the
synchronous rectifier transistor and D is the body diode of SW2.
Table 5: Power Losses Evaluation Formulas for a BUCK Converter
Pconduction
Pswitching
Pdiode
High Side Switch
Low Side Switch
R DS(on)SW1 * I 2L * δ
R DS(on)SW2 * I 2L * (1 − δ )
Vin * (Qgs2(SW1) + Q gd(SW1) ) * f *
Recovery
Not Applicable
Conduction
Not Applicable
IL
Ig
Zero Voltage Switching
1
Vin * Q rr(SW2) * f
Vf(SW2) * I L * t deadtime * f
Pgate(Q G )
Q G(SW1) * Vgg * f
PCo(Qoss)
Vin * Qoss(SW1) * f
Vin * Q oss(SW2) * f
2
2
2
Q G(SW2) * Vgg * f
1
Dissipated by SW1 during turn-on.
2
QG(SW2) is the charge supplied to the gate when SW2 woks as synchronous rectifier.
δ is the duty-cycle;
Pconduction =>losses during the on state;
Pswitching =>losses during the on-off transitions;
Pdiode
=>losses due to diode during conduction and during the reverse recovery;
Pgate
=>losses due to gate;
PCo (Qoss)
=>losses due to the output parasitic capacitance;
tdeadtime.
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Figure 5: simplified switching waveforms
Drain Current
Gate Voltage
VGS(th)
QG
W
S1
QG
t1
S2
QG
t2
D
t3
Drain Voltage
QSW
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