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TI Comparator Based Low Power 6-bit Flash ADC in 0.25micron
CMOS
A.Tangel, J. Yoo, and K. Choi
Abstract: This paper presents design and performance of an ultrafast System-On-Chip
suitable 6-bit CMOS Flash ADC with 0.25 m generic CMOS technology. The analog part of
a traditional Flash structure is replaced by the so called threshold inverter comparator array.
The resulting 6-bit ADC operates with 1GSPS, dissipates 66.87 mW of power at 2.5 V, and
occupies 0.013 mm2 layout area.
Introduction: Ultrafast A/D converters are needed for portable wireless devices that use the
radio frequency (RF) for networking. There are primarily four different high speed ADC
architectures in the literature; the full-flash, the semi-flash, the pipeline, and the
folding&interpolating ADCs. The full-flash type of ADC is the most attractive solution for
being the fastest among others. However it is limited to lower resolution levels due to a large
number of comparators (requiring 2n-1 comparators for an n-bit ADC). On the other hand, the
pipeline ADC is more suitable for higher resolution, requiring only n-stages for an n-bit ADC
[1].
The speed of an ADC is also affected by the technology used. It is clear that GaAs technology
will be much more faster than the CMOS and the Bipolar [2,3,4,5]. However the current
GaAs technology is not compatible with the silicon based CMOS technology, which makes it
very difficult to realize the single-chip system solution. For this reason, the authors propose
an ultrafast CMOS flash ADC based on the Threshold Inverter Comparator technique [6],
[7],[8].
The idea is to use the digital inverter as an internally-set analog voltage comparator. This
eliminates the need for high-gain differential input voltage comparators that are inherently
more complex and slower than the digital inverters. It also eliminates the need of reference
voltages requiring a resistor ladder circuit. Morover, it allows a complete high-speed ADC to
be implemented using the standard CMOS logic technology, making the featured ADC ideal
for SOC implementation.
Threshold Inverter Comparator: The inverter switching threshold voltage Vm is internal to
the inverter, fixed by the transistor sizes. The inverter switching threshold voltage Vm is
defined at Vin=Vout point on the voltage transfer characteristic curve of an inverter. The
authors obtained the equally spaced inverter switching threshold voltages between maximum
Vm (comparator 63 in Figure 1) and minimum Vm (comparator 1 in Figure 1) by
systematically changing the transistor sizes through the modern VLSI CAD tools. Simulation
was performed using 0.25 m standard CMOS technology parameters. The DC analysis of the
63 TIQ comparator outputs is shown in Figure 2. One may notice the uniformity of 63 equally
spaced inverter voltage transfer curves.
Complete ADC: Threshold Inverter comparator array outputs are sent to the gain boosting
circuitry which consist of two small-sized cascading identical inverters to obtain sharper
thresholding of comparator output and to provide full digital output voltage swing. Therefore,
the thermometer code output is obtained in the analog part of the complete A/D converter as
shown in Figure 1. The encoder then converts the thermometer code to the binary code in two
steps. Firstly, the thermometer code is converted to the 1-out-of-n code. Secondly, this code is
converted to the binary code [6].
Since the main draw back of this proposed idea is the effect of process parameter variations,
the transient analysis is based on at least 5-different transistor Spice model parameters
obtained from the vendor. Figure 3 shows the related transient analysis results for the
complete ADC outputs.
Results and conclusion: All results of five different process parameters are similar to that of
the first one (n94s), the original design model parameters. As one can see in Figure 3, all
results show correct operation without any missing codes at 1GSPS rate. However the authors
found shifting and expanding (or contracting) in the A/D converter operation voltage ranges
shown in Table 1. To tolerate the process parameter variation, one may add a front end
trimming (or signal conditioning) circuitry to the signal input, thereby adjusting signal offset
and amplitude. Table 2 includes the summary of simulation results for the complete 6-bit A/D
converter. Table 3 compares the proposed ADC with other A/D converters from the literature
[4],[9],[10],[11].
In conclusion, the TI comparator based A/D converters are preferable for SOC
implementation. Also it is highly adaptable to future CMOS technology development, going
to smaller feature size and low power supply voltage.
References
1 Wang, Y. T., and Razavi, B.: ’An 8-Bit 150MHz CMOS A/D Converter’, IEEE Journal of
Solid State Circuits, March 2000, 35(3), pp. 308-317
2 Broekkaert, B., Brar, B., Wagt, van der, Seabaugh, A., Moise, T., Morris, F., and Frazier,
G.: ‘A Monolithic 4 Bit 2 GSps Resonant Tunneling Analog-to-Digital Converter’, Gallium
Arsenide Integrated Circuit Symposium, 1997, pp. 187-190
3 Sheng, N., Yu, R., Chang, C., Gutierrez, G. And Wagt, P.V. der: ‘A 10-Bit, 500 MS/S
Analog-to-Digital Converter’, IEEE MTT-S Digest, 1999, pp. 197-200
4 Singh, J.: ‘High Speed Multi-Channel Data Acquisition Chip’, IEEE International
Conference on Electronics, Circuits and Systems, 1998, volume 1, pp. 401-404
5 Thomas, F., Debrie, F., Gloanec, M., Paih, M. L., Martin, P., Nguyen, T., and Ruggeri,
S.:’1-GHz GA As ADC Building Blocks’, IEEE Journal of Solis State Circuits, April 1989,
24(2), pp. 223-228
6 Yoo, J., Choi, K. and Tangel, A.: ‘ 1-GSPS CMOS Flash Analog-to-Digital Converter for
System-on-Chip Applications’, Proc. IEEE Computer Society Workshop on VLSI, April
2001, pp.135-139
7 Yoo, J., Lee, D., Choi, K. and Tangel, A.: ‘ Future Ready Ultrafast 8-bit CMOS ADC for
System-on-Chip Applications’ 14th Annual IEEE International ASIC/SOC Conference, Sept.
2001, pp. 789-793
8 Tangel, A., Choi, K.: ‘The CMOS Inverter as a comparator in ADC designs’, International
Conference on Electrical and Electronics Engineering (ELECO 2001), Nov. 2001, pp. 1-5
9 Dalton, D, Spalding, G. J., Reyhani, H., Murphy, T., Deevy, K., Walsh, M., and Griffin, P.:
‘A 200-MSPS 6-Bit Flash ADC in 0.6-m CMOS’, IEEE Transactions on Circuit and
Systems, November 1998, 45(11), pp. 1433-1444
10 Tamba, Y., and Yamakido, K.: ’A CMOS 6b 500 Msample/s ADC for a Hard Disk Drive
Read Channel’, IEEE International Solid-State Circuits Conference, 1999, pp. 324-325
11 Yoon, K., Park, S., and Kim, W.: ’A 6b 500Msample/s CMOS Flash ADC with a
Background Interpolated Auto-Zeroing Technique’, IEEE International Solid-State Circuits
Conference, 1999, pp. 326-327
Authors’ affiliations:
A. Tangel (Department of Electronics&Communication Engineering, University of Kocaeli,
Veziroglu Kampusu 41040 Izmit, TURKEY)
Email: [email protected]
J. Yoo and K. Choi (Department of Computer Science&Engineering, The Pennsylvania State
University, University Park PA16802 USA)
Email: {jyoo,kyusun}@cse.psu.edu
Figure captions:
Fig. 1 Block Diagram of the proposed TI based 6-bit flash A/D converter
Fig. 2 DC Analysis of the 63 TI comparator outputs
Fig. 3 Transient analysis for 6 processes
Table 1 The change of A/D converter operation voltage ranges due to process variation
Table 2 Simulation results for the 6-bit A/D converter
Table 3 The comparison of the proposed 6-bit ADC with other ADCs
Figure 1
Figure 2
Figure 3
Table 1
Process
Start Vm
End Vm
Range
Avg. LSB
Max. power Avg power
N94S
0.6815V
1.4999V
0.8184V
13.2mV
66.87mW
44.35mW
N99W
0.6911V
1.5030V
0.8119V
13.1mV
64.53mW
40.46mW
N99Y
0.6819V
1.4808V
0.7989V
12.9mV
65.97mW
41.57mW
N9BM
0.6984V
1.4983V
0.7999V
12.9mV
65.30mW
41.70mW
T02B
0.6874V
1.5288V
0.8414V
13.6mV
72.29mW
46.51mW
T02D
0.6955V
1.5188V
0.8233V
13.3mV
71.48mW
45.29mW
Table 2
CMOS technology
0.25m
Power supply
2.5V
Speed
1GPS
Area
0.013mm2
Avg. Power consumption
44.34mW
Max.power consumtion
66.87mW
Analog input range
0.6815V-1.499V
1LSB distance
13.2mV
Table 3
ADCs
Resolution
Sampling
Technology
rate
Gate
Architecture
Power
Length
Proposed
6-bit
1GSPS
CMOS
0.25
Flash
66.87mW
[2]
6-bit
2GSPS
GaAs
0.5
Flash
970mW
[9]
6-bit
0.2GSPS
CMOS
0.6
Flash
380mW
[4]
4-bit
1.18GSPS
GaAs
0.8
Flash
185.6mW
[10]
6-bit
0.5GSPS
CMOS
0.4
Flash
400mW
[11]
6-bit
0.5GSPS
CMOS
0.6
Flash
330mW