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Proc. Int. Conf. on Control System and Power Electronics, CSPE A New Topology for Mitigating the Common Mode Voltage in Medium Voltage Induction Motor Drives Dr. Venkata Reddy Kota, Mr. B. S. S. G. Pardhu University College of Engineering Kakinada (A), Jawaharlal Nehru Technological University Kakinada, Kakinada-533003, Andhra Pradesh, India. [email protected], [email protected] Abstract. In squirrel cage induction-motor (SQIM) drives, the motors are normally fed with pulse width modulated (PWM) voltages which cause spike (dv/dt) across the motor terminals. This may lead to insulation failure and damage of motor due to common mode voltage across the winding. This paper proposes a new topology for medium voltage IM drives with series connected three-level inverters to decrease dv/dtby increasing number of steps in the applied voltage. This paper also clearly explains the PWM control strategies for series connected inverters. The proposed series connected inverter topology for a squirrel cage induction motor is developed and simulated in MATLAB®/Simulink. The simulation results show the reduction in common mode voltages and validate the applicability of proposed topology for medium voltage induction motor drives. Keywords: Common-mode Voltages, Series connected Inverters, Squirrel cage Induction motor, Pulse width modulation, Harmonic reduction. 1 Introduction Induction motors are being used extensively in applications requiring fast and accurate control of speed and position. It is widely known that induction motors are robust, more reliable and require little maintenance. These are normally fed by the PWM converters. The PWM inverters generate common-mode voltages and can have very a high dv/dtrate [1]. Due to common mode voltages “motor bearing failure” and “motor winding insulation breakdown” occurs [2][3]. This problem can be eliminated by applying the multi-level voltages to the motor. A number of techniques have been suggested tos reduce or eliminate the common-mode voltages, generated by the various configurations of multilevel inverters. Multilevel converters are considered today as the state-of-the-art power-conversion systems [4] for high-power and power-quality demanding applications. Multilevel voltage profiles can also be obtained by using higher order neutral-pointclamped (NPC) multilevel inverters [10] or by cascading a number of two-level inverters [8][9]. However, these multilevel NPC inverters suffer from dc-bus imbalance [5][6][7], and unequal ratings of the clamped diodes [11] etc., which are not very serious problems for inverters with three level or lower. With the Flying capacitor © Elsevier, 2012 525 inverter it requires a huge number of capacitors. The clamping capacitor must be setup with the required voltage level. So, there is a necessity of initialization of the converter [11]. With the cascaded H-bridge it needs separate dc sources. Need to provide separate isolated dc supplies for each full-bridge converter. This paper proposes a new topology with series connected three level inverters for medium voltage induction motors which decrease dv/dtby increasing number of steps in the applied voltage. In the proposed topology, the power circuit is flexible in structure, and hence, the number of modules to be connected in series depends on the power of the drive. In this paper, the proposed topology and its sinusoidal pulse width modulation control strategies are implemented and simulated in MATLAB®/Simulink. The simulation results are presented for the series connected three level inverter topology for medium voltage squirrel cage induction motor drive applications. 2 Proposed converter topology The proposed topology, shown in Fig.1, contains four NPC three level inverters. The output voltage of each inverter is connected to the transformers which are connected in series to produce multilevel output voltage in order to reduce the high dv/dt in output voltage. The generation of gate pulses for each of three-level inverter module is based on sinusoidal pulse width modulation (SPWM) with Phase opposition Dispassion (POD) method. The generation of modulating waves for the series connected inverters is explained in the following section. Fig. 1 Block diagram for the Proposed Converter Topology If “Vdc” is the dc-bus voltage of each inverter module, “α” is the turns ratio of each transformer and “n” is the number of inverter modules then for sinusoidal PWM (SPWM) strategy; the motor rms phase voltage (VPh) can be expressed as: ℎ = √3 ∝ (1) √ where ‘m’ is modulation index of the inverter topology (In this work, m=1). 526 Modulation Index (m) of the inverter is given by = !" (2) # 3 Generation of modulating waves for proposed topology The basic principle of gate pulse generation for inverters is based on the SPWM method with the reference of following equations. (3) = $ sin(% ) The Fig. 2 shows the modulating signals corresponding to all four inverters which are extracted from the reference modulating wave. The modulating signals corresponding to all four inverters can be expressed as given below. (4) The modulating signal of inverter 1, & (' ) = & * (' ) + & , (' ) 1 & 0 ≤ % < sin?& 8@: ⎧2456787: 9 ⎪ & & Where & * (' ) = 1 sin?& 8@: ≤ % < B − sin?& 8@: ⎨ & ⎪ C?17 B − sin?& 8 : ≤ % < B @ ⎩ 2456789: ( ) ( ) and & , ' = −& * ' − B The modulating signal of inverter 2, (' ) = * (' ) + , (' ) (5) & sin?& 8@: 0 0 ≤ % < ⎧ ⎪ 1?24567(7) & & 9 sin?& 8 : ≤ % < sin?& 8 : ⎪ 24567(7)?24567 7 @ 8 : # 9 ⎪ & & sin?& 8 : ≤ % < B − sin?& 8 : Where * (' ) = 1 ⎨ 7 67 ⎪ C?(1D245 (9)) ?& 8&: ?& 8&: ≤ % < B − sin B − sin @ ⎪24567(7#)?24567879: ⎪ & 0 B − sin?& 8 : ≤ % < B ⎩ @ and , (' ) = − * (' − B) The modulating signal of inverter 3, E (' ) = E * (' ) + E , (' ) (6) & 0 0 ≤ % < sin?& 8 : ⎧ ⎪ 1?24567(7) & E # sin?& 8 : ≤ % < sin?& 8 : ⎪ 67 F 7 @ 245 ( )?245678 : 9 # ⎪ E E ?& ?& 1 sin 8 : ≤ % < B − sin 8 : Where E * (' ) = @ @ ⎨ 67 7 ⎪ C?(1D245 (#)) ?& 8E: ?& 8&: ≤ % < B − sin B − sin @ ⎪ 24567(F9)?2456787#: ⎪ & 0 B − sin?& 8 : ≤ % < B ⎩ and E , (' ) = −E * (' − B) The modulating signal of inverter 4, @ (' ) = @ * (' ) + @ , (' ) (7) 527 ⎧ ⎪ E 0 ≤ % < sin?& 8 : 0 @ E sin?& 8 : @ E sin?& 8 : @ ≤ % < B − Where@ * (' ) = sin(% ) ⎨ E ⎪ 0 B − sin?& 8 : ≤ % < B ⎩ @ and @ , (' ) = −@ * (' − B) From eq. (4) - (7), it can be observed that the summation of the all the modulation waves at any point of time is equals to the reference modulating wave (Vr). = & + + E + @ (8) Fig. 2 Modulating waves for the four series connected inverters 4 Simulation Results The proposed converter topology with four series connected three-level inverters for a medium voltage SQIM is developed and simulated in Matlab/Simulink. The Fig. 3 shows the line voltage and harmonic spectrum of each inverter.Fig. 4 depicts the output phase voltage of the proposed converter and the harmonic spectrum corresponding to the DC voltage of 600V for each converter. From the Fig.4, it can be observed that the proposed converter generates a better output voltage with a peak value of 2077 V and THD of only 8.66%. The common mode voltage (CMV) can be expressed as (DHD) G = (9) E Where V ao, Vbo and Vco are the phase voltages of inverters. Fig. 5 shows the common mode voltage with the proposed topology which is very small (<130V) compared to a single three level inverter (400V). The common mode voltage with different topologies of same rating is summarized in the table 1. From table 1, it can be observed that the proposed topology produces very less common mode voltage. 528 Fig. 3 Line voltage and harmonic spectrum of a) Inverter 1, b) Inverter 2, c) Inverter 3 and d) Inverter 4 Fig. 4 Phase voltage and harmonic spectrum of the output voltage 529 Fig.5 Common mode voltage with the proposed topology Table 1: Comparison of CMV with different topologies Single ThreeLevel Inverter Series connection of three 3Level Inverters Series connection of four 3Level Inverters Single 5Level Inverter Single 9Level Inverter % THD 33.62 % 12.22 % 8.66 % 7.89 % 4.71 % Peak Voltage 2092 Volts 2073Volts 2077 Volts 2059 V 2065 V RMS Voltage 1479.5 Volts 1466 Volts 1468 Volts 1456 V 1460 V CMV 400 Volts 150 Volts 120 Volts 200 Volts 135 Volts A squirrel cage induction motor is connected to the proposed converter to validate the applicability. The Fig. 6 depicts the phase current, speed and torque developed by the proposed converter fed, medium voltage SQIM for a reference torque of 50 N-m applied at time 1 sec. Fig. 6 Current, Speed and Torque of SQIM with step change in load 530 5 Conclusion In this paper, a series connection of three-level inverters has been proposed for a medium-voltage SQIM drives with reduction of common mode voltages and decreasing the high dv/dt with increasing the number of steps in output voltage. The proposed topology has low voltage stress and low total harmonic distortion. The huge requirements of components with different ratings are eliminated and the dc bus imbalance problem will not present in this topology. The proposed inverter topology output consists of number of steps, which leads to increase the life of the motor due to decrease in dv/dt. This proposed method has an advantage even if one inverter module is failure then the topology works with reduced power level. The proposed topology for a medium voltage SQIM drive is simulated in Matlab/Simulink environment and the results validate applicability of the proposed scheme. References 1. S. Chen and T. A. Lipo, “Bearing currents and shaft voltages of an induction motor under hard- and soft-switching inverter excitation,” IEEE Trans. Ind. Appl., vol. 34, no. 5, pp. 1042–1048, Sep./Oct. 1998. 2. P. K. Chaturvedi, Shailendra Jain, and PramodAgarwal, “A study of neutral Point and Common Mode Voltage Control in Multileval SPWM Technique”, Fifteenth national Power Systems Conference (NPSC), IIT Bombay, India, December 2008, pp 518-523 3. L. M. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44, Jan./Feb. 1999. 4. J Rodriguez, L G Franquelo, S Kouro, J I Leon, R C Portillo, M A M Prats, M A Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications” IEEE Trans. Appl., vol. 97, no. 11, pp. 1786–1817, Nov 2009. 5. C. Newton and M. Summer, “Novel technique for maintaining balanced internal DC link voltages in diode-clamped five-level inverters,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 146, no. 3, pp. 341–349, May 1999. 6. N. S. Choi, J. G. Cho, and G. H. Cho, “A general circuit topology of multilevel inverter,” in Proc. 22nd Annu. IEEE Conf. ESC, Jun. 24–27, 1991, pp. 96–103. 7. M. Marchesoni and P. Tenca, “Diode-clamped multilevel converters: A practicable way to balance DC-link voltages,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 752–765, Aug. 2002. 8. P.W. Hammond, “A new approach to enhanced power quality for medium voltage drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208, Jan./Feb. 1997. 9. R. Teodorescu, F. Blaabjerg, J. K. Pederson, E. Cengelci, and P. N. Enjeti, “Multilevel inverter by cascading industrial VSI,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 832–838, Aug. 2002. 10.A. Nabae, I. Takahashi, and H. Akagi, “A new neutral point clamped inverter,” IEEE Trans. Ind. Appl., vol. 17, no. 5, pp. 518–523, Sep./Oct. 1981. 11.G. Cararra, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A new multilevel PWM method: A theoretical analysis,” IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497–505, Jul. 1992. 531